Lines Matching +full:0 +full:xeb4
53 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92ee_phy_query_bb_reg()
143 u8 rfpi_enable = 0; in _rtl92ee_phy_rf_serial_read()
146 offset &= 0xff; in _rtl92ee_phy_rf_serial_read()
150 return 0xFFFFFFFF; in _rtl92ee_phy_rf_serial_read()
176 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92ee_phy_rf_serial_read()
195 offset &= 0xff; in _rtl92ee_phy_rf_serial_write()
197 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92ee_phy_rf_serial_write()
200 "RFW-%d Addr[0x%x]=0x%x\n", rfpath, in _rtl92ee_phy_rf_serial_write()
227 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92ee_phy_bb_config()
234 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92ee_phy_bb_config()
236 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl92ee_phy_bb_config()
237 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl92ee_phy_bb_config()
241 crystal_cap = rtlpriv->efuse.eeprom_crystalcap & 0x3F; in rtl92ee_phy_bb_config()
242 rtl_set_bbreg(hw, REG_MAC_PHY_CTRL, 0xFFF000, in rtl92ee_phy_bb_config()
259 u32 _platform = 0x08;/*SupportPlatform */ in _check_condition()
262 if (condition == 0xCDCDCDCD) in _check_condition()
265 cond = condition & 0xFF; in _check_condition()
266 if ((_board != cond) && (cond != 0xFF)) in _check_condition()
269 cond = condition & 0xFF00; in _check_condition()
271 if ((_interface & cond) == 0 && cond != 0x07) in _check_condition()
274 cond = condition & 0xFF0000; in _check_condition()
276 if ((_platform & cond) == 0 && cond != 0x0F) in _check_condition()
285 if (addr == 0xfe || addr == 0xffe) { in _rtl92ee_config_rf_reg()
291 if (addr == 0xb6) { in _rtl92ee_config_rf_reg()
293 u8 count = 0; in _rtl92ee_config_rf_reg()
310 if (addr == 0xb2) { in _rtl92ee_config_rf_reg()
312 u8 count = 0; in _rtl92ee_config_rf_reg()
322 rtl_set_rfreg(hw, rfpath, 0x18, in _rtl92ee_config_rf_reg()
323 RFREG_OFFSET_MASK, 0x0fc07); in _rtl92ee_config_rf_reg()
337 u32 content = 0x1000; /*RF Content: radio_a_txt*/ in _rtl92ee_config_rf_radio_a()
338 u32 maskforphyset = (u32)(content & 0xE000); in _rtl92ee_config_rf_radio_a()
347 u32 content = 0x1001; /*RF Content: radio_b_txt*/ in _rtl92ee_config_rf_radio_b()
348 u32 maskforphyset = (u32)(content & 0xE000); in _rtl92ee_config_rf_radio_b()
357 if (addr == 0xfe) in _rtl92ee_config_bb_reg()
359 else if (addr == 0xfd) in _rtl92ee_config_bb_reg()
361 else if (addr == 0xfc) in _rtl92ee_config_bb_reg()
363 else if (addr == 0xfb) in _rtl92ee_config_bb_reg()
365 else if (addr == 0xfa) in _rtl92ee_config_bb_reg()
367 else if (addr == 0xf9) in _rtl92ee_config_bb_reg()
380 u8 band = BAND_ON_2_4G, rf = 0, txnum = 0, sec = 0; in _rtl92ee_phy_init_tx_power_by_rate()
387 [band][rf][txnum][sec] = 0; in _rtl92ee_phy_init_tx_power_by_rate()
407 rtlphy->txpwr_by_rate_base_24g[path][txnum][0] = value; in _rtl92ee_phy_set_txpower_by_rate_base()
436 u8 value = 0; in _rtl92ee_phy_get_txpower_by_rate_base()
441 return 0; in _rtl92ee_phy_get_txpower_by_rate_base()
447 value = rtlphy->txpwr_by_rate_base_24g[path][txnum][0]; in _rtl92ee_phy_get_txpower_by_rate_base()
475 u16 raw = 0; in _rtl92ee_phy_store_txpower_by_rate_base()
476 u8 base = 0, path = 0; in _rtl92ee_phy_store_txpower_by_rate_base()
482 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
483 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
489 [BAND_ON_2_4G][path][RF_1TX][3] >> 0) & in _rtl92ee_phy_store_txpower_by_rate_base()
490 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
491 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
497 [BAND_ON_2_4G][path][RF_1TX][1] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
498 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
503 [BAND_ON_2_4G][path][RF_1TX][5] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
504 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
510 [BAND_ON_2_4G][path][RF_2TX][7] >> 24) & 0xFF; in _rtl92ee_phy_store_txpower_by_rate_base()
511 base = (raw >> 4) * 10 + (raw & 0xF); in _rtl92ee_phy_store_txpower_by_rate_base()
521 s8 i = 0; in _phy_convert_txpower_dbm_to_relative_value()
522 u8 tmp = 0; in _phy_convert_txpower_dbm_to_relative_value()
523 u32 temp_data = 0; in _phy_convert_txpower_dbm_to_relative_value()
525 for (i = 3; i >= 0; --i) { in _phy_convert_txpower_dbm_to_relative_value()
528 tmp = (u8)(*data >> (i * 8)) & 0xF; in _phy_convert_txpower_dbm_to_relative_value()
529 tmp += ((u8)((*data >> (i * 8 + 4)) & 0xF)) * 10; in _phy_convert_txpower_dbm_to_relative_value()
534 tmp = (u8)(*data >> (i * 8)) & 0xFF; in _phy_convert_txpower_dbm_to_relative_value()
546 u8 base = 0, rf = 0, band = BAND_ON_2_4G; in phy_convert_txpwr_dbm_to_rel_val()
568 0, 0, base); in phy_convert_txpwr_dbm_to_rel_val()
577 &rtlphy->tx_power_by_rate_offset[band][rf][RF_1TX][0], in phy_convert_txpwr_dbm_to_rel_val()
578 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
581 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
588 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
591 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
598 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
602 0, 3, base); in phy_convert_txpwr_dbm_to_rel_val()
630 rtlphy->pwrgroup_cnt = 0; in _rtl92ee_phy_bb8192ee_config_parafile()
646 0x200)); in _rtl92ee_phy_bb8192ee_config_parafile()
663 for (i = 0; i < arraylength; i = i + 2) in _rtl92ee_phy_config_mac_with_headerfile()
673 } while (0)
682 u32 v1 = 0, v2 = 0; in phy_config_bb_with_hdr_file()
688 for (i = 0; i < len; i = i + 2) { in phy_config_bb_with_hdr_file()
691 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_hdr_file()
701 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
702 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
703 v2 != 0xCDCD && i < len - 2) { in phy_config_bb_with_hdr_file()
712 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
713 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
714 v2 != 0xCDCD && i < len - 2) { in phy_config_bb_with_hdr_file()
720 while (v2 != 0xDEAD && i < len - 2) in phy_config_bb_with_hdr_file()
729 for (i = 0; i < len; i = i + 2) { in phy_config_bb_with_hdr_file()
732 if (v1 < 0xCDCDCDCD) { in phy_config_bb_with_hdr_file()
745 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
746 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
747 v2 != 0xCDCD && in phy_config_bb_with_hdr_file()
757 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
758 v2 != 0xCDEF && in phy_config_bb_with_hdr_file()
759 v2 != 0xCDCD && in phy_config_bb_with_hdr_file()
769 while (v2 != 0xDEAD && in phy_config_bb_with_hdr_file()
776 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", in phy_config_bb_with_hdr_file()
786 u8 index = 0; in _rtl92ee_get_rate_section_index()
791 index = 0; in _rtl92ee_get_rate_section_index()
821 regaddr &= 0xFFF; in _rtl92ee_get_rate_section_index()
822 if (regaddr >= 0xC20 && regaddr <= 0xC4C) in _rtl92ee_get_rate_section_index()
823 index = (u8)((regaddr - 0xC20) / 4); in _rtl92ee_get_rate_section_index()
824 else if (regaddr >= 0xE20 && regaddr <= 0xE4C) in _rtl92ee_get_rate_section_index()
825 index = (u8)((regaddr - 0xE20) / 4); in _rtl92ee_get_rate_section_index()
866 u32 v1 = 0, v2 = 0, v3 = 0, v4 = 0, v5 = 0, v6 = 0; in phy_config_bb_with_pghdrfile()
872 for (i = 0; i < phy_regarray_pg_len; i = i + 6) { in phy_config_bb_with_pghdrfile()
880 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_pghdrfile()
898 } while (0)
907 u32 v1 = 0, v2 = 0; in rtl92ee_phy_config_rf_with_headerfile()
916 for (i = 0; i < len; i = i + 2) { in rtl92ee_phy_config_rf_with_headerfile()
919 if (v1 < 0xcdcdcdcd) { in rtl92ee_phy_config_rf_with_headerfile()
930 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
931 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
932 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
941 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
942 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
943 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
950 while (v2 != 0xDEAD && i < len - 2) in rtl92ee_phy_config_rf_with_headerfile()
963 for (i = 0; i < len; i = i + 2) { in rtl92ee_phy_config_rf_with_headerfile()
966 if (v1 < 0xcdcdcdcd) { in rtl92ee_phy_config_rf_with_headerfile()
977 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
978 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
979 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
988 while (v2 != 0xDEAD && in rtl92ee_phy_config_rf_with_headerfile()
989 v2 != 0xCDEF && in rtl92ee_phy_config_rf_with_headerfile()
990 v2 != 0xCDCD && i < len - 2) { in rtl92ee_phy_config_rf_with_headerfile()
997 while (v2 != 0xDEAD && i < len - 2) in rtl92ee_phy_config_rf_with_headerfile()
1015 rtlphy->default_initialgain[0] = in rtl92ee_phy_get_hw_reg_originalvalue()
1025 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92ee_phy_get_hw_reg_originalvalue()
1026 rtlphy->default_initialgain[0], in rtl92ee_phy_get_hw_reg_originalvalue()
1037 "Default framesync (0x%x) = 0x%x\n", in rtl92ee_phy_get_hw_reg_originalvalue()
1097 u8 rate_section = 0; in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1117 rate_section = 0; in _rtl92ee_phy_get_ratesection_intxpower_byrate()
1162 u8 shift = 0, sec, tx_num; in _rtl92ee_get_txpower_by_rate()
1163 s8 diff = 0; in _rtl92ee_get_txpower_by_rate()
1183 shift = 0; in _rtl92ee_get_txpower_by_rate()
1218 shift) & 0xff; in _rtl92ee_get_txpower_by_rate()
1230 u8 tx_power = 0; in _rtl92ee_get_txpower_index()
1231 u8 diff = 0; in _rtl92ee_get_txpower_index()
1234 index = 0; in _rtl92ee_get_txpower_index()
1529 for (i = 0; i < size; i++) { in phy_set_txpower_index_by_rate_array()
1685 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92ee_phy_set_bw_mode_callback()
1697 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1698 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92ee_phy_set_bw_mode_callback()
1700 (BIT(31) | BIT(30)), 0); in rtl92ee_phy_set_bw_mode_callback()
1703 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1704 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92ee_phy_set_bw_mode_callback()
1707 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, in rtl92ee_phy_set_bw_mode_callback()
1710 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92ee_phy_set_bw_mode_callback()
1762 if (delay > 0) in rtl92ee_phy_sw_chnl_callback()
1781 return 0; in rtl92ee_phy_sw_chnl()
1783 return 0; in rtl92ee_phy_sw_chnl()
1787 rtlphy->sw_chnl_stage = 0; in rtl92ee_phy_sw_chnl()
1788 rtlphy->sw_chnl_step = 0; in rtl92ee_phy_sw_chnl()
1819 precommoncmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1822 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1824 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1826 postcommoncmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1829 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1831 rfdependcmdcnt = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1843 0, 0, 0); in _rtl92ee_phy_sw_chnl_step_by_step()
1847 case 0: in _rtl92ee_phy_sw_chnl_step_by_step()
1866 (*step) = 0; in _rtl92ee_phy_sw_chnl_step_by_step()
1887 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92ee_phy_sw_chnl_step_by_step()
1890 0xfffff00) | currentcmd->para2); in _rtl92ee_phy_sw_chnl_step_by_step()
1894 0x3ff, in _rtl92ee_phy_sw_chnl_step_by_step()
1939 u8 result = 0x00; in _rtl92ee_phy_path_a_iqk()
1941 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_a_iqk()
1942 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_iqk()
1943 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_iqk()
1944 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_iqk()
1946 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_iqk()
1947 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1948 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1949 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_iqk()
1951 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82140303); in _rtl92ee_phy_path_a_iqk()
1952 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_a_iqk()
1955 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_a_iqk()
1958 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl92ee_phy_path_a_iqk()
1959 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_iqk()
1963 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1964 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1965 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92ee_phy_path_a_iqk()
1968 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_a_iqk()
1969 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92ee_phy_path_a_iqk()
1970 result |= 0x01; in _rtl92ee_phy_path_a_iqk()
1980 u8 result = 0x00; in _rtl92ee_phy_path_b_iqk()
1982 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_b_iqk()
1983 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1984 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_iqk()
1985 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1987 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_iqk()
1988 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_iqk()
1990 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1991 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1992 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_iqk()
1993 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_iqk()
1995 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x821403e2); in _rtl92ee_phy_path_b_iqk()
1996 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160000); in _rtl92ee_phy_path_b_iqk()
1999 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x00462911); in _rtl92ee_phy_path_b_iqk()
2002 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_iqk()
2003 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_iqk()
2007 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2008 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2009 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92ee_phy_path_b_iqk()
2012 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_b_iqk()
2013 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92ee_phy_path_b_iqk()
2014 result |= 0x01; in _rtl92ee_phy_path_b_iqk()
2024 u8 result = 0x00; in _rtl92ee_phy_path_a_rx_iqk()
2028 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2030 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2031 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2032 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2033 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_a_rx_iqk()
2035 /*PA/PAD control by 0x56, and set = 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2036 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2037 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2040 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2043 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_a_rx_iqk()
2044 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2047 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2048 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2049 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2050 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2052 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2053 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2056 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_a_rx_iqk()
2059 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2060 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2070 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_a_rx_iqk()
2071 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) { in _rtl92ee_phy_path_a_rx_iqk()
2072 result |= 0x01; in _rtl92ee_phy_path_a_rx_iqk()
2074 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_a_rx_iqk()
2075 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2076 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2080 u32temp = 0x80007C00 | (reg_e94 & 0x3FF0000) | in _rtl92ee_phy_path_a_rx_iqk()
2081 ((reg_e9c & 0x3FF0000) >> 16); in _rtl92ee_phy_path_a_rx_iqk()
2085 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2087 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_a_rx_iqk()
2089 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_a_rx_iqk()
2090 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_a_rx_iqk()
2091 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_a_rx_iqk()
2093 /*PA/PAD control by 0x56, and set = 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2094 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_a_rx_iqk()
2095 rtl_set_rfreg(hw, RF90_PATH_A, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_a_rx_iqk()
2098 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_rx_iqk()
2101 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_a_rx_iqk()
2104 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2105 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2106 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2107 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_a_rx_iqk()
2109 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2110 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_a_rx_iqk()
2113 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_a_rx_iqk()
2115 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_a_rx_iqk()
2116 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_a_rx_iqk()
2123 /*PA/PAD controlled by 0x0*/ in _rtl92ee_phy_path_a_rx_iqk()
2125 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_a_rx_iqk()
2126 rtl_set_rfreg(hw, RF90_PATH_A, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_a_rx_iqk()
2129 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92ee_phy_path_a_rx_iqk()
2130 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl92ee_phy_path_a_rx_iqk()
2131 result |= 0x02; in _rtl92ee_phy_path_a_rx_iqk()
2140 u8 result = 0x00; in _rtl92ee_phy_path_b_rx_iqk()
2144 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2146 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2147 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2148 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2149 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl92ee_phy_path_b_rx_iqk()
2152 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2153 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2155 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2158 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_path_b_rx_iqk()
2159 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2162 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2163 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2164 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2165 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2167 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2168 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x68160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2171 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl92ee_phy_path_b_rx_iqk()
2174 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2175 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2185 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92ee_phy_path_b_rx_iqk()
2186 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) { in _rtl92ee_phy_path_b_rx_iqk()
2187 result |= 0x01; in _rtl92ee_phy_path_b_rx_iqk()
2189 /* PA/PAD controlled by 0x0 */ in _rtl92ee_phy_path_b_rx_iqk()
2190 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2191 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2195 u32temp = 0x80007C00 | (reg_eb4 & 0x3FF0000) | in _rtl92ee_phy_path_b_rx_iqk()
2196 ((reg_ebc & 0x3FF0000) >> 16); in _rtl92ee_phy_path_b_rx_iqk()
2200 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2201 rtl_set_rfreg(hw, RF90_PATH_B, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl92ee_phy_path_b_rx_iqk()
2203 rtl_set_rfreg(hw, RF90_PATH_B, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl92ee_phy_path_b_rx_iqk()
2204 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl92ee_phy_path_b_rx_iqk()
2205 rtl_set_rfreg(hw, RF90_PATH_B, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl92ee_phy_path_b_rx_iqk()
2208 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x980); in _rtl92ee_phy_path_b_rx_iqk()
2209 rtl_set_rfreg(hw, RF90_PATH_B, 0x56, RFREG_OFFSET_MASK, 0x51000); in _rtl92ee_phy_path_b_rx_iqk()
2212 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_b_rx_iqk()
2215 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_path_b_rx_iqk()
2218 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2219 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2220 rtl_set_bbreg(hw, RTX_IQK_TONE_B, MASKDWORD, 0x38008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2221 rtl_set_bbreg(hw, RRX_IQK_TONE_B, MASKDWORD, 0x18008c1c); in _rtl92ee_phy_path_b_rx_iqk()
2223 rtl_set_bbreg(hw, RTX_IQK_PI_B, MASKDWORD, 0x82160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2224 rtl_set_bbreg(hw, RRX_IQK_PI_B, MASKDWORD, 0x28160c1f); in _rtl92ee_phy_path_b_rx_iqk()
2227 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a891); in _rtl92ee_phy_path_b_rx_iqk()
2229 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xfa000000); in _rtl92ee_phy_path_b_rx_iqk()
2230 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl92ee_phy_path_b_rx_iqk()
2237 /*PA/PAD controlled by 0x0*/ in _rtl92ee_phy_path_b_rx_iqk()
2239 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl92ee_phy_path_b_rx_iqk()
2240 rtl_set_rfreg(hw, RF90_PATH_B, 0xdf, RFREG_OFFSET_MASK, 0x180); in _rtl92ee_phy_path_b_rx_iqk()
2243 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92ee_phy_path_b_rx_iqk()
2244 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92ee_phy_path_b_rx_iqk()
2245 result |= 0x02; in _rtl92ee_phy_path_b_rx_iqk()
2260 if (final_candidate == 0xFF) { in _rtl92ee_phy_path_a_fill_iqk_matrix()
2264 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2265 x = result[final_candidate][0]; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2266 if ((x & 0x00000200) != 0) in _rtl92ee_phy_path_a_fill_iqk_matrix()
2267 x = x | 0xFFFFFC00; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2269 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2271 ((x * oldval_0 >> 7) & 0x1)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2273 if ((y & 0x00000200) != 0) in _rtl92ee_phy_path_a_fill_iqk_matrix()
2274 y = y | 0xFFFFFC00; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2276 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2277 ((tx0_c & 0x3C0) >> 6)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2278 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_a_fill_iqk_matrix()
2279 (tx0_c & 0x3F)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2281 ((y * oldval_0 >> 7) & 0x1)); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2287 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2289 reg = result[final_candidate][3] & 0x3F; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2290 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2292 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92ee_phy_path_a_fill_iqk_matrix()
2293 rtl_set_bbreg(hw, ROFDM0_RXIQEXTANTA, 0xF0000000, reg); in _rtl92ee_phy_path_a_fill_iqk_matrix()
2305 if (final_candidate == 0xFF) { in _rtl92ee_phy_path_b_fill_iqk_matrix()
2309 MASKDWORD) >> 22) & 0x3FF; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2311 if ((x & 0x00000200) != 0) in _rtl92ee_phy_path_b_fill_iqk_matrix()
2312 x = x | 0xFFFFFC00; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2314 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2316 ((x * oldval_1 >> 7) & 0x1)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2318 if ((y & 0x00000200) != 0) in _rtl92ee_phy_path_b_fill_iqk_matrix()
2319 y = y | 0xFFFFFC00; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2321 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2322 ((tx1_c & 0x3C0) >> 6)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2323 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92ee_phy_path_b_fill_iqk_matrix()
2324 (tx1_c & 0x3F)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2326 ((y * oldval_1 >> 7) & 0x1)); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2332 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2334 reg = result[final_candidate][7] & 0x3F; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2335 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2337 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92ee_phy_path_b_fill_iqk_matrix()
2338 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0xF0000000, reg); in _rtl92ee_phy_path_b_fill_iqk_matrix()
2348 for (i = 0; i < registernum; i++) in _rtl92ee_phy_save_adda_registers()
2358 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92ee_phy_save_mac_registers()
2370 for (i = 0; i < regiesternum; i++) in _rtl92ee_phy_reload_adda_registers()
2380 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92ee_phy_reload_mac_registers()
2390 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in _rtl92ee_phy_path_adda_on()
2391 rtl_set_bbreg(hw, addareg[i], MASKDWORD, 0x0fc01616); in _rtl92ee_phy_path_adda_on()
2397 rtl_set_bbreg(hw, 0x520, 0x00ff0000, 0xff); in _rtl92ee_phy_mac_setting_calibration()
2402 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92ee_phy_path_a_standby()
2403 rtl_set_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK, 0x10000); in _rtl92ee_phy_path_a_standby()
2404 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92ee_phy_path_a_standby()
2412 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl92ee_phy_simularity_compare()
2418 simularity_bitmap = 0; in _rtl92ee_phy_simularity_compare()
2420 for (i = 0; i < bound; i++) { in _rtl92ee_phy_simularity_compare()
2422 if ((result[c1][i] & 0x00000200) != 0) in _rtl92ee_phy_simularity_compare()
2423 tmp1 = result[c1][i] | 0xFFFFFC00; in _rtl92ee_phy_simularity_compare()
2427 if ((result[c2][i] & 0x00000200) != 0) in _rtl92ee_phy_simularity_compare()
2428 tmp2 = result[c2][i] | 0xFFFFFC00; in _rtl92ee_phy_simularity_compare()
2440 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92ee_phy_simularity_compare()
2442 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92ee_phy_simularity_compare()
2452 if (simularity_bitmap == 0) { in _rtl92ee_phy_simularity_compare()
2453 for (i = 0; i < (bound / 4); i++) { in _rtl92ee_phy_simularity_compare()
2454 if (final_candidate[i] != 0xFF) { in _rtl92ee_phy_simularity_compare()
2463 if (!(simularity_bitmap & 0x03)) {/*path A TX OK*/ in _rtl92ee_phy_simularity_compare()
2464 for (i = 0; i < 2; i++) in _rtl92ee_phy_simularity_compare()
2467 if (!(simularity_bitmap & 0x0c)) {/*path A RX OK*/ in _rtl92ee_phy_simularity_compare()
2471 if (!(simularity_bitmap & 0x30)) {/*path B TX OK*/ in _rtl92ee_phy_simularity_compare()
2475 if (!(simularity_bitmap & 0xc0)) {/*path B RX OK*/ in _rtl92ee_phy_simularity_compare()
2489 u8 tmp_0xc50 = (u8)rtl_get_bbreg(hw, 0xc50, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2490 u8 tmp_0xc58 = (u8)rtl_get_bbreg(hw, 0xc58, MASKBYTE0); in _rtl92ee_phy_iq_calibrate()
2492 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl92ee_phy_iq_calibrate()
2493 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92ee_phy_iq_calibrate()
2494 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92ee_phy_iq_calibrate()
2495 0xed8, 0xedc, 0xee0, 0xeec in _rtl92ee_phy_iq_calibrate()
2498 0x522, 0x550, 0x551, 0x040 in _rtl92ee_phy_iq_calibrate()
2502 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, in _rtl92ee_phy_iq_calibrate()
2503 0x870, 0x860, in _rtl92ee_phy_iq_calibrate()
2504 0x864, 0x800 in _rtl92ee_phy_iq_calibrate()
2508 if (t == 0) { in _rtl92ee_phy_iq_calibrate()
2522 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92ee_phy_iq_calibrate()
2523 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92ee_phy_iq_calibrate()
2524 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92ee_phy_iq_calibrate()
2525 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208200); in _rtl92ee_phy_iq_calibrate()
2527 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2528 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(26), 0x01); in _rtl92ee_phy_iq_calibrate()
2529 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2530 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, BIT(10), 0x01); in _rtl92ee_phy_iq_calibrate()
2536 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2537 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2538 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2540 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2543 if (patha_ok == 0x01) { in _rtl92ee_phy_iq_calibrate()
2546 result[t][0] = (rtl_get_bbreg(hw, in _rtl92ee_phy_iq_calibrate()
2548 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2551 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2556 "Path A Tx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2560 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2563 if (patha_ok == 0x03) { in _rtl92ee_phy_iq_calibrate()
2568 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2572 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2577 "Path A Rx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2581 if (0x00 == patha_ok) in _rtl92ee_phy_iq_calibrate()
2583 "Path A IQK failed!!, ret = 0\n"); in _rtl92ee_phy_iq_calibrate()
2590 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl92ee_phy_iq_calibrate()
2591 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl92ee_phy_iq_calibrate()
2592 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl92ee_phy_iq_calibrate()
2594 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2596 if (pathb_ok == 0x01) { in _rtl92ee_phy_iq_calibrate()
2601 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2605 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2610 "Path B Tx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2614 for (i = 0 ; i < retrycount ; i++) { in _rtl92ee_phy_iq_calibrate()
2616 if (pathb_ok == 0x03) { in _rtl92ee_phy_iq_calibrate()
2621 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2625 MASKDWORD) & 0x3FF0000) in _rtl92ee_phy_iq_calibrate()
2630 "Path B Rx IQK Fail!!, ret = 0x%x\n", in _rtl92ee_phy_iq_calibrate()
2634 if (0x00 == pathb_ok) in _rtl92ee_phy_iq_calibrate()
2636 "Path B IQK failed!!, ret = 0\n"); in _rtl92ee_phy_iq_calibrate()
2641 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0); in _rtl92ee_phy_iq_calibrate()
2643 if (t != 0) { in _rtl92ee_phy_iq_calibrate()
2658 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2659 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, tmp_0xc50); in _rtl92ee_phy_iq_calibrate()
2661 rtl_set_bbreg(hw, 0xc50, MASKBYTE0, 0x50); in _rtl92ee_phy_iq_calibrate()
2662 rtl_set_bbreg(hw, 0xc58, MASKBYTE0, tmp_0xc58); in _rtl92ee_phy_iq_calibrate()
2665 /* load 0xe30 IQC default value */ in _rtl92ee_phy_iq_calibrate()
2666 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2667 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x01008c00); in _rtl92ee_phy_iq_calibrate()
2674 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; in _rtl92ee_phy_lc_calibrate()
2677 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92ee_phy_lc_calibrate()
2679 if ((tmpreg & 0x70) != 0) in _rtl92ee_phy_lc_calibrate()
2680 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92ee_phy_lc_calibrate()
2682 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92ee_phy_lc_calibrate()
2684 if ((tmpreg & 0x70) != 0) { in _rtl92ee_phy_lc_calibrate()
2685 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2688 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl92ee_phy_lc_calibrate()
2691 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2692 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl92ee_phy_lc_calibrate()
2695 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2696 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl92ee_phy_lc_calibrate()
2698 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl92ee_phy_lc_calibrate()
2700 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl92ee_phy_lc_calibrate()
2704 if ((tmpreg & 0x70) != 0) { in _rtl92ee_phy_lc_calibrate()
2705 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92ee_phy_lc_calibrate()
2706 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl92ee_phy_lc_calibrate()
2709 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl92ee_phy_lc_calibrate()
2712 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92ee_phy_lc_calibrate()
2730 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92ee_phy_set_rfpath_switch()
2735 BIT(5) | BIT(6), 0x1); in _rtl92ee_phy_set_rfpath_switch()
2738 BIT(5) | BIT(6), 0x2); in _rtl92ee_phy_set_rfpath_switch()
2740 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl92ee_phy_set_rfpath_switch()
2741 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl92ee_phy_set_rfpath_switch()
2749 BIT(14) | BIT(13) | BIT(12), 0); in _rtl92ee_phy_set_rfpath_switch()
2751 BIT(5) | BIT(4) | BIT(3), 0); in _rtl92ee_phy_set_rfpath_switch()
2753 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl92ee_phy_set_rfpath_switch()
2787 return 0; in rtl92ee_get_rightchnlplace_for_iqk()
2819 for (i = 0; i < 8; i++) { in rtl92ee_phy_iq_calibrate()
2820 result[0][i] = 0; in rtl92ee_phy_iq_calibrate()
2821 result[1][i] = 0; in rtl92ee_phy_iq_calibrate()
2822 result[2][i] = 0; in rtl92ee_phy_iq_calibrate()
2824 if ((i == 0) || (i == 2) || (i == 4) || (i == 6)) in rtl92ee_phy_iq_calibrate()
2825 result[3][i] = 0x100; in rtl92ee_phy_iq_calibrate()
2827 result[3][i] = 0; in rtl92ee_phy_iq_calibrate()
2829 final_candidate = 0xff; in rtl92ee_phy_iq_calibrate()
2835 for (i = 0; i < 3; i++) { in rtl92ee_phy_iq_calibrate()
2840 0, 1); in rtl92ee_phy_iq_calibrate()
2842 final_candidate = 0; in rtl92ee_phy_iq_calibrate()
2850 0, 2); in rtl92ee_phy_iq_calibrate()
2852 final_candidate = 0; in rtl92ee_phy_iq_calibrate()
2865 reg_e94 = result[3][0]; in rtl92ee_phy_iq_calibrate()
2872 if (final_candidate != 0xff) { in rtl92ee_phy_iq_calibrate()
2873 reg_e94 = result[final_candidate][0]; in rtl92ee_phy_iq_calibrate()
2886 rtlphy->reg_e94 = 0x100; in rtl92ee_phy_iq_calibrate()
2887 rtlphy->reg_eb4 = 0x100; in rtl92ee_phy_iq_calibrate()
2888 rtlphy->reg_e9c = 0x0; in rtl92ee_phy_iq_calibrate()
2889 rtlphy->reg_ebc = 0x0; in rtl92ee_phy_iq_calibrate()
2892 if (reg_e94 != 0) in rtl92ee_phy_iq_calibrate()
2895 (reg_ea4 == 0)); in rtl92ee_phy_iq_calibrate()
2899 (reg_ec4 == 0)); in rtl92ee_phy_iq_calibrate()
2903 /* To Fix BSOD when final_candidate is 0xff */ in rtl92ee_phy_iq_calibrate()
2905 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92ee_phy_iq_calibrate()
2906 rtlphy->iqk_matrix[idx].value[0][i] = in rtl92ee_phy_iq_calibrate()
2920 u32 timeout = 2000, timecount = 0; in rtl92ee_phy_lc_calibrate()
3003 rtl92ee_dm_write_dig(hw, 0x17); in rtl92ee_phy_set_io()
3005 rtl92ee_dm_write_cck_cca_thres(hw, 0x40); in rtl92ee_phy_set_io()
3022 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl92ee_phy_set_rf_on()
3023 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ee_phy_set_rf_on()
3024 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ in rtl92ee_phy_set_rf_on()
3025 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92ee_phy_set_rf_on()
3026 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ee_phy_set_rf_on()
3027 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl92ee_phy_set_rf_on()
3034 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92ee_phy_set_rf_sleep()
3035 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92ee_phy_set_rf_sleep()
3037 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92ee_phy_set_rf_sleep()
3038 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92ee_phy_set_rf_sleep()
3057 u32 initializecount = 0; in _rtl92ee_phy_set_rf_power_state()
3080 for (queue_id = 0, i = 0; in _rtl92ee_phy_set_rf_power_state()
3084 skb_queue_len(&ring->queue) == 0) { in _rtl92ee_phy_set_rf_power_state()
3124 for (queue_id = 0, i = 0; in _rtl92ee_phy_set_rf_power_state()
3127 if (skb_queue_len(&ring->queue) == 0) { in _rtl92ee_phy_set_rf_power_state()