Lines Matching +full:0 +full:xeb4
29 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
41 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
62 {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
63 {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
64 {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
65 {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
66 {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
70 {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
71 {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
72 {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
75 static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
78 {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
79 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
80 {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
88 0x70000, 0x00ff0, 0x4400f, 0x00ff0, 0x0, 0x0, 0x0,
89 0x0, 0x0, 0x64888, 0xe266c, 0x00090, 0x22fff
93 0x70000, 0x22880, 0x4470f, 0x55880, 0x00070, 0x88000,
94 0x0, 0x88080, 0x70000, 0x64a82, 0xe466c, 0x00090,
95 0x32c9a
99 0x70000, 0x44880, 0x4477f, 0x77880, 0x00070, 0x88000,
100 0x0, 0x880b0, 0x0, 0x64b82, 0xe466c, 0x00090, 0x32c9a
105 static u32 curveindex_5g[TARGET_CHNL_NUM_5G] = {0};
107 static u32 curveindex_2g[TARGET_CHNL_NUM_2G] = {0};
188 u8 dbi_direct = 0; in rtl92d_phy_query_bb_reg()
204 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92d_phy_query_bb_reg()
214 u8 dbi_direct = 0; in rtl92d_phy_set_bb_reg()
254 u8 rfpi_enable = 0; in _rtl92d_phy_rf_serial_read()
286 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x] = 0x%x\n", in _rtl92d_phy_rf_serial_read()
303 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92d_phy_rf_serial_write()
305 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92d_phy_rf_serial_write()
339 if (bitmask == 0) in rtl92d_phy_set_rf_reg()
369 for (i = 0; i < arraylength; i = i + 2) in rtl92d_phy_mac_config()
373 /* rtl_write_byte(rtlpriv, 0x14,0x71); */ in rtl92d_phy_mac_config()
376 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x0B); in rtl92d_phy_mac_config()
379 rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x07); in rtl92d_phy_mac_config()
390 /* 16 LSBs if read 32-bit from 0x870 */ in _rtl92d_phy_init_bb_rf_register_definition()
392 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ in _rtl92d_phy_init_bb_rf_register_definition()
394 /* 16 LSBs if read 32-bit from 0x874 */ in _rtl92d_phy_init_bb_rf_register_definition()
396 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ in _rtl92d_phy_init_bb_rf_register_definition()
400 /* 16 LSBs if read 32-bit from 0x8E0 */ in _rtl92d_phy_init_bb_rf_register_definition()
402 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ in _rtl92d_phy_init_bb_rf_register_definition()
404 /* 16 LSBs if read 32-bit from 0x8E4 */ in _rtl92d_phy_init_bb_rf_register_definition()
406 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ in _rtl92d_phy_init_bb_rf_register_definition()
410 /* 16 LSBs if read 32-bit from 0x860 */ in _rtl92d_phy_init_bb_rf_register_definition()
412 /* 16 LSBs if read 32-bit from 0x864 */ in _rtl92d_phy_init_bb_rf_register_definition()
416 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ in _rtl92d_phy_init_bb_rf_register_definition()
418 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ in _rtl92d_phy_init_bb_rf_register_definition()
518 u16 phy_reg_arraylen, agctab_arraylen = 0, agctab_5garraylen; in _rtl92d_phy_config_bb_with_headerfile()
523 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
547 for (i = 0; i < phy_reg_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
553 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n", in _rtl92d_phy_config_bb_with_headerfile()
558 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_config_bb_with_headerfile()
559 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
567 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
575 for (i = 0; i < agctab_arraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
583 "The Rtl819XAGCTAB_Array_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
590 for (i = 0; i < agctab_5garraylen; i = i + 2) { in _rtl92d_phy_config_bb_with_headerfile()
599 "The Rtl819XAGCTAB_5GArray_Table[0] is %u Rtl819XPHY_REGArray[1] is %u\n", in _rtl92d_phy_config_bb_with_headerfile()
620 index = 0; in _rtl92d_store_pwrindex_diffrate_offset()
625 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) in _rtl92d_store_pwrindex_diffrate_offset()
641 else if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) in _rtl92d_store_pwrindex_diffrate_offset()
656 "MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", in _rtl92d_store_pwrindex_diffrate_offset()
674 for (i = 0; i < phy_regarray_pg_len; i = i + 3) { in _rtl92d_phy_config_bb_with_pgheaderfile()
709 rtlphy->pwrgroup_cnt = 0; in _rtl92d_phy_bb_config()
724 RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92d_phy_bb_config()
739 regval | BIT(13) | BIT(0) | BIT(1)); in rtl92d_phy_bb_config()
740 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83); in rtl92d_phy_bb_config()
741 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb); in rtl92d_phy_bb_config()
742 /* 0x1f bit7 bit6 represent for mac0/mac1 driver ready */ in rtl92d_phy_bb_config()
748 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); in rtl92d_phy_bb_config()
776 if (rtlpriv->efuse.internal_pa_5g[0]) { in rtl92d_phy_config_rf_with_headerfile()
791 * mac1 start on 5G, mac 0 has to set phy0&phy1 in rtl92d_phy_config_rf_with_headerfile()
801 for (i = 0; i < radioa_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
808 for (i = 0; i < radiob_arraylen; i = i + 2) { in rtl92d_phy_config_rf_with_headerfile()
827 rtlphy->default_initialgain[0] = in rtl92d_phy_get_hw_reg_originalvalue()
836 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
837 rtlphy->default_initialgain[0], in rtl92d_phy_get_hw_reg_originalvalue()
846 "Default framesync (0x%x) = 0x%x\n", in rtl92d_phy_get_hw_reg_originalvalue()
868 cckpowerlevel[RF90_PATH_A] = 0; in _rtl92d_get_txpower_index()
869 cckpowerlevel[RF90_PATH_B] = 0; in _rtl92d_get_txpower_index()
893 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92d_ccxpower_index_check()
894 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92d_ccxpower_index_check()
921 _rtl92d_get_txpower_index(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
922 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
924 _rtl92d_ccxpower_index_check(hw, channel, &cckpowerlevel[0], in rtl92d_phy_set_txpower_level()
925 &ofdmpowerlevel[0]); in rtl92d_phy_set_txpower_level()
927 rtl92d_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl92d_phy_set_txpower_level()
928 rtl92d_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel); in rtl92d_phy_set_txpower_level()
938 unsigned long flag = 0; in rtl92d_phy_set_bw_mode()
964 reg_prsr_rsc = (reg_prsr_rsc & 0x90) | in rtl92d_phy_set_bw_mode()
975 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
976 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl92d_phy_set_bw_mode()
982 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
983 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl92d_phy_set_bw_mode()
992 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl92d_phy_set_bw_mode()
995 BIT(11), 0); in rtl92d_phy_set_bw_mode()
996 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl92d_phy_set_bw_mode()
1013 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1014 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0); in _rtl92d_phy_stop_trx_before_changeband()
1015 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x00); in _rtl92d_phy_stop_trx_before_changeband()
1016 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x0); in _rtl92d_phy_stop_trx_before_changeband()
1048 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1); in rtl92d_phy_switch_wirelessband()
1049 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1); in rtl92d_phy_switch_wirelessband()
1054 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_switch_wirelessband()
1057 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1060 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1063 0 ? REG_MAC0 : REG_MAC1)); in rtl92d_phy_switch_wirelessband()
1066 0 ? REG_MAC0 : REG_MAC1), value8); in rtl92d_phy_switch_wirelessband()
1079 unsigned long flag = 0; in _rtl92d_phy_reload_imr_setting()
1084 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1085 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1086 /* fc area 0xd2c */ in _rtl92d_phy_reload_imr_setting()
1093 /* leave 0 for channel1-14. */ in _rtl92d_phy_reload_imr_setting()
1096 for (i = 0; i < imr_num; i++) in _rtl92d_phy_reload_imr_setting()
1099 rf_imr_param_normal[0][group][i]); in _rtl92d_phy_reload_imr_setting()
1100 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1113 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(25) | BIT(24), 0); in _rtl92d_phy_reload_imr_setting()
1115 0x00f00000, 0xf); in _rtl92d_phy_reload_imr_setting()
1117 for (i = 0; i < imr_num; i++) { in _rtl92d_phy_reload_imr_setting()
1121 rf_imr_param_normal[0][0][i]); in _rtl92d_phy_reload_imr_setting()
1124 0x00f00000, 0); in _rtl92d_phy_reload_imr_setting()
1153 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1); in _rtl92d_phy_enable_rf_env()
1156 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1); in _rtl92d_phy_enable_rf_env()
1160 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREADDRESSLENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1162 /*Set 0 to 12 bits for 8255 */ in _rtl92d_phy_enable_rf_env()
1163 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0); in _rtl92d_phy_enable_rf_env()
1198 u8 index = 0, i = 0, rfpath = RF90_PATH_A; in _rtl92d_phy_switch_rf_setting()
1200 u32 u4regvalue, mask = 0x1C000, value = 0, u4tmp, u4tmp2; in _rtl92d_phy_switch_rf_setting()
1208 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1209 for (i = 0; i < RF_CHNL_NUM_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1211 index = 0; in _rtl92d_phy_switch_rf_setting()
1213 for (i = 0; i < RF_CHNL_NUM_5G_40M; i++) { in _rtl92d_phy_switch_rf_setting()
1234 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_5G; i++) { in _rtl92d_phy_switch_rf_setting()
1235 if (i == 0 && (rtlhal->macphymode == DUALMAC_DUALPHY)) { in _rtl92d_phy_switch_rf_setting()
1238 RFREG_OFFSET_MASK, 0xE439D); in _rtl92d_phy_switch_rf_setting()
1241 0x7FF) | (u4tmp << 11); in _rtl92d_phy_switch_rf_setting()
1254 "offset 0x%x value 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1267 value = 0x07; in _rtl92d_phy_switch_rf_setting()
1269 value = 0x02; in _rtl92d_phy_switch_rf_setting()
1271 index = 0; in _rtl92d_phy_switch_rf_setting()
1285 for (i = 0; in _rtl92d_phy_switch_rf_setting()
1293 "offset 0x%x value 0x%x path %d index %d\n", in _rtl92d_phy_switch_rf_setting()
1299 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in _rtl92d_phy_switch_rf_setting()
1307 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_switch_rf_setting()
1310 index = 0; in _rtl92d_phy_switch_rf_setting()
1317 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_switch_rf_setting()
1327 for (i = 0; i < RF_REG_NUM_FOR_C_CUT_2G; i++) { in _rtl92d_phy_switch_rf_setting()
1341 "offset 0x%x value 0x%x mak 0x%x path %d index %d readback 0x%x\n", in _rtl92d_phy_switch_rf_setting()
1350 "cosa ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_switch_rf_setting()
1375 return 0; in rtl92d_get_rightchnlplace_for_iqk()
1388 u8 result = 0; in _rtl92d_phy_patha_iqk()
1393 if (rtlhal->interfaceindex == 0) { in _rtl92d_phy_patha_iqk()
1394 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1395 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92d_phy_patha_iqk()
1397 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1398 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1400 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1401 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1404 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1405 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92d_phy_patha_iqk()
1406 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92d_phy_patha_iqk()
1407 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160206); in _rtl92d_phy_patha_iqk()
1411 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk()
1414 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk()
1415 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk()
1422 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk()
1423 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk()
1424 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk()
1425 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk()
1426 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk()
1427 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk()
1428 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk()
1429 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk()
1430 if (!(regeac & BIT(28)) && (((rege94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_patha_iqk()
1431 (((rege9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_patha_iqk()
1432 result |= 0x01; in _rtl92d_phy_patha_iqk()
1436 if (!(regeac & BIT(27)) && (((regea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_patha_iqk()
1437 (((regeac & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_patha_iqk()
1438 result |= 0x02; in _rtl92d_phy_patha_iqk()
1452 u8 result = 0; in _rtl92d_phy_patha_iqk_5g_normal()
1464 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1465 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_patha_iqk_5g_normal()
1466 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140307); in _rtl92d_phy_patha_iqk_5g_normal()
1467 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68160960); in _rtl92d_phy_patha_iqk_5g_normal()
1470 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1471 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_patha_iqk_5g_normal()
1472 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82110000); in _rtl92d_phy_patha_iqk_5g_normal()
1473 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68110000); in _rtl92d_phy_patha_iqk_5g_normal()
1477 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_patha_iqk_5g_normal()
1479 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x07000f60); in _rtl92d_phy_patha_iqk_5g_normal()
1480 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, MASKDWORD, 0x66e60e30); in _rtl92d_phy_patha_iqk_5g_normal()
1481 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_patha_iqk_5g_normal()
1485 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92d_phy_patha_iqk_5g_normal()
1486 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_patha_iqk_5g_normal()
1493 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1494 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_patha_iqk_5g_normal()
1495 rege94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1496 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe94 = 0x%x\n", rege94); in _rtl92d_phy_patha_iqk_5g_normal()
1497 rege9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1498 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xe9c = 0x%x\n", rege9c); in _rtl92d_phy_patha_iqk_5g_normal()
1499 regea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92d_phy_patha_iqk_5g_normal()
1500 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xea4 = 0x%x\n", regea4); in _rtl92d_phy_patha_iqk_5g_normal()
1502 (((rege94 & 0x03FF0000) >> 16) != 0x142)) { in _rtl92d_phy_patha_iqk_5g_normal()
1503 result |= 0x01; in _rtl92d_phy_patha_iqk_5g_normal()
1512 (((regea4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_patha_iqk_5g_normal()
1513 result |= 0x02; in _rtl92d_phy_patha_iqk_5g_normal()
1522 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_patha_iqk_5g_normal()
1533 u8 result = 0; in _rtl92d_phy_pathb_iqk()
1538 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92d_phy_pathb_iqk()
1539 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92d_phy_pathb_iqk()
1545 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1546 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk()
1547 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1548 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk()
1549 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1550 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk()
1551 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1552 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk()
1553 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk()
1554 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk()
1555 if (!(regeac & BIT(31)) && (((regeb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92d_phy_pathb_iqk()
1556 (((regebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92d_phy_pathb_iqk()
1557 result |= 0x01; in _rtl92d_phy_pathb_iqk()
1560 if (!(regeac & BIT(30)) && (((regec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92d_phy_pathb_iqk()
1561 (((regecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92d_phy_pathb_iqk()
1562 result |= 0x02; in _rtl92d_phy_pathb_iqk()
1574 u8 result = 0; in _rtl92d_phy_pathb_iqk_5g_normal()
1581 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1582 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x18008c1f); in _rtl92d_phy_pathb_iqk_5g_normal()
1583 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1584 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x68110000); in _rtl92d_phy_pathb_iqk_5g_normal()
1587 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1588 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x18008c2f); in _rtl92d_phy_pathb_iqk_5g_normal()
1589 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140307); in _rtl92d_phy_pathb_iqk_5g_normal()
1590 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x68160960); in _rtl92d_phy_pathb_iqk_5g_normal()
1594 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl92d_phy_pathb_iqk_5g_normal()
1597 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, MASKDWORD, 0x0f600700); in _rtl92d_phy_pathb_iqk_5g_normal()
1598 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE, MASKDWORD, 0x061f0d30); in _rtl92d_phy_pathb_iqk_5g_normal()
1600 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_pathb_iqk_5g_normal()
1604 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xfa000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1605 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92d_phy_pathb_iqk_5g_normal()
1613 regeac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1614 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeac = 0x%x\n", regeac); in _rtl92d_phy_pathb_iqk_5g_normal()
1615 regeb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1616 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xeb4 = 0x%x\n", regeb4); in _rtl92d_phy_pathb_iqk_5g_normal()
1617 regebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1618 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xebc = 0x%x\n", regebc); in _rtl92d_phy_pathb_iqk_5g_normal()
1619 regec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1620 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xec4 = 0x%x\n", regec4); in _rtl92d_phy_pathb_iqk_5g_normal()
1621 regecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92d_phy_pathb_iqk_5g_normal()
1622 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xecc = 0x%x\n", regecc); in _rtl92d_phy_pathb_iqk_5g_normal()
1624 (((regeb4 & 0x03FF0000) >> 16) != 0x142)) in _rtl92d_phy_pathb_iqk_5g_normal()
1625 result |= 0x01; in _rtl92d_phy_pathb_iqk_5g_normal()
1629 (((regec4 & 0x03FF0000) >> 16) != 0x132)) { in _rtl92d_phy_pathb_iqk_5g_normal()
1630 result |= 0x02; in _rtl92d_phy_pathb_iqk_5g_normal()
1640 rtlphy->iqk_bb_backup[0]); in _rtl92d_phy_pathb_iqk_5g_normal()
1654 for (i = 0; i < regnum; i++) in _rtl92d_phy_save_adda_registers()
1665 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_save_mac_registers()
1679 for (i = 0; i < regnum; i++) in _rtl92d_phy_reload_adda_registers()
1690 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92d_phy_reload_mac_registers()
1703 pathon = patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1705 pathon = rtlpriv->rtlhal.interfaceindex == 0 ? in _rtl92d_phy_path_adda_on()
1706 0x04db25a4 : 0x0b1b25a4; in _rtl92d_phy_path_adda_on()
1707 for (i = 0; i < IQK_ADDA_REG_NUM; i++) in _rtl92d_phy_path_adda_on()
1718 rtl_write_byte(rtlpriv, macreg[0], 0x3F); in _rtl92d_phy_mac_setting_calibration()
1731 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92d_phy_patha_standby()
1732 rtl_set_bbreg(hw, RFPGA0_XA_LSSIPARAMETER, MASKDWORD, 0x00010000); in _rtl92d_phy_patha_standby()
1733 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_patha_standby()
1743 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92d_phy_pimode_switch()
1744 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1745 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92d_phy_pimode_switch()
1756 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate()
1757 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate()
1758 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate()
1759 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate()
1762 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate()
1775 if (t == 0) { in _rtl92d_phy_iq_calibrate()
1777 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate()
1790 if (t == 0) in _rtl92d_phy_iq_calibrate()
1798 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate()
1799 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate()
1800 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate()
1801 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22204000); in _rtl92d_phy_iq_calibrate()
1802 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate()
1805 0x00010000); in _rtl92d_phy_iq_calibrate()
1807 0x00010000); in _rtl92d_phy_iq_calibrate()
1813 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1815 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate()
1818 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92d_phy_iq_calibrate()
1820 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate()
1821 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1823 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1826 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1827 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1828 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1829 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1830 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1831 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1832 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1833 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1835 } else if (i == (retrycount - 1) && patha_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1840 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1841 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1842 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate()
1843 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1846 if (0x00 == patha_ok) in _rtl92d_phy_iq_calibrate()
1852 for (i = 0; i < retrycount; i++) { in _rtl92d_phy_iq_calibrate()
1854 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate()
1857 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1858 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1859 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1860 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1861 result[t][6] = (rtl_get_bbreg(hw, 0xec4, in _rtl92d_phy_iq_calibrate()
1862 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1863 result[t][7] = (rtl_get_bbreg(hw, 0xecc, in _rtl92d_phy_iq_calibrate()
1864 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1866 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92d_phy_iq_calibrate()
1870 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, in _rtl92d_phy_iq_calibrate()
1871 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1872 result[t][5] = (rtl_get_bbreg(hw, 0xebc, in _rtl92d_phy_iq_calibrate()
1873 MASKDWORD) & 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate()
1876 if (0x00 == pathb_ok) in _rtl92d_phy_iq_calibrate()
1885 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate()
1886 if (t != 0) { in _rtl92d_phy_iq_calibrate()
1904 /* load 0xe30 IQC default value */ in _rtl92d_phy_iq_calibrate()
1905 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1906 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl92d_phy_iq_calibrate()
1919 RFPGA0_XCD_SWITCHCONTROL, 0xe6c, 0xe70, 0xe74, in _rtl92d_phy_iq_calibrate_5g_normal()
1920 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92d_phy_iq_calibrate_5g_normal()
1921 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92d_phy_iq_calibrate_5g_normal()
1922 0xed8, 0xedc, 0xee0, 0xeec in _rtl92d_phy_iq_calibrate_5g_normal()
1925 0x522, 0x550, 0x551, 0x040 in _rtl92d_phy_iq_calibrate_5g_normal()
1942 if (t == 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
1944 RTPRINT(rtlpriv, FINIT, INIT_IQK, "==>0x%08x\n", bbvalue); in _rtl92d_phy_iq_calibrate_5g_normal()
1966 if (t == 0) in _rtl92d_phy_iq_calibrate_5g_normal()
1972 rtl_set_bbreg(hw, RFPGA0_RFMOD, BIT(24), 0x00); in _rtl92d_phy_iq_calibrate_5g_normal()
1973 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKDWORD, 0x03a05600); in _rtl92d_phy_iq_calibrate_5g_normal()
1974 rtl_set_bbreg(hw, ROFDM0_TRMUXPAR, MASKDWORD, 0x000800e4); in _rtl92d_phy_iq_calibrate_5g_normal()
1975 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW, MASKDWORD, 0x22208000); in _rtl92d_phy_iq_calibrate_5g_normal()
1976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xf00000, 0x0f); in _rtl92d_phy_iq_calibrate_5g_normal()
1979 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1981 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl92d_phy_iq_calibrate_5g_normal()
1984 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92d_phy_iq_calibrate_5g_normal()
1985 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x10007c00); in _rtl92d_phy_iq_calibrate_5g_normal()
1986 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92d_phy_iq_calibrate_5g_normal()
1988 if (patha_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
1990 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1991 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1992 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1993 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1994 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1995 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1996 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
1997 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
1998 } else if (patha_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
2002 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2003 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2004 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2005 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2014 if (pathb_ok == 0x03) { in _rtl92d_phy_iq_calibrate_5g_normal()
2017 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2018 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2019 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2020 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2021 result[t][6] = (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2022 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2023 result[t][7] = (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2024 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2025 } else if (pathb_ok == 0x01) { /* Tx IQK OK */ in _rtl92d_phy_iq_calibrate_5g_normal()
2028 result[t][4] = (rtl_get_bbreg(hw, 0xeb4, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2029 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2030 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92d_phy_iq_calibrate_5g_normal()
2031 0x3FF0000) >> 16; in _rtl92d_phy_iq_calibrate_5g_normal()
2041 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92d_phy_iq_calibrate_5g_normal()
2042 if (t != 0) { in _rtl92d_phy_iq_calibrate_5g_normal()
2071 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ in _rtl92d_phy_simularity_compare()
2079 sim_bitmap = 0; in _rtl92d_phy_simularity_compare()
2080 for (i = 0; i < bound; i++) { in _rtl92d_phy_simularity_compare()
2085 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2087 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92d_phy_simularity_compare()
2096 if (sim_bitmap == 0) { in _rtl92d_phy_simularity_compare()
2097 for (i = 0; i < (bound / 4); i++) { in _rtl92d_phy_simularity_compare()
2098 if (final_candidate[i] != 0xFF) { in _rtl92d_phy_simularity_compare()
2107 if (!(sim_bitmap & 0x0F)) { /* path A OK */ in _rtl92d_phy_simularity_compare()
2108 for (i = 0; i < 4; i++) in _rtl92d_phy_simularity_compare()
2110 } else if (!(sim_bitmap & 0x03)) { /* path A, Tx OK */ in _rtl92d_phy_simularity_compare()
2111 for (i = 0; i < 2; i++) in _rtl92d_phy_simularity_compare()
2114 if (!(sim_bitmap & 0xF0) && is2t) { /* path B OK */ in _rtl92d_phy_simularity_compare()
2117 } else if (!(sim_bitmap & 0x30)) { /* path B, Tx OK */ in _rtl92d_phy_simularity_compare()
2137 if (final_candidate == 0xFF) { in _rtl92d_phy_patha_fill_iqk_matrix()
2141 MASKDWORD) >> 22) & 0x3FF; /* OFDM0_D */ in _rtl92d_phy_patha_fill_iqk_matrix()
2142 val_x = result[final_candidate][0]; in _rtl92d_phy_patha_fill_iqk_matrix()
2143 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2144 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2147 "X = 0x%x, tx0_a = 0x%x, oldval_0 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2149 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92d_phy_patha_fill_iqk_matrix()
2151 ((val_x * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2153 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_patha_fill_iqk_matrix()
2154 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_patha_fill_iqk_matrix()
2161 "Y = 0x%lx, tx0_c = 0x%lx\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2163 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92d_phy_patha_fill_iqk_matrix()
2164 ((tx0_c & 0x3C0) >> 6)); in _rtl92d_phy_patha_fill_iqk_matrix()
2165 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_patha_fill_iqk_matrix()
2166 (tx0_c & 0x3F)); in _rtl92d_phy_patha_fill_iqk_matrix()
2169 ((val_y * oldval_0 >> 7) & 0x1)); in _rtl92d_phy_patha_fill_iqk_matrix()
2170 RTPRINT(rtlpriv, FINIT, INIT_IQK, "0xC80 = 0x%x\n", in _rtl92d_phy_patha_fill_iqk_matrix()
2178 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2179 reg = result[final_candidate][3] & 0x3F; in _rtl92d_phy_patha_fill_iqk_matrix()
2180 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2181 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92d_phy_patha_fill_iqk_matrix()
2182 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92d_phy_patha_fill_iqk_matrix()
2196 if (final_candidate == 0xFF) { in _rtl92d_phy_pathb_fill_iqk_matrix()
2200 MASKDWORD) >> 22) & 0x3FF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2202 if ((val_x & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2203 val_x = val_x | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2205 RTPRINT(rtlpriv, FINIT, INIT_IQK, "X = 0x%x, tx1_a = 0x%x\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2207 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92d_phy_pathb_fill_iqk_matrix()
2209 ((val_x * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2211 if ((val_y & 0x00000200) != 0) in _rtl92d_phy_pathb_fill_iqk_matrix()
2212 val_y = val_y | 0xFFFFFC00; in _rtl92d_phy_pathb_fill_iqk_matrix()
2216 RTPRINT(rtlpriv, FINIT, INIT_IQK, "Y = 0x%lx, tx1_c = 0x%lx\n", in _rtl92d_phy_pathb_fill_iqk_matrix()
2218 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2219 ((tx1_c & 0x3C0) >> 6)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2220 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92d_phy_pathb_fill_iqk_matrix()
2221 (tx1_c & 0x3F)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2223 ((val_y * oldval_1 >> 7) & 0x1)); in _rtl92d_phy_pathb_fill_iqk_matrix()
2227 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2228 reg = result[final_candidate][7] & 0x3F; in _rtl92d_phy_pathb_fill_iqk_matrix()
2229 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2230 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92d_phy_pathb_fill_iqk_matrix()
2231 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92d_phy_pathb_fill_iqk_matrix()
2244 long regebc, regec4, regecc, regtmp = 0; in rtl92d_phy_iq_calibrate()
2246 unsigned long flag = 0; in rtl92d_phy_iq_calibrate()
2250 for (i = 0; i < 8; i++) { in rtl92d_phy_iq_calibrate()
2251 result[0][i] = 0; in rtl92d_phy_iq_calibrate()
2252 result[1][i] = 0; in rtl92d_phy_iq_calibrate()
2253 result[2][i] = 0; in rtl92d_phy_iq_calibrate()
2254 result[3][i] = 0; in rtl92d_phy_iq_calibrate()
2256 final_candidate = 0xff; in rtl92d_phy_iq_calibrate()
2265 for (i = 0; i < 3; i++) { in rtl92d_phy_iq_calibrate()
2276 0, 1); in rtl92d_phy_iq_calibrate()
2278 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2284 0, 2); in rtl92d_phy_iq_calibrate()
2286 final_candidate = 0; in rtl92d_phy_iq_calibrate()
2294 for (i = 0; i < 8; i++) in rtl92d_phy_iq_calibrate()
2297 if (regtmp != 0) in rtl92d_phy_iq_calibrate()
2300 final_candidate = 0xFF; in rtl92d_phy_iq_calibrate()
2305 for (i = 0; i < 4; i++) { in rtl92d_phy_iq_calibrate()
2306 rege94 = result[i][0]; in rtl92d_phy_iq_calibrate()
2319 if (final_candidate != 0xff) { in rtl92d_phy_iq_calibrate()
2320 rtlphy->reg_e94 = rege94 = result[final_candidate][0]; in rtl92d_phy_iq_calibrate()
2336 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; /* X default value */ in rtl92d_phy_iq_calibrate()
2337 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; /* Y default value */ in rtl92d_phy_iq_calibrate()
2339 if ((rege94 != 0) /*&&(regea4 != 0) */) in rtl92d_phy_iq_calibrate()
2341 final_candidate, (regea4 == 0)); in rtl92d_phy_iq_calibrate()
2343 if ((regeb4 != 0) /*&&(regec4 != 0) */) in rtl92d_phy_iq_calibrate()
2345 final_candidate, (regec4 == 0)); in rtl92d_phy_iq_calibrate()
2347 if (final_candidate != 0xFF) { in rtl92d_phy_iq_calibrate()
2351 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl92d_phy_iq_calibrate()
2353 value[0][i] = result[final_candidate][i]; in rtl92d_phy_iq_calibrate()
2375 if (0 && !rtlphy->iqk_matrix[indexforchannel].iqk_done && in rtl92d_phy_reload_iqk_setting()
2385 indexforchannel == 0) || indexforchannel > 0) { in rtl92d_phy_reload_iqk_setting()
2389 if (rtlphy->iqk_matrix[indexforchannel].value[0][0] != 0) in rtl92d_phy_reload_iqk_setting()
2391 rtlphy->iqk_matrix[indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2392 rtlphy->iqk_matrix[indexforchannel].value[0][2] == 0); in rtl92d_phy_reload_iqk_setting()
2395 indexforchannel].value[0][4] != 0) in rtl92d_phy_reload_iqk_setting()
2396 /*&&(regec4 != 0) */) in rtl92d_phy_reload_iqk_setting()
2400 indexforchannel].value, 0, in rtl92d_phy_reload_iqk_setting()
2402 indexforchannel].value[0][6] in rtl92d_phy_reload_iqk_setting()
2403 == 0)); in rtl92d_phy_reload_iqk_setting()
2427 for (i = 0; i < ARRAY_SIZE(channel5g); i++) in _rtl92d_is_legal_5g_channel()
2438 u32 smallest_abs_val = 0xffffffff, u4tmp; in _rtl92d_phy_calc_curvindex()
2442 for (i = 0; i < chnl_num; i++) { in _rtl92d_phy_calc_curvindex()
2445 curveindex[i] = 0; in _rtl92d_phy_calc_curvindex()
2446 for (j = 0; j < (CV_CURVE_CNT * 2); j++) { in _rtl92d_phy_calc_curvindex()
2455 smallest_abs_val = 0xffffffff; in _rtl92d_phy_calc_curvindex()
2469 u32 u4tmp = 0, u4regvalue = 0; in _rtl92d_phy_reload_lck_setting()
2479 "ver 1 set RF-A, 5G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2490 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2498 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", u4tmp); in _rtl92d_phy_reload_lck_setting()
2500 rtlpriv->rtlhal.interfaceindex == 0) { in _rtl92d_phy_reload_lck_setting()
2508 rtl_set_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800, u4tmp); in _rtl92d_phy_reload_lck_setting()
2510 "ver 3 set RF-B, 2G, 0x28 = 0x%x !!\n", in _rtl92d_phy_reload_lck_setting()
2511 rtl_get_rfreg(hw, erfpath, RF_SYN_G4, 0x3f800)); in _rtl92d_phy_reload_lck_setting()
2529 u32 curvecount_val[CV_CURVE_CNT * 2] = {0}; in _rtl92d_phy_lc_calibrate_sw()
2530 u16 timeout = 800, timecount = 0; in _rtl92d_phy_lc_calibrate_sw()
2533 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl92d_phy_lc_calibrate_sw()
2536 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2537 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl92d_phy_lc_calibrate_sw()
2539 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_lc_calibrate_sw()
2540 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F); in _rtl92d_phy_lc_calibrate_sw()
2541 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2543 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2547 RFREG_OFFSET_MASK, 0x010000); in _rtl92d_phy_lc_calibrate_sw()
2551 BIT(17), 0x0); in _rtl92d_phy_lc_calibrate_sw()
2554 0x08000, 0x01); in _rtl92d_phy_lc_calibrate_sw()
2567 if (index == 0 && rtlhal->interfaceindex == 0) { in _rtl92d_phy_lc_calibrate_sw()
2574 memset(curvecount_val, 0, sizeof(curvecount_val)); in _rtl92d_phy_lc_calibrate_sw()
2577 0x08000, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2578 RTPRINT(rtlpriv, FINIT, INIT_IQK, "set RF 0x18[15] = 0\n"); in _rtl92d_phy_lc_calibrate_sw()
2580 for (i = 0; i < CV_CURVE_CNT; i++) { in _rtl92d_phy_lc_calibrate_sw()
2581 u32 readval = 0, readval2 = 0; in _rtl92d_phy_lc_calibrate_sw()
2582 rtl_set_rfreg(hw, (enum radio_path)index, 0x3F, in _rtl92d_phy_lc_calibrate_sw()
2583 0x7f, i); in _rtl92d_phy_lc_calibrate_sw()
2585 rtl_set_rfreg(hw, (enum radio_path)index, 0x4D, in _rtl92d_phy_lc_calibrate_sw()
2586 RFREG_OFFSET_MASK, 0x0); in _rtl92d_phy_lc_calibrate_sw()
2588 0x4F, RFREG_OFFSET_MASK); in _rtl92d_phy_lc_calibrate_sw()
2589 curvecount_val[2 * i + 1] = (readval & 0xfffe0) >> 5; in _rtl92d_phy_lc_calibrate_sw()
2590 /* reg 0x4f [4:0] */ in _rtl92d_phy_lc_calibrate_sw()
2591 /* reg 0x50 [19:10] */ in _rtl92d_phy_lc_calibrate_sw()
2593 0x50, 0xffc00); in _rtl92d_phy_lc_calibrate_sw()
2594 curvecount_val[2 * i] = (((readval & 0x1F) << 10) | in _rtl92d_phy_lc_calibrate_sw()
2597 if (index == 0 && rtlhal->interfaceindex == 0) in _rtl92d_phy_lc_calibrate_sw()
2607 BIT(17), 0x1); in _rtl92d_phy_lc_calibrate_sw()
2611 for (index = 0; index < path; index++) { in _rtl92d_phy_lc_calibrate_sw()
2612 offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1; in _rtl92d_phy_lc_calibrate_sw()
2613 rtl_write_byte(rtlpriv, offset, 0x50); in _rtl92d_phy_lc_calibrate_sw()
2616 if ((tmpreg & 0x70) != 0) in _rtl92d_phy_lc_calibrate_sw()
2617 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl92d_phy_lc_calibrate_sw()
2619 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2620 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x00); in _rtl92d_phy_lc_calibrate_sw()
2637 u32 timeout = 2000, timecount = 0; in rtl92d_phy_lc_calibrate()
2694 /* 0xe94, 0xe9c, 0xea4, 0xeac, 0xeb4, 0xebc, 0xec4, 0xecc */ in rtl92d_phy_reset_iqk_result()
2695 for (i = 0; i < IQK_MATRIX_SETTINGS_NUM; i++) { in rtl92d_phy_reset_iqk_result()
2696 rtlphy->iqk_matrix[i].value[0][0] = 0x100; in rtl92d_phy_reset_iqk_result()
2697 rtlphy->iqk_matrix[i].value[0][2] = 0x100; in rtl92d_phy_reset_iqk_result()
2698 rtlphy->iqk_matrix[i].value[0][4] = 0x100; in rtl92d_phy_reset_iqk_result()
2699 rtlphy->iqk_matrix[i].value[0][6] = 0x100; in rtl92d_phy_reset_iqk_result()
2700 rtlphy->iqk_matrix[i].value[0][1] = 0x0; in rtl92d_phy_reset_iqk_result()
2701 rtlphy->iqk_matrix[i].value[0][3] = 0x0; in rtl92d_phy_reset_iqk_result()
2702 rtlphy->iqk_matrix[i].value[0][5] = 0x0; in rtl92d_phy_reset_iqk_result()
2703 rtlphy->iqk_matrix[i].value[0][7] = 0x0; in rtl92d_phy_reset_iqk_result()
2724 precommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2727 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2729 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2730 postcommoncmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2732 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2733 rfdependcmdcnt = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2736 RF_CHNLBW, channel, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2739 0, 0, 0); in _rtl92d_phy_sw_chnl_step_by_step()
2743 case 0: in _rtl92d_phy_sw_chnl_step_by_step()
2758 (*step) = 0; in _rtl92d_phy_sw_chnl_step_by_step()
2779 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92d_phy_sw_chnl_step_by_step()
2782 0xffffff00) | currentcmd->para2); in _rtl92d_phy_sw_chnl_step_by_step()
2828 u32 timeout = 1000, timecount = 0; in rtl92d_phy_sw_chnl()
2833 return 0; in rtl92d_phy_sw_chnl()
2835 return 0; in rtl92d_phy_sw_chnl()
2840 return 0; in rtl92d_phy_sw_chnl()
2850 if (rtlphy->current_channel > 14 && !(ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2852 else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0))) in rtl92d_phy_sw_chnl()
2860 return 0; in rtl92d_phy_sw_chnl()
2866 return 0; in rtl92d_phy_sw_chnl()
2874 if (channel == 0) in rtl92d_phy_sw_chnl()
2876 rtlphy->sw_chnl_stage = 0; in rtl92d_phy_sw_chnl()
2877 rtlphy->sw_chnl_step = 0; in rtl92d_phy_sw_chnl()
2887 if (delay > 0) in rtl92d_phy_sw_chnl()
2918 de_digtable->cur_igvalue = 0x37; in rtl92d_phy_set_io()
2973 /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */ in _rtl92d_phy_set_rfon()
2974 /* b. SPS_CTRL 0x11[7:0] = 0x2b */ in _rtl92d_phy_set_rfon()
2976 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in _rtl92d_phy_set_rfon()
2977 /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */ in _rtl92d_phy_set_rfon()
2978 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2980 /* d. APSD_CTRL 0x600[7:0] = 0x00 */ in _rtl92d_phy_set_rfon()
2981 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfon()
2982 /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */ in _rtl92d_phy_set_rfon()
2983 /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/ in _rtl92d_phy_set_rfon()
2984 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfon()
2985 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfon()
2986 /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */ in _rtl92d_phy_set_rfon()
2987 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfon()
2996 /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */ in _rtl92d_phy_set_rfsleep()
2997 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92d_phy_set_rfsleep()
2998 /* b. RF path 0 offset 0x00 = 0x00 disable RF */ in _rtl92d_phy_set_rfsleep()
2999 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3000 /* c. APSD_CTRL 0x600[7:0] = 0x40 */ in _rtl92d_phy_set_rfsleep()
3001 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3002 /* d. APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
3003 * APSD_CTRL 0x600[7:0] = 0x00 in _rtl92d_phy_set_rfsleep()
3004 * RF path 0 offset 0x00 = 0x00 in _rtl92d_phy_set_rfsleep()
3005 * APSD_CTRL 0x600[7:0] = 0x40 in _rtl92d_phy_set_rfsleep()
3007 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3008 while (u4btmp != 0 && delay > 0) { in _rtl92d_phy_set_rfsleep()
3009 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92d_phy_set_rfsleep()
3010 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92d_phy_set_rfsleep()
3011 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92d_phy_set_rfsleep()
3012 u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92d_phy_set_rfsleep()
3015 if (delay == 0) { in _rtl92d_phy_set_rfsleep()
3017 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92d_phy_set_rfsleep()
3019 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3020 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92d_phy_set_rfsleep()
3021 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92d_phy_set_rfsleep()
3026 /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */ in _rtl92d_phy_set_rfsleep()
3027 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92d_phy_set_rfsleep()
3028 /* f. SPS_CTRL 0x11[7:0] = 0x22 */ in _rtl92d_phy_set_rfsleep()
3030 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92d_phy_set_rfsleep()
3031 /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */ in _rtl92d_phy_set_rfsleep()
3054 u32 initializecount = 0; in rtl92d_phy_set_rf_power_state()
3100 for (queue_id = 0, i = 0; in rtl92d_phy_set_rf_power_state()
3103 if (skb_queue_len(&ring->queue) == 0 || in rtl92d_phy_set_rf_power_state()
3109 "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 but lower power state!\n", in rtl92d_phy_set_rf_power_state()
3161 rtl_write_byte(rtlpriv, offset, 0xF3); in rtl92d_phy_config_macphymode()
3166 rtl_write_byte(rtlpriv, offset, 0xF4); in rtl92d_phy_config_macphymode()
3171 rtl_write_byte(rtlpriv, offset, 0xF1); in rtl92d_phy_config_macphymode()
3201 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_config_macphymode_info()
3219 group = 0; in rtl92d_get_chnlgroup_fromarray()
3252 u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1); in rtl92d_phy_set_poweron()
3254 /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */ in rtl92d_phy_set_poweron()
3270 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_set_poweron()
3279 for (i = 0; i < 200; i++) { in rtl92d_phy_set_poweron()
3280 if ((value8 & BIT(7)) == 0) { in rtl92d_phy_set_poweron()
3302 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3303 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3304 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3307 rtl_write_byte(rtlpriv, REG_DMC, 0xf8); in rtl92d_phy_config_maccoexist_rfpage()
3308 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x08); in rtl92d_phy_config_maccoexist_rfpage()
3309 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x13ff); in rtl92d_phy_config_maccoexist_rfpage()
3312 rtl_write_byte(rtlpriv, REG_DMC, 0x0); in rtl92d_phy_config_maccoexist_rfpage()
3313 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x10); in rtl92d_phy_config_maccoexist_rfpage()
3314 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF); in rtl92d_phy_config_maccoexist_rfpage()
3330 /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */ in rtl92d_update_bbrf_configuration()
3332 /* r_select_5G for path_A/B,0x878 */ in rtl92d_update_bbrf_configuration()
3333 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0); in rtl92d_update_bbrf_configuration()
3334 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0); in rtl92d_update_bbrf_configuration()
3336 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0); in rtl92d_update_bbrf_configuration()
3337 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0); in rtl92d_update_bbrf_configuration()
3339 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */ in rtl92d_update_bbrf_configuration()
3340 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0); in rtl92d_update_bbrf_configuration()
3341 /* fc_area 0xd2c */ in rtl92d_update_bbrf_configuration()
3342 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0); in rtl92d_update_bbrf_configuration()
3344 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa); in rtl92d_update_bbrf_configuration()
3345 /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3347 0x40000100); in rtl92d_update_bbrf_configuration()
3349 0x40000100); in rtl92d_update_bbrf_configuration()
3359 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3360 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3361 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0); in rtl92d_update_bbrf_configuration()
3375 ((rtlefuse->eeprom_c9 & BIT(0)) << 1) | in rtl92d_update_bbrf_configuration()
3376 ((rtlefuse->eeprom_cc & BIT(0)) << 5)); in rtl92d_update_bbrf_configuration()
3383 BIT(31) | BIT(15), 0); in rtl92d_update_bbrf_configuration()
3388 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1); in rtl92d_update_bbrf_configuration()
3389 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1); in rtl92d_update_bbrf_configuration()
3391 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1); in rtl92d_update_bbrf_configuration()
3392 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1); in rtl92d_update_bbrf_configuration()
3394 /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */ in rtl92d_update_bbrf_configuration()
3395 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1); in rtl92d_update_bbrf_configuration()
3397 rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1); in rtl92d_update_bbrf_configuration()
3399 rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0); in rtl92d_update_bbrf_configuration()
3400 /* TX BB gain shift,Just for testchip,0xc80,0xc88 */ in rtl92d_update_bbrf_configuration()
3401 if (rtlefuse->internal_pa_5g[0]) in rtl92d_update_bbrf_configuration()
3403 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3406 0x20000080); in rtl92d_update_bbrf_configuration()
3409 0x2d4000b5); in rtl92d_update_bbrf_configuration()
3412 0x20000080); in rtl92d_update_bbrf_configuration()
3438 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3439 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, MASKDWORD, 0x40000100); in rtl92d_update_bbrf_configuration()
3440 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3442 BIT(26) | BIT(24), 0x00); in rtl92d_update_bbrf_configuration()
3443 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3444 rtl_set_bbreg(hw, 0xca0, 0xF0000000, 0x00); in rtl92d_update_bbrf_configuration()
3445 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, 0x00); in rtl92d_update_bbrf_configuration()
3451 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3453 BIT(18), 0); in rtl92d_update_bbrf_configuration()
3455 rtl_set_rfreg(hw, (enum radio_path)rfpath, 0x0B, in rtl92d_update_bbrf_configuration()
3456 0x1c000, 0x07); in rtl92d_update_bbrf_configuration()
3458 /* MOD_AG for RF path_A 0x18 BIT8,BIT16 */ in rtl92d_update_bbrf_configuration()
3467 /* Use antenna 0,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3468 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x11); in rtl92d_update_bbrf_configuration()
3469 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x1); in rtl92d_update_bbrf_configuration()
3472 if (rtlhal->interfaceindex == 0) { in rtl92d_update_bbrf_configuration()
3474 BIT(13), 0x3); in rtl92d_update_bbrf_configuration()
3478 "MAC1 use DBI to update 0x888\n"); in rtl92d_update_bbrf_configuration()
3479 /* 0x888 */ in rtl92d_update_bbrf_configuration()
3489 /* Use antenna 0 & 1,0xc04,0xd04 */ in rtl92d_update_bbrf_configuration()
3490 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x33); in rtl92d_update_bbrf_configuration()
3491 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0x3); in rtl92d_update_bbrf_configuration()
3492 /* disable ad/da clock1,0x888 */ in rtl92d_update_bbrf_configuration()
3493 rtl_set_bbreg(hw, RFPGA0_ADDALLOCKEN, BIT(12) | BIT(13), 0); in rtl92d_update_bbrf_configuration()
3499 rtlphy->reg_rf3c[rfpath] = rtl_get_rfreg(hw, rfpath, 0x3C, in rtl92d_update_bbrf_configuration()
3502 for (i = 0; i < 2; i++) in rtl92d_update_bbrf_configuration()
3503 rtl_dbg(rtlpriv, COMP_RF, DBG_LOUD, "RF 0x18 = 0x%x\n", in rtl92d_update_bbrf_configuration()
3522 if (rtlhal->interfaceindex == 0) { in rtl92d_phy_check_poweroff()