Lines Matching +full:0 +full:xeb4
24 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", in rtl92c_phy_query_bb_reg()
59 return 0; in _rtl92c_phy_fw_rf_serial_read()
79 u8 rfpi_enable = 0; in _rtl92c_phy_rf_serial_read()
82 offset &= 0x3f; in _rtl92c_phy_rf_serial_read()
86 return 0xFFFFFFFF; in _rtl92c_phy_rf_serial_read()
115 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_read()
136 offset &= 0x3f; in _rtl92c_phy_rf_serial_write()
138 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl92c_phy_rf_serial_write()
140 rtl_dbg(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n", in _rtl92c_phy_rf_serial_write()
156 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); in _rtl92c_phy_bb_config_1t()
157 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022); in _rtl92c_phy_bb_config_1t()
158 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45); in _rtl92c_phy_bb_config_1t()
159 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23); in _rtl92c_phy_bb_config_1t()
160 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1); in _rtl92c_phy_bb_config_1t()
161 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
162 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
163 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
164 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
165 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2); in _rtl92c_phy_bb_config_1t()
194 rtlphy->pwrgroup_cnt = 0; in _rtl92c_phy_bb8192c_config_parafile()
209 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl92c_phy_bb8192c_config_parafile()
224 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] = in _rtl92c_store_pwrindex_diffrate_offset()
227 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
230 [rtlphy->pwrgroup_cnt][0]); in _rtl92c_store_pwrindex_diffrate_offset()
236 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
245 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
250 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { in _rtl92c_store_pwrindex_diffrate_offset()
254 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
263 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
272 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
281 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
290 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
299 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
308 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
317 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
322 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { in _rtl92c_store_pwrindex_diffrate_offset()
326 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
335 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
344 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
353 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
362 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", in _rtl92c_store_pwrindex_diffrate_offset()
377 rtlphy->default_initialgain[0] = in rtl92c_phy_get_hw_reg_originalvalue()
387 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl92c_phy_get_hw_reg_originalvalue()
388 rtlphy->default_initialgain[0], in rtl92c_phy_get_hw_reg_originalvalue()
399 "Default framesync (0x%x) = 0x%x\n", in rtl92c_phy_get_hw_reg_originalvalue()
550 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl92c_ccxpower_index_check()
551 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl92c_ccxpower_index_check()
563 &cckpowerlevel[0], &ofdmpowerlevel[0]); in rtl92c_phy_set_txpower_level()
564 _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0], in rtl92c_phy_set_txpower_level()
565 &ofdmpowerlevel[0]); in rtl92c_phy_set_txpower_level()
566 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl92c_phy_set_txpower_level()
567 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], in rtl92c_phy_set_txpower_level()
583 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0) in rtl92c_phy_update_txpower_dbm()
586 ofdmtxpwridx = 0; in rtl92c_phy_update_txpower_dbm()
590 for (idx = 0; idx < 14; idx++) { in rtl92c_phy_update_txpower_dbm()
591 for (rf_path = 0; rf_path < 2; rf_path++) { in rtl92c_phy_update_txpower_dbm()
624 if ((power_indbm - offset) > 0) in _rtl92c_phy_dbm_to_txpwr_idx()
627 txpwridx = 0; in _rtl92c_phy_dbm_to_txpwr_idx()
699 if (delay > 0) in rtl92c_phy_sw_chnl_callback()
719 return 0; in rtl92c_phy_sw_chnl()
721 return 0; in rtl92c_phy_sw_chnl()
725 rtlphy->sw_chnl_stage = 0; in rtl92c_phy_sw_chnl()
726 rtlphy->sw_chnl_step = 0; in rtl92c_phy_sw_chnl()
751 MASKDWORD, 0x00255); in _rtl92c_phy_sw_rf_seting()
801 precommoncmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
804 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
806 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
808 postcommoncmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
811 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl92c_phy_sw_chnl_step_by_step()
813 rfdependcmdcnt = 0; in _rtl92c_phy_sw_chnl_step_by_step()
823 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, in _rtl92c_phy_sw_chnl_step_by_step()
824 0); in _rtl92c_phy_sw_chnl_step_by_step()
828 case 0: in _rtl92c_phy_sw_chnl_step_by_step()
848 (*step) = 0; in _rtl92c_phy_sw_chnl_step_by_step()
870 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl92c_phy_sw_chnl_step_by_step()
873 0xfffffc00) | currentcmd->para2); in _rtl92c_phy_sw_chnl_step_by_step()
906 u8 result = 0x00; in _rtl92c_phy_path_a_iqk()
908 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
909 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f); in _rtl92c_phy_path_a_iqk()
910 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
911 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, in _rtl92c_phy_path_a_iqk()
912 config_pathb ? 0x28160202 : 0x28160502); in _rtl92c_phy_path_a_iqk()
915 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
916 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22); in _rtl92c_phy_path_a_iqk()
917 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102); in _rtl92c_phy_path_a_iqk()
918 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202); in _rtl92c_phy_path_a_iqk()
921 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1); in _rtl92c_phy_path_a_iqk()
922 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl92c_phy_path_a_iqk()
923 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl92c_phy_path_a_iqk()
927 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92c_phy_path_a_iqk()
928 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl92c_phy_path_a_iqk()
929 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl92c_phy_path_a_iqk()
930 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl92c_phy_path_a_iqk()
933 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl92c_phy_path_a_iqk()
934 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl92c_phy_path_a_iqk()
935 result |= 0x01; in _rtl92c_phy_path_a_iqk()
940 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92c_phy_path_a_iqk()
941 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl92c_phy_path_a_iqk()
942 result |= 0x02; in _rtl92c_phy_path_a_iqk()
949 u8 result = 0x00; in _rtl92c_phy_path_b_iqk()
951 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl92c_phy_path_b_iqk()
952 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl92c_phy_path_b_iqk()
954 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl92c_phy_path_b_iqk()
955 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl92c_phy_path_b_iqk()
956 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl92c_phy_path_b_iqk()
957 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl92c_phy_path_b_iqk()
958 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl92c_phy_path_b_iqk()
961 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl92c_phy_path_b_iqk()
962 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl92c_phy_path_b_iqk()
963 result |= 0x01; in _rtl92c_phy_path_b_iqk()
967 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl92c_phy_path_b_iqk()
968 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl92c_phy_path_b_iqk()
969 result |= 0x02; in _rtl92c_phy_path_b_iqk()
980 if (final_candidate == 0xFF) { in _rtl92c_phy_path_a_fill_iqk_matrix()
984 MASKDWORD) >> 22) & 0x3FF; in _rtl92c_phy_path_a_fill_iqk_matrix()
985 x = result[final_candidate][0]; in _rtl92c_phy_path_a_fill_iqk_matrix()
986 if ((x & 0x00000200) != 0) in _rtl92c_phy_path_a_fill_iqk_matrix()
987 x = x | 0xFFFFFC00; in _rtl92c_phy_path_a_fill_iqk_matrix()
989 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl92c_phy_path_a_fill_iqk_matrix()
991 ((x * oldval_0 >> 7) & 0x1)); in _rtl92c_phy_path_a_fill_iqk_matrix()
993 if ((y & 0x00000200) != 0) in _rtl92c_phy_path_a_fill_iqk_matrix()
994 y = y | 0xFFFFFC00; in _rtl92c_phy_path_a_fill_iqk_matrix()
996 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl92c_phy_path_a_fill_iqk_matrix()
997 ((tx0_c & 0x3C0) >> 6)); in _rtl92c_phy_path_a_fill_iqk_matrix()
998 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_a_fill_iqk_matrix()
999 (tx0_c & 0x3F)); in _rtl92c_phy_path_a_fill_iqk_matrix()
1001 ((y * oldval_0 >> 7) & 0x1)); in _rtl92c_phy_path_a_fill_iqk_matrix()
1005 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
1006 reg = result[final_candidate][3] & 0x3F; in _rtl92c_phy_path_a_fill_iqk_matrix()
1007 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
1008 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl92c_phy_path_a_fill_iqk_matrix()
1009 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl92c_phy_path_a_fill_iqk_matrix()
1020 if (final_candidate == 0xFF) { in _rtl92c_phy_path_b_fill_iqk_matrix()
1024 MASKDWORD) >> 22) & 0x3FF; in _rtl92c_phy_path_b_fill_iqk_matrix()
1026 if ((x & 0x00000200) != 0) in _rtl92c_phy_path_b_fill_iqk_matrix()
1027 x = x | 0xFFFFFC00; in _rtl92c_phy_path_b_fill_iqk_matrix()
1029 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a); in _rtl92c_phy_path_b_fill_iqk_matrix()
1031 ((x * oldval_1 >> 7) & 0x1)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1033 if ((y & 0x00000200) != 0) in _rtl92c_phy_path_b_fill_iqk_matrix()
1034 y = y | 0xFFFFFC00; in _rtl92c_phy_path_b_fill_iqk_matrix()
1036 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000, in _rtl92c_phy_path_b_fill_iqk_matrix()
1037 ((tx1_c & 0x3C0) >> 6)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1038 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000, in _rtl92c_phy_path_b_fill_iqk_matrix()
1039 (tx1_c & 0x3F)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1041 ((y * oldval_1 >> 7) & 0x1)); in _rtl92c_phy_path_b_fill_iqk_matrix()
1045 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1046 reg = result[final_candidate][7] & 0x3F; in _rtl92c_phy_path_b_fill_iqk_matrix()
1047 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1048 reg = (result[final_candidate][7] >> 6) & 0xF; in _rtl92c_phy_path_b_fill_iqk_matrix()
1049 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg); in _rtl92c_phy_path_b_fill_iqk_matrix()
1059 for (i = 0; i < registernum; i++) in _rtl92c_phy_save_adda_registers()
1069 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92c_phy_save_mac_registers()
1080 for (i = 0; i < regiesternum; i++) in _rtl92c_phy_reload_adda_registers()
1090 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl92c_phy_reload_mac_registers()
1101 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl92c_phy_path_adda_on()
1103 pathon = 0x0bdb25a0; in _rtl92c_phy_path_adda_on()
1104 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl92c_phy_path_adda_on()
1106 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl92c_phy_path_adda_on()
1117 u32 i = 0; in _rtl92c_phy_mac_setting_calibration()
1119 rtl_write_byte(rtlpriv, macreg[i], 0x3F); in _rtl92c_phy_mac_setting_calibration()
1129 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl92c_phy_path_a_standby()
1130 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_path_a_standby()
1131 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_path_a_standby()
1138 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl92c_phy_pi_mode_switch()
1139 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1140 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl92c_phy_pi_mode_switch()
1149 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl92c_phy_simularity_compare()
1157 simularity_bitmap = 0; in _rtl92c_phy_simularity_compare()
1159 for (i = 0; i < bound; i++) { in _rtl92c_phy_simularity_compare()
1166 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl92c_phy_simularity_compare()
1168 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl92c_phy_simularity_compare()
1179 if (simularity_bitmap == 0) { in _rtl92c_phy_simularity_compare()
1180 for (i = 0; i < (bound / 4); i++) { in _rtl92c_phy_simularity_compare()
1181 if (final_candidate[i] != 0xFF) { in _rtl92c_phy_simularity_compare()
1189 } else if (!(simularity_bitmap & 0x0F)) { in _rtl92c_phy_simularity_compare()
1190 for (i = 0; i < 4; i++) in _rtl92c_phy_simularity_compare()
1193 } else if (!(simularity_bitmap & 0xF0) && is2t) { in _rtl92c_phy_simularity_compare()
1210 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl92c_phy_iq_calibrate()
1211 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl92c_phy_iq_calibrate()
1212 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl92c_phy_iq_calibrate()
1213 0xed8, 0xedc, 0xee0, 0xeec in _rtl92c_phy_iq_calibrate()
1216 0x522, 0x550, 0x551, 0x040 in _rtl92c_phy_iq_calibrate()
1220 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1221 rtl_get_bbreg(hw, 0x800, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1229 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1237 if (t == 0) { in _rtl92c_phy_iq_calibrate()
1238 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1239 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1240 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD); in _rtl92c_phy_iq_calibrate()
1242 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl92c_phy_iq_calibrate()
1243 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl92c_phy_iq_calibrate()
1244 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl92c_phy_iq_calibrate()
1246 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1247 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl92c_phy_iq_calibrate()
1251 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1253 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000); in _rtl92c_phy_iq_calibrate()
1254 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl92c_phy_iq_calibrate()
1255 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl92c_phy_iq_calibrate()
1256 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800); in _rtl92c_phy_iq_calibrate()
1257 for (i = 0; i < retrycount; i++) { in _rtl92c_phy_iq_calibrate()
1259 if (patha_ok == 0x03) { in _rtl92c_phy_iq_calibrate()
1260 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1261 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1262 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1263 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1264 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1265 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1266 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1267 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1269 } else if (i == (retrycount - 1) && patha_ok == 0x01) in _rtl92c_phy_iq_calibrate()
1271 result[t][0] = (rtl_get_bbreg(hw, 0xe94, in _rtl92c_phy_iq_calibrate()
1272 MASKDWORD) & 0x3FF0000) >> in _rtl92c_phy_iq_calibrate()
1275 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1282 for (i = 0; i < retrycount; i++) { in _rtl92c_phy_iq_calibrate()
1284 if (pathb_ok == 0x03) { in _rtl92c_phy_iq_calibrate()
1286 0xeb4, in _rtl92c_phy_iq_calibrate()
1288 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1290 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1291 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1293 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1294 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1296 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1297 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1299 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl92c_phy_iq_calibrate()
1301 0xeb4, in _rtl92c_phy_iq_calibrate()
1303 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1305 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl92c_phy_iq_calibrate()
1306 0x3FF0000) >> 16; in _rtl92c_phy_iq_calibrate()
1309 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04); in _rtl92c_phy_iq_calibrate()
1310 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874); in _rtl92c_phy_iq_calibrate()
1311 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08); in _rtl92c_phy_iq_calibrate()
1312 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl92c_phy_iq_calibrate()
1313 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1315 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl92c_phy_iq_calibrate()
1316 if (t != 0) { in _rtl92c_phy_iq_calibrate()
1337 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01); in _rtl92c_phy_set_rfpath_switch()
1338 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl92c_phy_set_rfpath_switch()
1343 BIT(5) | BIT(6), 0x1); in _rtl92c_phy_set_rfpath_switch()
1346 BIT(5) | BIT(6), 0x2); in _rtl92c_phy_set_rfpath_switch()
1349 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2); in _rtl92c_phy_set_rfpath_switch()
1351 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1); in _rtl92c_phy_set_rfpath_switch()
1368 reg_tmp = 0; in rtl92c_phy_iq_calibrate()
1389 for (i = 0; i < 8; i++) { in rtl92c_phy_iq_calibrate()
1390 result[0][i] = 0; in rtl92c_phy_iq_calibrate()
1391 result[1][i] = 0; in rtl92c_phy_iq_calibrate()
1392 result[2][i] = 0; in rtl92c_phy_iq_calibrate()
1393 result[3][i] = 0; in rtl92c_phy_iq_calibrate()
1395 final_candidate = 0xff; in rtl92c_phy_iq_calibrate()
1401 for (i = 0; i < 3; i++) { in rtl92c_phy_iq_calibrate()
1408 result, 0, in rtl92c_phy_iq_calibrate()
1411 final_candidate = 0; in rtl92c_phy_iq_calibrate()
1417 result, 0, in rtl92c_phy_iq_calibrate()
1420 final_candidate = 0; in rtl92c_phy_iq_calibrate()
1429 for (i = 0; i < 8; i++) in rtl92c_phy_iq_calibrate()
1432 if (reg_tmp != 0) in rtl92c_phy_iq_calibrate()
1435 final_candidate = 0xFF; in rtl92c_phy_iq_calibrate()
1439 for (i = 0; i < 4; i++) { in rtl92c_phy_iq_calibrate()
1440 reg_e94 = result[i][0]; in rtl92c_phy_iq_calibrate()
1447 if (final_candidate != 0xff) { in rtl92c_phy_iq_calibrate()
1448 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0]; in rtl92c_phy_iq_calibrate()
1457 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100; in rtl92c_phy_iq_calibrate()
1458 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; in rtl92c_phy_iq_calibrate()
1460 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ in rtl92c_phy_iq_calibrate()
1463 (reg_ea4 == 0)); in rtl92c_phy_iq_calibrate()
1465 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */ in rtl92c_phy_iq_calibrate()
1469 (reg_ec4 == 0)); in rtl92c_phy_iq_calibrate()
1570 dm_digtable->cur_igvalue = 0x17; in rtl92c_phy_set_io()
1589 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl92ce_phy_set_rf_on()
1590 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ce_phy_set_rf_on()
1591 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in rtl92ce_phy_set_rf_on()
1592 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl92ce_phy_set_rf_on()
1593 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl92ce_phy_set_rf_on()
1594 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl92ce_phy_set_rf_on()
1604 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl92c_phy_set_rf_sleep()
1605 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92c_phy_set_rf_sleep()
1606 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92c_phy_set_rf_sleep()
1607 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92c_phy_set_rf_sleep()
1608 while (u4b_tmp != 0 && delay > 0) { in _rtl92c_phy_set_rf_sleep()
1609 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0); in _rtl92c_phy_set_rf_sleep()
1610 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl92c_phy_set_rf_sleep()
1611 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); in _rtl92c_phy_set_rf_sleep()
1612 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK); in _rtl92c_phy_set_rf_sleep()
1615 if (delay == 0) { in _rtl92c_phy_set_rf_sleep()
1616 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00); in _rtl92c_phy_set_rf_sleep()
1617 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92c_phy_set_rf_sleep()
1618 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in _rtl92c_phy_set_rf_sleep()
1619 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl92c_phy_set_rf_sleep()
1624 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl92c_phy_set_rf_sleep()
1625 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl92c_phy_set_rf_sleep()