Lines Matching +full:0 +full:xeb4
58 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, in rtl88e_phy_query_bb_reg()
154 u8 rfpi_enable = 0; in _rtl88e_phy_rf_serial_read()
157 offset &= 0xff; in _rtl88e_phy_rf_serial_read()
161 return 0xFFFFFFFF; in _rtl88e_phy_rf_serial_read()
188 "RFR-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_read()
207 offset &= 0xff; in _rtl88e_phy_rf_serial_write()
209 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff; in _rtl88e_phy_rf_serial_write()
212 "RFW-%d Addr[0x%x]=0x%x\n", in _rtl88e_phy_rf_serial_write()
221 rtl_write_byte(rtlpriv, 0x04CA, 0x0B); in rtl88e_phy_mac_config()
235 regval | BIT(13) | BIT(0) | BIT(1)); in rtl88e_phy_bb_config()
241 tmp = rtl_read_dword(rtlpriv, 0x4c); in rtl88e_phy_bb_config()
242 rtl_write_dword(rtlpriv, 0x4c, tmp | BIT(23)); in rtl88e_phy_bb_config()
260 u32 _platform = 0x08;/*SupportPlatform */ in _rtl88e_check_condition()
263 if (condition == 0xCDCDCDCD) in _rtl88e_check_condition()
266 cond = condition & 0xFF; in _rtl88e_check_condition()
267 if ((_board & cond) == 0 && cond != 0x1F) in _rtl88e_check_condition()
270 cond = condition & 0xFF00; in _rtl88e_check_condition()
272 if ((_interface & cond) == 0 && cond != 0x07) in _rtl88e_check_condition()
275 cond = condition & 0xFF0000; in _rtl88e_check_condition()
277 if ((_platform & cond) == 0 && cond != 0x0F) in _rtl88e_check_condition()
286 if (addr == 0xffe) { in _rtl8188e_config_rf_reg()
288 } else if (addr == 0xfd) { in _rtl8188e_config_rf_reg()
290 } else if (addr == 0xfc) { in _rtl8188e_config_rf_reg()
292 } else if (addr == 0xfb) { in _rtl8188e_config_rf_reg()
294 } else if (addr == 0xfa) { in _rtl8188e_config_rf_reg()
296 } else if (addr == 0xf9) { in _rtl8188e_config_rf_reg()
309 u32 content = 0x1000; /*RF Content: radio_a_txt*/ in _rtl8188e_config_rf_radio_a()
310 u32 maskforphyset = (u32)(content & 0xE000); in _rtl8188e_config_rf_radio_a()
319 if (addr == 0xfe) { in _rtl8188e_config_bb_reg()
321 } else if (addr == 0xfd) { in _rtl8188e_config_bb_reg()
323 } else if (addr == 0xfc) { in _rtl8188e_config_bb_reg()
325 } else if (addr == 0xfb) { in _rtl8188e_config_bb_reg()
327 } else if (addr == 0xfa) { in _rtl8188e_config_bb_reg()
329 } else if (addr == 0xf9) { in _rtl8188e_config_bb_reg()
351 rtlphy->pwrgroup_cnt = 0; in _rtl88e_phy_bb8188e_config_parafile()
366 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200)); in _rtl88e_phy_bb8188e_config_parafile()
383 for (i = 0; i < arraylength; i = i + 2) in _rtl88e_phy_config_mac_with_headerfile()
392 } while (0)
401 for (i = 0; i < arraylen; i = i + 2) { in handle_branch1()
404 if (v1 < 0xcdcdcdcd) { in handle_branch1()
414 while (v2 != 0xDEAD && in handle_branch1()
415 v2 != 0xCDEF && in handle_branch1()
416 v2 != 0xCDCD && i < arraylen - 2) in handle_branch1()
423 while (v2 != 0xDEAD && in handle_branch1()
424 v2 != 0xCDEF && in handle_branch1()
425 v2 != 0xCDCD && i < arraylen - 2) { in handle_branch1()
430 while (v2 != 0xDEAD && i < arraylen - 2) in handle_branch1()
445 for (i = 0; i < arraylen; i = i + 2) { in handle_branch2()
448 if (v1 < 0xCDCDCDCD) { in handle_branch2()
461 while (v2 != 0xDEAD && in handle_branch2()
462 v2 != 0xCDEF && in handle_branch2()
463 v2 != 0xCDCD && i < arraylen - 2) in handle_branch2()
470 while (v2 != 0xDEAD && in handle_branch2()
471 v2 != 0xCDEF && in handle_branch2()
472 v2 != 0xCDCD && i < arraylen - 2) { in handle_branch2()
480 while (v2 != 0xDEAD && i < arraylen - 2) in handle_branch2()
485 "The agctab_array_table[0] is %x Rtl818EEPHY_REGArray[1] is %x\n", in handle_branch2()
517 rtlphy->mcs_txpwrlevel_origoffset[count][0] = data; in store_pwrindex_rate_offset()
519 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n", in store_pwrindex_rate_offset()
521 rtlphy->mcs_txpwrlevel_origoffset[count][0]); in store_pwrindex_rate_offset()
526 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n", in store_pwrindex_rate_offset()
533 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n", in store_pwrindex_rate_offset()
537 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) { in store_pwrindex_rate_offset()
540 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n", in store_pwrindex_rate_offset()
547 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n", in store_pwrindex_rate_offset()
554 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n", in store_pwrindex_rate_offset()
561 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n", in store_pwrindex_rate_offset()
572 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n", in store_pwrindex_rate_offset()
579 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n", in store_pwrindex_rate_offset()
586 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n", in store_pwrindex_rate_offset()
593 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n", in store_pwrindex_rate_offset()
597 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) { in store_pwrindex_rate_offset()
600 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n", in store_pwrindex_rate_offset()
607 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n", in store_pwrindex_rate_offset()
614 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n", in store_pwrindex_rate_offset()
621 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n", in store_pwrindex_rate_offset()
628 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n", in store_pwrindex_rate_offset()
644 u32 v1 = 0, v2 = 0; in phy_config_bb_with_pghdr()
650 for (i = 0; i < phy_reg_page_len; i = i + 3) { in phy_config_bb_with_pghdr()
654 if (v1 < 0xcdcdcdcd) { in phy_config_bb_with_pghdr()
655 if (phy_reg_page[i] == 0xfe) in phy_config_bb_with_pghdr()
657 else if (phy_reg_page[i] == 0xfd) in phy_config_bb_with_pghdr()
659 else if (phy_reg_page[i] == 0xfc) in phy_config_bb_with_pghdr()
661 else if (phy_reg_page[i] == 0xfb) in phy_config_bb_with_pghdr()
663 else if (phy_reg_page[i] == 0xfa) in phy_config_bb_with_pghdr()
665 else if (phy_reg_page[i] == 0xf9) in phy_config_bb_with_pghdr()
683 while (v2 != 0xDEAD && in phy_config_bb_with_pghdr()
704 } while (0)
714 for (i = 0; i < radioa_arraylen; i = i + 2) { in process_path_a()
717 if (v1 < 0xcdcdcdcd) { in process_path_a()
727 while (v2 != 0xDEAD && in process_path_a()
728 v2 != 0xCDEF && in process_path_a()
729 v2 != 0xCDCD && in process_path_a()
738 while (v2 != 0xDEAD && in process_path_a()
739 v2 != 0xCDEF && in process_path_a()
740 v2 != 0xCDCD && in process_path_a()
746 while (v2 != 0xDEAD && in process_path_a()
754 _rtl8188e_config_rf_radio_a(hw, 0x52, 0x7E4BD); in process_path_a()
786 rtlphy->default_initialgain[0] = in rtl88e_phy_get_hw_reg_originalvalue()
796 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n", in rtl88e_phy_get_hw_reg_originalvalue()
797 rtlphy->default_initialgain[0], in rtl88e_phy_get_hw_reg_originalvalue()
808 "Default framesync (0x%x) = 0x%x\n", in rtl88e_phy_get_hw_reg_originalvalue()
932 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][index] > 0x0f) in handle_path_a()
940 if (rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][index] > 0xf) in handle_path_a()
958 u8 rf_path = 0; in _rtl88e_get_txpower_index()
960 for (rf_path = 0; rf_path < 2; rf_path++) { in _rtl88e_get_txpower_index()
989 rtlphy->cur_cck_txpwridx = cckpowerlevel[0]; in _rtl88e_ccxpower_index_check()
990 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0]; in _rtl88e_ccxpower_index_check()
991 rtlphy->cur_bw20_txpwridx = bw20powerlevel[0]; in _rtl88e_ccxpower_index_check()
992 rtlphy->cur_bw40_txpwridx = bw40powerlevel[0]; in _rtl88e_ccxpower_index_check()
999 u8 cckpowerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
1000 u8 ofdmpowerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
1001 u8 bw20powerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
1002 u8 bw40powerlevel[MAX_TX_COUNT] = {0}; in rtl88e_phy_set_txpower_level()
1007 &cckpowerlevel[0], &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1008 &bw20powerlevel[0], &bw40powerlevel[0]); in rtl88e_phy_set_txpower_level()
1010 &cckpowerlevel[0], &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1011 &bw20powerlevel[0], &bw40powerlevel[0]); in rtl88e_phy_set_txpower_level()
1012 rtl88e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]); in rtl88e_phy_set_txpower_level()
1013 rtl88e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], in rtl88e_phy_set_txpower_level()
1014 &bw20powerlevel[0], in rtl88e_phy_set_txpower_level()
1015 &bw40powerlevel[0], channel); in rtl88e_phy_set_txpower_level()
1100 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5); in rtl88e_phy_set_bw_mode_callback()
1111 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1112 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0); in rtl88e_phy_set_bw_mode_callback()
1116 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1117 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1); in rtl88e_phy_set_bw_mode_callback()
1121 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc); in rtl88e_phy_set_bw_mode_callback()
1122 /*rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);*/ in rtl88e_phy_set_bw_mode_callback()
1124 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)), in rtl88e_phy_set_bw_mode_callback()
1176 if (delay > 0) in rtl88e_phy_sw_chnl_callback()
1195 return 0; in rtl88e_phy_sw_chnl()
1197 return 0; in rtl88e_phy_sw_chnl()
1201 rtlphy->sw_chnl_stage = 0; in rtl88e_phy_sw_chnl()
1202 rtlphy->sw_chnl_step = 0; in rtl88e_phy_sw_chnl()
1233 precommoncmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1236 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1238 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1240 postcommoncmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1243 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); in _rtl88e_phy_sw_chnl_step_by_step()
1245 rfdependcmdcnt = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1255 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, in _rtl88e_phy_sw_chnl_step_by_step()
1256 0); in _rtl88e_phy_sw_chnl_step_by_step()
1260 case 0: in _rtl88e_phy_sw_chnl_step_by_step()
1279 (*step) = 0; in _rtl88e_phy_sw_chnl_step_by_step()
1300 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) { in _rtl88e_phy_sw_chnl_step_by_step()
1303 0xfffffc00) | currentcmd->para2); in _rtl88e_phy_sw_chnl_step_by_step()
1352 u8 result = 0x00; in _rtl88e_phy_path_a_iqk()
1354 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_iqk()
1355 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_iqk()
1356 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x8214032a); in _rtl88e_phy_path_a_iqk()
1357 rtl_set_bbreg(hw, 0xe3c, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_iqk()
1359 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x00462911); in _rtl88e_phy_path_a_iqk()
1360 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_iqk()
1361 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_iqk()
1365 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1366 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1367 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1368 rtl_get_bbreg(hw, 0xea4, MASKDWORD); in _rtl88e_phy_path_a_iqk()
1371 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_a_iqk()
1372 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_a_iqk()
1373 result |= 0x01; in _rtl88e_phy_path_a_iqk()
1380 u8 result = 0x00; in _rtl88e_phy_path_b_iqk()
1382 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002); in _rtl88e_phy_path_b_iqk()
1383 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000); in _rtl88e_phy_path_b_iqk()
1385 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1386 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1387 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1388 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1389 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD); in _rtl88e_phy_path_b_iqk()
1392 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_b_iqk()
1393 (((reg_ebc & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_b_iqk()
1394 result |= 0x01; in _rtl88e_phy_path_b_iqk()
1398 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) && in _rtl88e_phy_path_b_iqk()
1399 (((reg_ecc & 0x03FF0000) >> 16) != 0x36)) in _rtl88e_phy_path_b_iqk()
1400 result |= 0x02; in _rtl88e_phy_path_b_iqk()
1407 u8 result = 0x00; in _rtl88e_phy_path_a_rx_iqk()
1411 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1412 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1413 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1414 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1415 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf117b); in _rtl88e_phy_path_a_rx_iqk()
1416 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1419 rtl_set_bbreg(hw, RTX_IQK, MASKDWORD, 0x01007c00); in _rtl88e_phy_path_a_rx_iqk()
1420 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x81004800); in _rtl88e_phy_path_a_rx_iqk()
1423 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1424 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1425 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160804); in _rtl88e_phy_path_a_rx_iqk()
1426 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160000); in _rtl88e_phy_path_a_rx_iqk()
1429 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1431 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1432 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1442 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) && in _rtl88e_phy_path_a_rx_iqk()
1443 (((reg_e9c & 0x03FF0000) >> 16) != 0x42)) in _rtl88e_phy_path_a_rx_iqk()
1444 result |= 0x01; in _rtl88e_phy_path_a_rx_iqk()
1448 u32temp = 0x80007C00 | (reg_e94&0x3FF0000) | in _rtl88e_phy_path_a_rx_iqk()
1449 ((reg_e9c&0x3FF0000) >> 16); in _rtl88e_phy_path_a_rx_iqk()
1453 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x00000000); in _rtl88e_phy_path_a_rx_iqk()
1454 rtl_set_rfreg(hw, RF90_PATH_A, RF_WE_LUT, RFREG_OFFSET_MASK, 0x800a0); in _rtl88e_phy_path_a_rx_iqk()
1455 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK_OS, RFREG_OFFSET_MASK, 0x30000); in _rtl88e_phy_path_a_rx_iqk()
1456 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G1, RFREG_OFFSET_MASK, 0x0000f); in _rtl88e_phy_path_a_rx_iqk()
1457 rtl_set_rfreg(hw, RF90_PATH_A, RF_TXPA_G2, RFREG_OFFSET_MASK, 0xf7ffa); in _rtl88e_phy_path_a_rx_iqk()
1458 rtl_set_bbreg(hw, RFPGA0_IQK, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_rx_iqk()
1461 rtl_set_bbreg(hw, RRX_IQK, MASKDWORD, 0x01004800); in _rtl88e_phy_path_a_rx_iqk()
1464 rtl_set_bbreg(hw, RTX_IQK_TONE_A, MASKDWORD, 0x30008c1c); in _rtl88e_phy_path_a_rx_iqk()
1465 rtl_set_bbreg(hw, RRX_IQK_TONE_A, MASKDWORD, 0x10008c1c); in _rtl88e_phy_path_a_rx_iqk()
1466 rtl_set_bbreg(hw, RTX_IQK_PI_A, MASKDWORD, 0x82160c05); in _rtl88e_phy_path_a_rx_iqk()
1467 rtl_set_bbreg(hw, RRX_IQK_PI_A, MASKDWORD, 0x28160c05); in _rtl88e_phy_path_a_rx_iqk()
1470 rtl_set_bbreg(hw, RIQK_AGC_RSP, MASKDWORD, 0x0046a911); in _rtl88e_phy_path_a_rx_iqk()
1472 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf9000000); in _rtl88e_phy_path_a_rx_iqk()
1473 rtl_set_bbreg(hw, RIQK_AGC_PTS, MASKDWORD, 0xf8000000); in _rtl88e_phy_path_a_rx_iqk()
1483 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) && in _rtl88e_phy_path_a_rx_iqk()
1484 (((reg_eac & 0x03FF0000) >> 16) != 0x36)) in _rtl88e_phy_path_a_rx_iqk()
1485 result |= 0x02; in _rtl88e_phy_path_a_rx_iqk()
1496 if (final_candidate == 0xFF) { in _rtl88e_phy_path_a_fill_iqk_matrix()
1500 MASKDWORD) >> 22) & 0x3FF; in _rtl88e_phy_path_a_fill_iqk_matrix()
1501 x = result[final_candidate][0]; in _rtl88e_phy_path_a_fill_iqk_matrix()
1502 if ((x & 0x00000200) != 0) in _rtl88e_phy_path_a_fill_iqk_matrix()
1503 x = x | 0xFFFFFC00; in _rtl88e_phy_path_a_fill_iqk_matrix()
1505 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a); in _rtl88e_phy_path_a_fill_iqk_matrix()
1507 ((x * oldval_0 >> 7) & 0x1)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1509 if ((y & 0x00000200) != 0) in _rtl88e_phy_path_a_fill_iqk_matrix()
1510 y = y | 0xFFFFFC00; in _rtl88e_phy_path_a_fill_iqk_matrix()
1512 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1513 ((tx0_c & 0x3C0) >> 6)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1514 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000, in _rtl88e_phy_path_a_fill_iqk_matrix()
1515 (tx0_c & 0x3F)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1517 ((y * oldval_0 >> 7) & 0x1)); in _rtl88e_phy_path_a_fill_iqk_matrix()
1521 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1522 reg = result[final_candidate][3] & 0x3F; in _rtl88e_phy_path_a_fill_iqk_matrix()
1523 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1524 reg = (result[final_candidate][3] >> 6) & 0xF; in _rtl88e_phy_path_a_fill_iqk_matrix()
1525 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg); in _rtl88e_phy_path_a_fill_iqk_matrix()
1535 for (i = 0; i < registernum; i++) in _rtl88e_phy_save_adda_registers()
1545 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl88e_phy_save_mac_registers()
1556 for (i = 0; i < regiesternum; i++) in _rtl88e_phy_reload_adda_registers()
1566 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++) in _rtl88e_phy_reload_mac_registers()
1577 pathon = is_patha_on ? 0x04db25a4 : 0x0b1b25a4; in _rtl88e_phy_path_adda_on()
1579 pathon = 0x0bdb25a0; in _rtl88e_phy_path_adda_on()
1580 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0); in _rtl88e_phy_path_adda_on()
1582 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathon); in _rtl88e_phy_path_adda_on()
1593 u32 i = 0; in _rtl88e_phy_mac_setting_calibration()
1595 rtl_write_byte(rtlpriv, macreg[i], 0x3F); in _rtl88e_phy_mac_setting_calibration()
1605 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0); in _rtl88e_phy_path_a_standby()
1606 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_path_a_standby()
1607 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_path_a_standby()
1614 mode = pi_mode ? 0x01000100 : 0x01000000; in _rtl88e_phy_pi_mode_switch()
1615 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1616 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode); in _rtl88e_phy_pi_mode_switch()
1625 u8 final_candidate[2] = { 0xFF, 0xFF }; in _rtl88e_phy_simularity_compare()
1633 simularity_bitmap = 0; in _rtl88e_phy_simularity_compare()
1635 for (i = 0; i < bound; i++) { in _rtl88e_phy_simularity_compare()
1642 if (result[c1][i] + result[c1][i + 1] == 0) in _rtl88e_phy_simularity_compare()
1644 else if (result[c2][i] + result[c2][i + 1] == 0) in _rtl88e_phy_simularity_compare()
1655 if (simularity_bitmap == 0) { in _rtl88e_phy_simularity_compare()
1656 for (i = 0; i < (bound / 4); i++) { in _rtl88e_phy_simularity_compare()
1657 if (final_candidate[i] != 0xFF) { in _rtl88e_phy_simularity_compare()
1665 } else if (!(simularity_bitmap & 0x0F)) { in _rtl88e_phy_simularity_compare()
1666 for (i = 0; i < 4; i++) in _rtl88e_phy_simularity_compare()
1669 } else if (!(simularity_bitmap & 0xF0) && is2t) { in _rtl88e_phy_simularity_compare()
1687 0x85c, 0xe6c, 0xe70, 0xe74, in _rtl88e_phy_iq_calibrate()
1688 0xe78, 0xe7c, 0xe80, 0xe84, in _rtl88e_phy_iq_calibrate()
1689 0xe88, 0xe8c, 0xed0, 0xed4, in _rtl88e_phy_iq_calibrate()
1690 0xed8, 0xedc, 0xee0, 0xeec in _rtl88e_phy_iq_calibrate()
1693 0x522, 0x550, 0x551, 0x040 in _rtl88e_phy_iq_calibrate()
1697 RFPGA0_XCD_RFINTERFACESW, 0xb68, 0xb6c, in _rtl88e_phy_iq_calibrate()
1698 0x870, 0x860, 0x864, 0x800 in _rtl88e_phy_iq_calibrate()
1702 if (t == 0) { in _rtl88e_phy_iq_calibrate()
1712 if (t == 0) { in _rtl88e_phy_iq_calibrate()
1720 rtl_set_bbreg(hw, 0x800, BIT(24), 0x00); in _rtl88e_phy_iq_calibrate()
1721 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600); in _rtl88e_phy_iq_calibrate()
1722 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4); in _rtl88e_phy_iq_calibrate()
1723 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000); in _rtl88e_phy_iq_calibrate()
1725 rtl_set_bbreg(hw, 0x870, BIT(10), 0x01); in _rtl88e_phy_iq_calibrate()
1726 rtl_set_bbreg(hw, 0x870, BIT(26), 0x01); in _rtl88e_phy_iq_calibrate()
1727 rtl_set_bbreg(hw, 0x860, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1728 rtl_set_bbreg(hw, 0x864, BIT(10), 0x00); in _rtl88e_phy_iq_calibrate()
1731 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1732 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); in _rtl88e_phy_iq_calibrate()
1736 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1738 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x0f600000); in _rtl88e_phy_iq_calibrate()
1740 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000); in _rtl88e_phy_iq_calibrate()
1741 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00); in _rtl88e_phy_iq_calibrate()
1742 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x81004800); in _rtl88e_phy_iq_calibrate()
1743 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1745 if (patha_ok == 0x01) { in _rtl88e_phy_iq_calibrate()
1748 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1749 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1750 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1751 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1756 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1758 if (patha_ok == 0x03) { in _rtl88e_phy_iq_calibrate()
1761 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1762 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1763 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1764 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1772 if (0 == patha_ok) in _rtl88e_phy_iq_calibrate()
1778 for (i = 0; i < retrycount; i++) { in _rtl88e_phy_iq_calibrate()
1780 if (pathb_ok == 0x03) { in _rtl88e_phy_iq_calibrate()
1782 0xeb4, in _rtl88e_phy_iq_calibrate()
1784 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1786 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1787 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1789 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1790 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1792 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1793 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1795 } else if (i == (retrycount - 1) && pathb_ok == 0x01) { in _rtl88e_phy_iq_calibrate()
1797 0xeb4, in _rtl88e_phy_iq_calibrate()
1799 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1801 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) & in _rtl88e_phy_iq_calibrate()
1802 0x3FF0000) >> 16; in _rtl88e_phy_iq_calibrate()
1806 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0); in _rtl88e_phy_iq_calibrate()
1808 if (t != 0) { in _rtl88e_phy_iq_calibrate()
1819 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1821 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); in _rtl88e_phy_iq_calibrate()
1822 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1823 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x01008c00); in _rtl88e_phy_iq_calibrate()
1831 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; in _rtl88e_phy_lc_calibrate()
1834 tmpreg = rtl_read_byte(rtlpriv, 0xd03); in _rtl88e_phy_lc_calibrate()
1836 if ((tmpreg & 0x70) != 0) in _rtl88e_phy_lc_calibrate()
1837 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F); in _rtl88e_phy_lc_calibrate()
1839 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl88e_phy_lc_calibrate()
1841 if ((tmpreg & 0x70) != 0) { in _rtl88e_phy_lc_calibrate()
1842 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1845 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00, in _rtl88e_phy_lc_calibrate()
1848 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1849 (rf_a_mode & 0x8FFFF) | 0x10000); in _rtl88e_phy_lc_calibrate()
1852 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1853 (rf_b_mode & 0x8FFFF) | 0x10000); in _rtl88e_phy_lc_calibrate()
1855 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS); in _rtl88e_phy_lc_calibrate()
1857 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000); in _rtl88e_phy_lc_calibrate()
1861 if ((tmpreg & 0x70) != 0) { in _rtl88e_phy_lc_calibrate()
1862 rtl_write_byte(rtlpriv, 0xd03, tmpreg); in _rtl88e_phy_lc_calibrate()
1863 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode); in _rtl88e_phy_lc_calibrate()
1866 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS, in _rtl88e_phy_lc_calibrate()
1869 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in _rtl88e_phy_lc_calibrate()
1886 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01); in _rtl88e_phy_set_rfpath_switch()
1891 BIT(5) | BIT(6), 0x1); in _rtl88e_phy_set_rfpath_switch()
1894 BIT(5) | BIT(6), 0x2); in _rtl88e_phy_set_rfpath_switch()
1896 rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW, BIT(8) | BIT(9), 0); in _rtl88e_phy_set_rfpath_switch()
1897 rtl_set_bbreg(hw, 0x914, MASKLWORD, 0x0201); in _rtl88e_phy_set_rfpath_switch()
1905 BIT(14) | BIT(13) | BIT(12), 0); in _rtl88e_phy_set_rfpath_switch()
1907 BIT(5) | BIT(4) | BIT(3), 0); in _rtl88e_phy_set_rfpath_switch()
1909 rtl_set_bbreg(hw, RCONFIG_RAM64x16, BIT(31), 0); in _rtl88e_phy_set_rfpath_switch()
1932 reg_tmp = 0; in rtl88e_phy_iq_calibrate()
1953 for (i = 0; i < 8; i++) { in rtl88e_phy_iq_calibrate()
1954 result[0][i] = 0; in rtl88e_phy_iq_calibrate()
1955 result[1][i] = 0; in rtl88e_phy_iq_calibrate()
1956 result[2][i] = 0; in rtl88e_phy_iq_calibrate()
1957 result[3][i] = 0; in rtl88e_phy_iq_calibrate()
1959 final_candidate = 0xff; in rtl88e_phy_iq_calibrate()
1964 for (i = 0; i < 3; i++) { in rtl88e_phy_iq_calibrate()
1971 _rtl88e_phy_simularity_compare(hw, result, 0, 1); in rtl88e_phy_iq_calibrate()
1973 final_candidate = 0; in rtl88e_phy_iq_calibrate()
1979 _rtl88e_phy_simularity_compare(hw, result, 0, 2); in rtl88e_phy_iq_calibrate()
1981 final_candidate = 0; in rtl88e_phy_iq_calibrate()
1989 for (i = 0; i < 8; i++) in rtl88e_phy_iq_calibrate()
1992 if (reg_tmp != 0) in rtl88e_phy_iq_calibrate()
1995 final_candidate = 0xFF; in rtl88e_phy_iq_calibrate()
1999 for (i = 0; i < 4; i++) { in rtl88e_phy_iq_calibrate()
2000 reg_e94 = result[i][0]; in rtl88e_phy_iq_calibrate()
2006 if (final_candidate != 0xff) { in rtl88e_phy_iq_calibrate()
2007 reg_e94 = result[final_candidate][0]; in rtl88e_phy_iq_calibrate()
2018 rtlphy->reg_e94 = 0x100; in rtl88e_phy_iq_calibrate()
2019 rtlphy->reg_eb4 = 0x100; in rtl88e_phy_iq_calibrate()
2020 rtlphy->reg_e9c = 0x0; in rtl88e_phy_iq_calibrate()
2021 rtlphy->reg_ebc = 0x0; in rtl88e_phy_iq_calibrate()
2023 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ in rtl88e_phy_iq_calibrate()
2026 (reg_ea4 == 0)); in rtl88e_phy_iq_calibrate()
2027 if (final_candidate != 0xFF) { in rtl88e_phy_iq_calibrate()
2028 for (i = 0; i < IQK_MATRIX_REG_NUM; i++) in rtl88e_phy_iq_calibrate()
2029 rtlphy->iqk_matrix[0].value[0][i] = in rtl88e_phy_iq_calibrate()
2031 rtlphy->iqk_matrix[0].iqk_done = true; in rtl88e_phy_iq_calibrate()
2043 u32 timeout = 2000, timecount = 0; in rtl88e_phy_lc_calibrate()
2117 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x83); in rtl88e_phy_set_io()
2121 dm_digtable->cur_igvalue = 0x17; in rtl88e_phy_set_io()
2122 rtl_set_bbreg(hw, RCCK0_CCA, 0xff0000, 0x40); in rtl88e_phy_set_io()
2139 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b); in rtl88ee_phy_set_rf_on()
2140 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl88ee_phy_set_rf_on()
2141 /*rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);*/ in rtl88ee_phy_set_rf_on()
2142 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in rtl88ee_phy_set_rf_on()
2143 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); in rtl88ee_phy_set_rf_on()
2144 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00); in rtl88ee_phy_set_rf_on()
2151 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF); in _rtl88ee_phy_set_rf_sleep()
2152 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00); in _rtl88ee_phy_set_rf_sleep()
2153 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); in _rtl88ee_phy_set_rf_sleep()
2154 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22); in _rtl88ee_phy_set_rf_sleep()
2173 u32 initializecount = 0; in _rtl88ee_phy_set_rf_power_state()
2201 for (queue_id = 0, i = 0; in _rtl88ee_phy_set_rf_power_state()
2205 skb_queue_len(&ring->queue) == 0) { in _rtl88ee_phy_set_rf_power_state()
2245 for (queue_id = 0, i = 0; in _rtl88ee_phy_set_rf_power_state()
2248 if (skb_queue_len(&ring->queue) == 0) { in _rtl88ee_phy_set_rf_power_state()