419 	sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);  in rtl8192fu_identify_chip()
426 	val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);  in rtl8192fu_identify_chip()
435 	val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);  in rtl8192fu_identify_chip()
690 	agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);  in rtl8192fu_init_aggregation()
797 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);  in rtl8192f_phy_lc_calibrate()
806 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);  in rtl8192f_phy_lc_calibrate()
866 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {  in rtl8192fu_iqk_path_a()
872 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_iqk_path_a()
873 	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);  in rtl8192fu_iqk_path_a()
874 	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);  in rtl8192fu_iqk_path_a()
947 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXA) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_a()
953 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_rx_iqk_path_a()
954 	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);  in rtl8192fu_rx_iqk_path_a()
955 	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);  in rtl8192fu_rx_iqk_path_a()
1016 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXA) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_a()
1022 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_rx_iqk_path_a()
1023 	reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);  in rtl8192fu_rx_iqk_path_a()
1091 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {  in rtl8192fu_iqk_path_b()
1097 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_iqk_path_b()
1098 	reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);  in rtl8192fu_iqk_path_b()
1099 	reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);  in rtl8192fu_iqk_path_b()
1177 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_TXB) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_b()
1183 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_rx_iqk_path_b()
1184 	reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);  in rtl8192fu_rx_iqk_path_b()
1185 	reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);  in rtl8192fu_rx_iqk_path_b()
1244 	while (rtl8xxxu_read32(priv, REG_IQK_RPT_RXB) == 0 && ktime < 21) {  in rtl8192fu_rx_iqk_path_b()
1249 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_rx_iqk_path_b()
1250 	reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);  in rtl8192fu_rx_iqk_path_b()
1251 	reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);  in rtl8192fu_rx_iqk_path_b()
1301 	rx_initial_gain_a = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);  in rtl8192fu_phy_iqcalibrate()
1302 	rx_initial_gain_b = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);  in rtl8192fu_phy_iqcalibrate()
1354 			val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);  in rtl8192fu_phy_iqcalibrate()
1357 			val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);  in rtl8192fu_phy_iqcalibrate()
1370 			val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);  in rtl8192fu_phy_iqcalibrate()
1373 			val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8192fu_phy_iqcalibrate()
1390 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);  in rtl8192fu_phy_iqcalibrate()
1393 				val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);  in rtl8192fu_phy_iqcalibrate()
1406 				val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);  in rtl8192fu_phy_iqcalibrate()
1409 				val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);  in rtl8192fu_phy_iqcalibrate()
1473 	rfe_path_select = rtl8xxxu_read32(priv, REG_RFE_PATH_SELECT);  in rtl8192fu_phy_iq_calibrate()
1573 		val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);  in rtl8192fu_phy_iq_calibrate()
1640 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8192fu_emu_to_active()
1653 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8192fu_emu_to_active()
1677 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8192fu_emu_to_active()
1762 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8192fu_active_to_emu()
1814 		val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);  in rtl8192fu_active_to_lps()
1921 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);  in rtl8192f_enable_rf()
1934 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);  in rtl8192f_disable_rf()
1964 	xtal1 = rtl8xxxu_read32(priv, REG_AFE_PLL_CTRL);  in rtl8192f_set_crystal_cap()
1965 	xtal0 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);  in rtl8192f_set_crystal_cap()