413 	sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);  in rtl8188eu_identify_chip()
448 	rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);  in rtl8188eu_config_channel()
457 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);  in rtl8188eu_config_channel()
461 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);  in rtl8188eu_config_channel()
484 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);  in rtl8188eu_config_channel()
488 		val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);  in rtl8188eu_config_channel()
496 		val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);  in rtl8188eu_config_channel()
502 		val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);  in rtl8188eu_config_channel()
510 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);  in rtl8188eu_config_channel()
648 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8188eu_iqk_path_a()
649 	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);  in rtl8188eu_iqk_path_a()
650 	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);  in rtl8188eu_iqk_path_a()
666 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
677 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
702 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8188eu_rx_iqk_path_a()
703 	reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);  in rtl8188eu_rx_iqk_path_a()
704 	reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);  in rtl8188eu_rx_iqk_path_a()
718 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
728 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_rx_iqk_path_a()
751 	reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);  in rtl8188eu_rx_iqk_path_a()
752 	reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);  in rtl8188eu_rx_iqk_path_a()
811 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);  in rtl8188eu_phy_iqcalibrate()
824 	val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);  in rtl8188eu_phy_iqcalibrate()
833 		val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);  in rtl8188eu_phy_iqcalibrate()
839 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);  in rtl8188eu_phy_iqcalibrate()
842 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);  in rtl8188eu_phy_iqcalibrate()
850 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_phy_iqcalibrate()
859 			val32 = rtl8xxxu_read32(priv,  in rtl8188eu_phy_iqcalibrate()
862 			val32 = rtl8xxxu_read32(priv,  in rtl8188eu_phy_iqcalibrate()
875 			val32 = rtl8xxxu_read32(priv,  in rtl8188eu_phy_iqcalibrate()
878 			val32 = rtl8xxxu_read32(priv,  in rtl8188eu_phy_iqcalibrate()
890 	val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);  in rtl8188eu_phy_iqcalibrate()
1027 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8188e_emu_to_active()
1045 	val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);  in rtl8188e_emu_to_active()
1060 	val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8188e_emu_to_active()
1065 		val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);  in rtl8188e_emu_to_active()
1110 	val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);  in rtl8188eu_emu_to_disabled()
1147 		val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);  in rtl8188eu_active_to_lps()
1284 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);  in rtl8188e_enable_rf()
1296 	val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);  in rtl8188e_disable_rf()