Lines Matching refs:rt2x00_set_field32
94 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value); in rt2800_bbp_write()
95 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_write()
96 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_write()
97 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0); in rt2800_bbp_write()
98 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_write()
123 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word); in rt2800_bbp_read()
124 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1); in rt2800_bbp_read()
125 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1); in rt2800_bbp_read()
126 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1); in rt2800_bbp_read()
155 rt2x00_set_field32(®, RF_CSR_CFG_DATA_MT7620, value); in rt2800_rfcsr_write()
156 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_write()
158 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 1); in rt2800_rfcsr_write()
159 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_write()
168 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value); in rt2800_rfcsr_write()
169 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_write()
170 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1); in rt2800_rfcsr_write()
171 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_write()
241 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM_MT7620, in rt2800_rfcsr_read()
243 rt2x00_set_field32(®, RF_CSR_CFG_WRITE_MT7620, 0); in rt2800_rfcsr_read()
244 rt2x00_set_field32(®, RF_CSR_CFG_BUSY_MT7620, 1); in rt2800_rfcsr_read()
257 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word); in rt2800_rfcsr_read()
258 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0); in rt2800_rfcsr_read()
259 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1); in rt2800_rfcsr_read()
294 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value); in rt2800_rf_write()
295 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0); in rt2800_rf_write()
296 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0); in rt2800_rf_write()
297 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1); in rt2800_rf_write()
461 rt2x00_set_field32(®, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff); in rt2800_enable_wlan_rt3290()
462 rt2x00_set_field32(®, FRC_WL_ANT_SET, 1); in rt2800_enable_wlan_rt3290()
463 rt2x00_set_field32(®, WLAN_CLK_EN, 0); in rt2800_enable_wlan_rt3290()
464 rt2x00_set_field32(®, WLAN_EN, 1); in rt2800_enable_wlan_rt3290()
499 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 0); in rt2800_enable_wlan_rt3290()
500 rt2x00_set_field32(®, WLAN_CLK_EN, 1); in rt2800_enable_wlan_rt3290()
501 rt2x00_set_field32(®, WLAN_RESET, 1); in rt2800_enable_wlan_rt3290()
504 rt2x00_set_field32(®, WLAN_RESET, 0); in rt2800_enable_wlan_rt3290()
532 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1); in rt2800_mcu_request()
533 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token); in rt2800_mcu_request()
534 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0); in rt2800_mcu_request()
535 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1); in rt2800_mcu_request()
539 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command); in rt2800_mcu_request()
592 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_disable_wpdma()
593 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_disable_wpdma()
594 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_disable_wpdma()
595 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_disable_wpdma()
596 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_disable_wpdma()
743 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); in rt2800_load_firmware()
744 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); in rt2800_load_firmware()
804 rt2x00_set_field32(&word, TXWI_W0_FRAG, in rt2800_write_tx_data()
806 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, in rt2800_write_tx_data()
808 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0); in rt2800_write_tx_data()
809 rt2x00_set_field32(&word, TXWI_W0_TS, in rt2800_write_tx_data()
811 rt2x00_set_field32(&word, TXWI_W0_AMPDU, in rt2800_write_tx_data()
813 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, in rt2800_write_tx_data()
815 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop); in rt2800_write_tx_data()
816 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs); in rt2800_write_tx_data()
817 rt2x00_set_field32(&word, TXWI_W0_BW, in rt2800_write_tx_data()
819 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI, in rt2800_write_tx_data()
821 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc); in rt2800_write_tx_data()
822 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode); in rt2800_write_tx_data()
826 rt2x00_set_field32(&word, TXWI_W1_ACK, in rt2800_write_tx_data()
828 rt2x00_set_field32(&word, TXWI_W1_NSEQ, in rt2800_write_tx_data()
830 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size); in rt2800_write_tx_data()
831 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID, in rt2800_write_tx_data()
834 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, in rt2800_write_tx_data()
836 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid); in rt2800_write_tx_data()
837 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1); in rt2800_write_tx_data()
1348 rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM, in rt2800_update_beacons_setup()
1368 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_write_beacon()
1458 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_clear_beacon()
1560 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity); in rt2800_brightness_set()
1564 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, in rt2800_brightness_set()
1567 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, in rt2800_brightness_set()
1570 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, in rt2800_brightness_set()
1647 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7)); in rt2800_config_wcid_attr_bssidx()
1648 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT, in rt2800_config_wcid_attr_bssidx()
1665 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, in rt2800_config_wcid_attr_cipher()
1672 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, in rt2800_config_wcid_attr_cipher()
1674 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, in rt2800_config_wcid_attr_cipher()
1676 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher); in rt2800_config_wcid_attr_cipher()
1681 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0); in rt2800_config_wcid_attr_cipher()
1682 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0); in rt2800_config_wcid_attr_cipher()
1683 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0); in rt2800_config_wcid_attr_cipher()
1684 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0); in rt2800_config_wcid_attr_cipher()
1740 rt2x00_set_field32(®, field, in rt2800_config_shared_key()
1806 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, max_psdu); in rt2800_set_max_psdu_len()
1920 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR, in rt2800_config_filter()
1922 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR, in rt2800_config_filter()
1924 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME, in rt2800_config_filter()
1926 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0); in rt2800_config_filter()
1927 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1); in rt2800_config_filter()
1928 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST, in rt2800_config_filter()
1930 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0); in rt2800_config_filter()
1931 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1); in rt2800_config_filter()
1932 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK, in rt2800_config_filter()
1934 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END, in rt2800_config_filter()
1936 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK, in rt2800_config_filter()
1938 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS, in rt2800_config_filter()
1940 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS, in rt2800_config_filter()
1942 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL, in rt2800_config_filter()
1944 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA, 0); in rt2800_config_filter()
1945 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR, in rt2800_config_filter()
1947 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL, in rt2800_config_filter()
1964 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync); in rt2800_config_intf()
1972 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0); in rt2800_config_intf()
1973 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1); in rt2800_config_intf()
1974 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1975 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0); in rt2800_config_intf()
1979 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4); in rt2800_config_intf()
1980 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2); in rt2800_config_intf()
1981 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32); in rt2800_config_intf()
1982 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16); in rt2800_config_intf()
2000 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff); in rt2800_config_intf()
2011 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3); in rt2800_config_intf()
2012 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 0); in rt2800_config_intf()
2098 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate); in rt2800_config_ht_opmode()
2099 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode); in rt2800_config_ht_opmode()
2103 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate); in rt2800_config_ht_opmode()
2104 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode); in rt2800_config_ht_opmode()
2108 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate); in rt2800_config_ht_opmode()
2109 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode); in rt2800_config_ht_opmode()
2113 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate); in rt2800_config_ht_opmode()
2114 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode); in rt2800_config_ht_opmode()
2125 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, in rt2800_config_erp()
2132 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, in rt2800_config_erp()
2145 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, in rt2800_config_erp()
2150 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs); in rt2800_config_erp()
2156 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, in rt2800_config_erp()
2216 rt2x00_set_field32(®, GPIO_SWITCH_0, 1); in rt2800_config_3572bt_ant()
2217 rt2x00_set_field32(®, GPIO_SWITCH_1, 1); in rt2800_config_3572bt_ant()
2219 rt2x00_set_field32(®, GPIO_SWITCH_0, 0); in rt2800_config_3572bt_ant()
2220 rt2x00_set_field32(®, GPIO_SWITCH_1, 0); in rt2800_config_3572bt_ant()
2232 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); in rt2800_config_3572bt_ant()
2233 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); in rt2800_config_3572bt_ant()
2251 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin); in rt2800_set_ant_diversity()
2258 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_set_ant_diversity()
2259 rt2x00_set_field32(®, GPIO_CTRL_VAL3, gpio_bit3); in rt2800_set_ant_diversity()
2428 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt2800_config_channel_rf2xxx()
2431 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1); in rt2800_config_channel_rf2xxx()
2434 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1); in rt2800_config_channel_rf2xxx()
2435 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2437 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1); in rt2800_config_channel_rf2xxx()
2446 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2452 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1); in rt2800_config_channel_rf2xxx()
2454 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST, in rt2800_config_channel_rf2xxx()
2460 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2); in rt2800_config_channel_rf2xxx()
2462 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1); in rt2800_config_channel_rf2xxx()
2463 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2); in rt2800_config_channel_rf2xxx()
2466 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf)); in rt2800_config_channel_rf2xxx()
2726 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel_rf3052()
2728 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel_rf3052()
2730 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 0); in rt2800_config_channel_rf3052()
3440 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, in rt2800_config_channel_rf55xx()
3909 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, tx_power[0]); in rt2800_config_alc_rt6352()
3910 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, tx_power[1]); in rt2800_config_alc_rt6352()
3911 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_0, 0x2f); in rt2800_config_alc_rt6352()
3912 rt2x00_set_field32(®, TX_ALC_CFG_0_LIMIT_1, 0x2f); in rt2800_config_alc_rt6352()
3919 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_0, target_power); in rt2800_config_alc_rt6352()
3920 rt2x00_set_field32(®, TX_ALC_CFG_0_CH_INIT_1, target_power); in rt2800_config_alc_rt6352()
3925 rt2x00_set_field32(®, TX_ALC_CFG_1_TX_TEMP_COMP, 0); in rt2800_config_alc_rt6352()
4297 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf)); in rt2800_config_channel()
4298 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14); in rt2800_config_channel()
4299 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); in rt2800_config_channel()
4307 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); in rt2800_config_channel()
4315 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, in rt2800_config_channel()
4317 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, in rt2800_config_channel()
4322 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, in rt2800_config_channel()
4324 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, in rt2800_config_channel()
4329 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, in rt2800_config_channel()
4332 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_config_channel()
4334 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, in rt2800_config_channel()
4342 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1); in rt2800_config_channel()
4343 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1); in rt2800_config_channel()
4347 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1); in rt2800_config_channel()
4348 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1); in rt2800_config_channel()
4352 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1); in rt2800_config_channel()
4353 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); in rt2800_config_channel()
4357 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); in rt2800_config_channel()
4358 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); in rt2800_config_channel()
4381 rt2x00_set_field32(®, GPIO_CTRL_DIR8, 0); in rt2800_config_channel()
4383 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 1); in rt2800_config_channel()
4385 rt2x00_set_field32(®, GPIO_CTRL_VAL8, 0); in rt2800_config_channel()
4393 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4394 rt2x00_set_field32(®, GPIO_CTRL_DIR7, 0); in rt2800_config_channel()
4396 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4397 rt2x00_set_field32(®, GPIO_CTRL_VAL7, 1); in rt2800_config_channel()
4400 rt2x00_set_field32(®, GPIO_CTRL_DIR4, 0); in rt2800_config_channel()
4401 rt2x00_set_field32(®, GPIO_CTRL_VAL4, 1); in rt2800_config_channel()
4824 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4826 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4828 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4835 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4837 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4839 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4846 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4848 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4850 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4857 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4859 rt2x00_set_field32(®s[TX_PWR_CFG_0_IDX], in rt2800_config_txpower_rt3593()
4861 rt2x00_set_field32(®s[TX_PWR_CFG_0_EXT_IDX], in rt2800_config_txpower_rt3593()
4872 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4874 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4876 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4883 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4885 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4887 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4894 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4896 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4898 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4909 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4911 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4913 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4920 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4922 rt2x00_set_field32(®s[TX_PWR_CFG_1_IDX], in rt2800_config_txpower_rt3593()
4924 rt2x00_set_field32(®s[TX_PWR_CFG_1_EXT_IDX], in rt2800_config_txpower_rt3593()
4931 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4933 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4935 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4942 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4944 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4946 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4957 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4959 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4961 rt2x00_set_field32(®s[TX_PWR_CFG_7_IDX], in rt2800_config_txpower_rt3593()
4968 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4970 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4972 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4979 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4981 rt2x00_set_field32(®s[TX_PWR_CFG_2_IDX], in rt2800_config_txpower_rt3593()
4983 rt2x00_set_field32(®s[TX_PWR_CFG_2_EXT_IDX], in rt2800_config_txpower_rt3593()
4990 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4992 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
4994 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5005 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5007 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5009 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5016 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5018 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5020 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5027 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5029 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5031 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5038 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5040 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5042 rt2x00_set_field32(®s[TX_PWR_CFG_5_IDX], in rt2800_config_txpower_rt3593()
5053 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5055 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5057 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5064 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5066 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5068 rt2x00_set_field32(®s[TX_PWR_CFG_6_IDX], in rt2800_config_txpower_rt3593()
5075 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5077 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5079 rt2x00_set_field32(®s[TX_PWR_CFG_8_IDX], in rt2800_config_txpower_rt3593()
5090 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5092 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5094 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5101 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5103 rt2x00_set_field32(®s[TX_PWR_CFG_3_IDX], in rt2800_config_txpower_rt3593()
5105 rt2x00_set_field32(®s[TX_PWR_CFG_3_EXT_IDX], in rt2800_config_txpower_rt3593()
5112 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt3593()
5113 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt3593()
5114 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0, in rt2800_config_txpower_rt3593()
5121 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt3593()
5122 rt2x00_set_field32(®s[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt3593()
5123 rt2x00_set_field32(®s[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2, in rt2800_config_txpower_rt3593()
5134 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5136 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5138 rt2x00_set_field32(®s[TX_PWR_CFG_9_IDX], in rt2800_config_txpower_rt3593()
5272 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t); in rt2800_config_txpower_rt6352()
5277 rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t); in rt2800_config_txpower_rt6352()
5284 rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t); in rt2800_config_txpower_rt6352()
5291 rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t); in rt2800_config_txpower_rt6352()
5399 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower); in rt2800_config_txpower_rt28xx()
5410 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower); in rt2800_config_txpower_rt28xx()
5421 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower); in rt2800_config_txpower_rt28xx()
5432 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower); in rt2800_config_txpower_rt28xx()
5449 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower); in rt2800_config_txpower_rt28xx()
5460 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower); in rt2800_config_txpower_rt28xx()
5471 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower); in rt2800_config_txpower_rt28xx()
5482 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower); in rt2800_config_txpower_rt28xx()
5578 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1); in rt2800_vco_calibration()
5581 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); in rt2800_vco_calibration()
5585 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); in rt2800_vco_calibration()
5591 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1); in rt2800_vco_calibration()
5594 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); in rt2800_vco_calibration()
5598 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1); in rt2800_vco_calibration()
5649 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, in rt2800_config_retry_limit()
5651 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, in rt2800_config_retry_limit()
5668 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5); in rt2800_config_ps()
5669 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, in rt2800_config_ps()
5671 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1); in rt2800_config_ps()
5677 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); in rt2800_config_ps()
5678 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); in rt2800_config_ps()
5679 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0); in rt2800_config_ps()
5863 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600); in rt2800_init_registers()
5864 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0); in rt2800_init_registers()
5865 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0); in rt2800_init_registers()
5866 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0); in rt2800_init_registers()
5867 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0); in rt2800_init_registers()
5868 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); in rt2800_init_registers()
5874 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9); in rt2800_init_registers()
5875 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2); in rt2800_init_registers()
5881 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1); in rt2800_init_registers()
5887 rt2x00_set_field32(®, LDO0_EN, 1); in rt2800_init_registers()
5888 rt2x00_set_field32(®, LDO_BGSEL, 3); in rt2800_init_registers()
5893 rt2x00_set_field32(®, OSC_ROSC_EN, 1); in rt2800_init_registers()
5894 rt2x00_set_field32(®, OSC_CAL_REQ, 1); in rt2800_init_registers()
5895 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27); in rt2800_init_registers()
5899 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e); in rt2800_init_registers()
5903 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00); in rt2800_init_registers()
5904 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17); in rt2800_init_registers()
5905 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93); in rt2800_init_registers()
5906 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f); in rt2800_init_registers()
5910 rt2x00_set_field32(®, PLL_CONTROL, 1); in rt2800_init_registers()
6008 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0); in rt2800_init_registers()
6016 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); in rt2800_init_registers()
6017 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); in rt2800_init_registers()
6018 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); in rt2800_init_registers()
6019 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); in rt2800_init_registers()
6020 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); in rt2800_init_registers()
6021 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); in rt2800_init_registers()
6022 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); in rt2800_init_registers()
6023 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); in rt2800_init_registers()
6027 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); in rt2800_init_registers()
6028 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); in rt2800_init_registers()
6029 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); in rt2800_init_registers()
6033 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); in rt2800_init_registers()
6043 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu); in rt2800_init_registers()
6044 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); in rt2800_init_registers()
6045 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); in rt2800_init_registers()
6049 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); in rt2800_init_registers()
6050 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); in rt2800_init_registers()
6051 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); in rt2800_init_registers()
6052 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); in rt2800_init_registers()
6053 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); in rt2800_init_registers()
6054 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); in rt2800_init_registers()
6055 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); in rt2800_init_registers()
6061 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 2); in rt2800_init_registers()
6062 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 2); in rt2800_init_registers()
6063 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); in rt2800_init_registers()
6064 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); in rt2800_init_registers()
6065 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); in rt2800_init_registers()
6066 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); in rt2800_init_registers()
6070 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); in rt2800_init_registers()
6071 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); in rt2800_init_registers()
6072 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); in rt2800_init_registers()
6073 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); in rt2800_init_registers()
6074 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); in rt2800_init_registers()
6075 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); in rt2800_init_registers()
6076 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); in rt2800_init_registers()
6080 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
6081 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
6082 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6083 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
6084 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6085 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6086 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6087 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6088 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6089 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
6093 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); in rt2800_init_registers()
6094 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); in rt2800_init_registers()
6095 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6096 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); in rt2800_init_registers()
6097 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6098 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6099 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6100 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6101 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6102 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); in rt2800_init_registers()
6106 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
6107 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6108 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6109 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6110 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6111 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6112 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6113 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6114 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6115 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6119 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
6120 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6121 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6122 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6123 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6124 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6125 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
6126 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6127 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
6128 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6132 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); in rt2800_init_registers()
6133 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6134 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6135 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6136 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6137 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6138 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); in rt2800_init_registers()
6139 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6140 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); in rt2800_init_registers()
6141 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6145 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); in rt2800_init_registers()
6146 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); in rt2800_init_registers()
6147 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); in rt2800_init_registers()
6148 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); in rt2800_init_registers()
6149 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); in rt2800_init_registers()
6150 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); in rt2800_init_registers()
6151 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); in rt2800_init_registers()
6152 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); in rt2800_init_registers()
6153 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); in rt2800_init_registers()
6154 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); in rt2800_init_registers()
6161 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); in rt2800_init_registers()
6162 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); in rt2800_init_registers()
6163 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); in rt2800_init_registers()
6164 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); in rt2800_init_registers()
6165 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); in rt2800_init_registers()
6166 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); in rt2800_init_registers()
6167 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); in rt2800_init_registers()
6168 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); in rt2800_init_registers()
6169 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); in rt2800_init_registers()
6178 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); in rt2800_init_registers()
6179 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); in rt2800_init_registers()
6180 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); in rt2800_init_registers()
6181 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); in rt2800_init_registers()
6182 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); in rt2800_init_registers()
6183 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); in rt2800_init_registers()
6184 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); in rt2800_init_registers()
6185 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); in rt2800_init_registers()
6186 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); in rt2800_init_registers()
6187 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); in rt2800_init_registers()
6199 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7); in rt2800_init_registers()
6200 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, in rt2800_init_registers()
6202 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 1); in rt2800_init_registers()
6215 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16); in rt2800_init_registers()
6216 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16); in rt2800_init_registers()
6217 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4); in rt2800_init_registers()
6218 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314); in rt2800_init_registers()
6219 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1); in rt2800_init_registers()
6252 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30); in rt2800_init_registers()
6256 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125); in rt2800_init_registers()
6277 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, rate); in rt2800_init_registers()
6282 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0); in rt2800_init_registers()
6283 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0); in rt2800_init_registers()
6284 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1); in rt2800_init_registers()
6285 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2); in rt2800_init_registers()
6286 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3); in rt2800_init_registers()
6287 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4); in rt2800_init_registers()
6288 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5); in rt2800_init_registers()
6289 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6); in rt2800_init_registers()
6293 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8); in rt2800_init_registers()
6294 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8); in rt2800_init_registers()
6295 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9); in rt2800_init_registers()
6296 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10); in rt2800_init_registers()
6297 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11); in rt2800_init_registers()
6298 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12); in rt2800_init_registers()
6299 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13); in rt2800_init_registers()
6300 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14); in rt2800_init_registers()
6304 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8); in rt2800_init_registers()
6305 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8); in rt2800_init_registers()
6306 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9); in rt2800_init_registers()
6307 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10); in rt2800_init_registers()
6308 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11); in rt2800_init_registers()
6309 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12); in rt2800_init_registers()
6310 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13); in rt2800_init_registers()
6311 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14); in rt2800_init_registers()
6315 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0); in rt2800_init_registers()
6316 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0); in rt2800_init_registers()
6317 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1); in rt2800_init_registers()
6318 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2); in rt2800_init_registers()
6325 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0); in rt2800_init_registers()
6326 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0); in rt2800_init_registers()
6345 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4); in rt2800_init_registers()
6352 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1); in rt2800_init_registers()
6353 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1); in rt2800_init_registers()
6354 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1); in rt2800_init_registers()
6355 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1); in rt2800_init_registers()
6356 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1); in rt2800_init_registers()
6923 rt2x00_set_field32(®, GPIO_CTRL_DIR3, 0); in rt2800_init_bbp_53xx()
6924 rt2x00_set_field32(®, GPIO_CTRL_DIR6, 0); in rt2800_init_bbp_53xx()
6925 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 0); in rt2800_init_bbp_53xx()
6926 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 0); in rt2800_init_bbp_53xx()
6928 rt2x00_set_field32(®, GPIO_CTRL_VAL3, 1); in rt2800_init_bbp_53xx()
6930 rt2x00_set_field32(®, GPIO_CTRL_VAL6, 1); in rt2800_init_bbp_53xx()
7299 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); in rt2800_led_open_drain_enable()
7632 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7633 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7644 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_30xx()
7649 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_30xx()
7651 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_30xx()
7656 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_30xx()
7871 rt2x00_set_field32(®, GPIO_SWITCH_5, 0); in rt2800_init_rfcsr_3390()
7927 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3572()
7928 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7932 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3572()
7933 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3572()
7996 rt2x00_set_field32(®, GPIO_SWITCH_4, 0); in rt2800_init_rfcsr_3593()
7997 rt2x00_set_field32(®, GPIO_SWITCH_7, 0); in rt2800_init_rfcsr_3593()
8047 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); in rt2800_init_rfcsr_3593()
8048 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); in rt2800_init_rfcsr_3593()
8052 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0); in rt2800_init_rfcsr_3593()
10717 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
10718 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_enable_radio()
10724 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1); in rt2800_enable_radio()
10725 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1); in rt2800_enable_radio()
10726 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1); in rt2800_enable_radio()
10730 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1); in rt2800_enable_radio()
10731 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1); in rt2800_enable_radio()
10763 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0); in rt2800_disable_radio()
10764 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0); in rt2800_disable_radio()
10809 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i); in rt2800_efuse_read()
10810 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0); in rt2800_efuse_read()
10811 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1); in rt2800_efuse_read()
11902 rt2x00_set_field32(®, GPIO_CTRL_DIR2, 1); in rt2800_probe_hw()
11984 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value); in rt2800_set_rts_threshold()
11988 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11992 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
11996 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
12000 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
12004 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
12008 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled); in rt2800_set_rts_threshold()
12052 rt2x00_set_field32(®, field, queue->txop); in rt2800_conf_tx()
12060 rt2x00_set_field32(®, field, queue->aifs); in rt2800_conf_tx()
12064 rt2x00_set_field32(®, field, queue->cw_min); in rt2800_conf_tx()
12068 rt2x00_set_field32(®, field, queue->cw_max); in rt2800_conf_tx()
12075 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop); in rt2800_conf_tx()
12076 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs); in rt2800_conf_tx()
12077 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min); in rt2800_conf_tx()
12078 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max); in rt2800_conf_tx()