Lines Matching full:31
41 #define MT_TX_FREE_PAIR BIT(31)
45 #define MT_TXD0_Q_IDX GENMASK(31, 25)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
62 #define MT_TXD2_FIX_RATE BIT(31)
78 #define MT_TXD3_SN_VALID BIT(31)
92 #define MT_TXD4_PN_LOW GENMASK(31, 0)
94 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
102 #define MT_TXD6_TX_IBF BIT(31)
114 #define MT_TXD7_TXD_LEN GENMASK(31, 30)
136 #define MT_TXS0_FIXED_RATE BIT(31)
155 #define MT_TXS1_SEQNO GENMASK(31, 20)
160 #define MT_TXS2_BF_STATUS GENMASK(31, 30)
166 #define MT_TXS3_PID GENMASK(31, 24)
169 #define MT_TXS4_TIMESTAMP GENMASK(31, 0)
173 #define MT_TXS5_MPDU_TX_CNT GENMASK(31, 23)
175 #define MT_TXS6_MPDU_FAIL_CNT GENMASK(31, 23)
177 #define MT_TXS7_MPDU_RETRY_CNT GENMASK(31, 23)
182 #define MT_RXD0_PKT_TYPE GENMASK(31, 27)
205 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
225 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
239 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
261 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
265 #define MT_RXD6_TA_LO GENMASK(31, 16)
267 #define MT_RXD7_TA_HI GENMASK(31, 0)
270 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
272 #define MT_RXD9_HT_CONTROL GENMASK(31, 0)
281 #define MT_PRXV_HE_RU_ALLOC_L GENMASK(31, 28)
291 #define MT_PRXV_RCPI3 GENMASK(31, 24)
306 #define MT_CRXV_HE_UPLINK BIT(31)
311 #define MT_CRXV_HE_RU3 GENMASK(31, 24)
326 #define MT_CRXV_FOE_LO GENMASK(31, 19)