Lines Matching +full:loop +full:- +full:powered
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2005-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
14 * low power states due to driver-invoked device resets
15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
21 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
30 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
37 #define CSR_FUNC_SCRATCH (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
45 * 31-16: Reserved
46 * 15-4: Type of device: see CSR_HW_REV_TYPE_xxx definitions
47 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
48 * 1-0: "Dash" (-) value, as in A-1, etc.
57 * 11:8: Step (A - 0x0, B - 0x1, etc)
64 * EEPROM and OTP (one-time-programmable) memory reads
78 * UCODE-DRIVER GP (general purpose) mailbox registers.
114 /* Doorbell - since Bz
123 /* Analog phase-lock-loop configuration */
138 * 3-2: 0 = A, 1 = B, 2 = C, 3 = D step
139 * 1-0: "Dash" (-) value, as in C-1, etc.
147 * Scratch register initial configuration - this is set on init, and read
239 * Indicates state of (platform's) hardware RF-Kill switch
240 * 26-24: POWER_SAVE_TYPE
241 * Indicates current power-saving mode:
242 * 000 -- No power saving
243 * 001 -- MAC power-down
244 * 010 -- PHY (radio) power-down
245 * 011 -- Error
247 * 9-6: SYS_CONFIG
251 * Indicates MAC is entering a power-saving sleep power-down.
252 * Not a good time to access device-internal resources.
255 * access to device-internal resources. Host must wait for
256 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
262 * Indicates MAC (ucode processor, etc.) is powered up and can run.
266 * init or post-power-down restore of internal SRAM memory.
269 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
374 /* One-time-programmable memory general purpose reg */
375 #define CSR_OTP_GP_REG_DEVICE_SELECT (0x00010000) /* 0 - EEPROM, 1 - OTP */
376 #define CSR_OTP_GP_REG_OTP_ACCESS_MODE (0x00020000) /* 0 - absolute, 1 - relative */
392 * UCODE-DRIVER GP (general purpose) mailbox register 1
403 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
411 * uCode sets this when preparing a power-saving power-down.
412 * uCode resets this when power-up is complete and SRAM is sane.
416 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
459 * arbiter without need for the MAC HW to be powered up. This is possible due to
464 * need not be powered up so no "grab inc access" is required.
484 * HBUS (Host-side Bus)
488 * may be powered-down.
492 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
505 * data registers auto-increment the address by one dword.
507 * 0-31: memory address within device
523 * 0-15: register address (offset) within device
524 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
535 * Per-Tx-queue write pointer (index, really!)
538 * 0-7: queue write index
539 * 11-8: queue selector
552 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
573 /* Those are the masks INSIDE the flags bit-field: */
640 #define CSR_ADDR_BASE(trans) ((trans)->cfg->mac_addr_from_csr)