Lines Matching refs:ipw_write32
361 #define ipw_write32(ipw, ofs, val) do { \ macro
548 ipw_write32(priv, reg, ipw_read32(priv, reg) | mask); in ipw_set_bit()
554 ipw_write32(priv, reg, ipw_read32(priv, reg) & ~mask); in ipw_clear_bit()
562 ipw_write32(priv, IPW_INTA_MASK_R, IPW_INTA_MASK_ALL); in __ipw_enable_interrupts()
570 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in __ipw_disable_interrupts()
2690 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0); in ipw_eeprom_init_sram()
2695 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 1); in ipw_eeprom_init_sram()
3044 ipw_write32(priv, addr, 0); in ipw_load_ucode()
3249 ipw_write32(priv, IPW_RESET_REG, IPW_RESET_REG_STOP_MASTER); in ipw_stop_nic()
3291 ipw_write32(priv, IPW_READ_INT_REGISTER, in ipw_init_nic()
3487 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in ipw_load()
3491 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3524 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE); in ipw_load()
3546 ipw_write32(priv, IPW_EEPROM_LOAD_DISABLE, 0); in ipw_load()
3555 ipw_write32(priv, IPW_INTA_MASK_R, ~IPW_INTA_MASK_ALL); in ipw_load()
3557 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3584 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_BIT_FW_INITIALIZATION_DONE); in ipw_load()
3598 ipw_write32(priv, IPW_RX_READ_INDEX, priv->rxq->read); in ipw_load()
3601 ipw_write32(priv, IPW_INTA_RW, IPW_INTA_MASK_ALL); in ipw_load()
3712 ipw_write32(priv, base, q->dma_addr); in ipw_queue_init()
3713 ipw_write32(priv, size, count); in ipw_queue_init()
3714 ipw_write32(priv, read, 0); in ipw_queue_init()
3715 ipw_write32(priv, write, 0); in ipw_queue_init()
5013 ipw_write32(priv, q->reg_w, q->first_empty); in ipw_queue_tx_hcmd()
5107 ipw_write32(priv, IPW_RFDS_TABLE_LOWER + rxq->write * RFD_SIZE, in ipw_rx_queue_restock()
5122 ipw_write32(priv, IPW_RX_WRITE_INDEX, rxq->write); in ipw_rx_queue_restock()
10220 ipw_write32(priv, q->reg_w, q->first_empty); in ipw_tx_skb()
10480 ipw_write32(priv, IPW_INTA_RW, inta); in ipw_isr()