Lines Matching +full:0 +full:x0300
20 /* bit 0~7 channel number
21 * for 80+80 channels: bit 0~3 low channel id, bit 4~7 high channel id
23 #define BRCMU_CHSPEC_CH_MASK 0x00ff
24 #define BRCMU_CHSPEC_CH_SHIFT 0
25 #define BRCMU_CHSPEC_CHL_MASK 0x000f
26 #define BRCMU_CHSPEC_CHL_SHIFT 0
27 #define BRCMU_CHSPEC_CHH_MASK 0x00f0
36 #define BRCMU_CHSPEC_D11N_SB_MASK 0x0300
38 #define BRCMU_CHSPEC_D11N_SB_L 0x0100 /* control lower */
39 #define BRCMU_CHSPEC_D11N_SB_U 0x0200 /* control upper */
40 #define BRCMU_CHSPEC_D11N_SB_N 0x0300 /* none */
41 #define BRCMU_CHSPEC_D11N_BW_MASK 0x0c00
43 #define BRCMU_CHSPEC_D11N_BW_10 0x0400
44 #define BRCMU_CHSPEC_D11N_BW_20 0x0800
45 #define BRCMU_CHSPEC_D11N_BW_40 0x0c00
46 #define BRCMU_CHSPEC_D11N_BND_MASK 0x3000
48 #define BRCMU_CHSPEC_D11N_BND_5G 0x1000
49 #define BRCMU_CHSPEC_D11N_BND_2G 0x2000
56 #define BRCMU_CHSPEC_D11AC_SB_MASK 0x0700
58 #define BRCMU_CHSPEC_D11AC_SB_LLL 0x0000
59 #define BRCMU_CHSPEC_D11AC_SB_LLU 0x0100
60 #define BRCMU_CHSPEC_D11AC_SB_LUL 0x0200
61 #define BRCMU_CHSPEC_D11AC_SB_LUU 0x0300
62 #define BRCMU_CHSPEC_D11AC_SB_ULL 0x0400
63 #define BRCMU_CHSPEC_D11AC_SB_ULU 0x0500
64 #define BRCMU_CHSPEC_D11AC_SB_UUL 0x0600
65 #define BRCMU_CHSPEC_D11AC_SB_UUU 0x0700
72 #define BRCMU_CHSPEC_D11AC_BW_MASK 0x3800
74 #define BRCMU_CHSPEC_D11AC_BW_5 0x0000
75 #define BRCMU_CHSPEC_D11AC_BW_10 0x0800
76 #define BRCMU_CHSPEC_D11AC_BW_20 0x1000
77 #define BRCMU_CHSPEC_D11AC_BW_40 0x1800
78 #define BRCMU_CHSPEC_D11AC_BW_80 0x2000
79 #define BRCMU_CHSPEC_D11AC_BW_160 0x2800
80 #define BRCMU_CHSPEC_D11AC_BW_8080 0x3000
81 #define BRCMU_CHSPEC_D11AC_BND_MASK 0xc000
83 #define BRCMU_CHSPEC_D11AC_BND_2G 0x0000
84 #define BRCMU_CHSPEC_D11AC_BND_3G 0x4000
85 #define BRCMU_CHSPEC_D11AC_BND_4G 0x8000
86 #define BRCMU_CHSPEC_D11AC_BND_5G 0xc000
88 #define BRCMU_CHAN_BAND_2G 0