30 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data)  in wcn36xx_ccu_write_register()  argument
36 	writel(data, wcn->ccu_base + addr);  in wcn36xx_ccu_write_register()
39 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)  in wcn36xx_dxe_write_register()  argument
45 	writel(data, wcn->dxe_base + addr);  in wcn36xx_dxe_write_register()
48 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)  in wcn36xx_dxe_read_register()  argument
50 	*data = readl(wcn->dxe_base + addr);  in wcn36xx_dxe_read_register()
101 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn)  in wcn36xx_dxe_alloc_ctl_blks()  argument
105 	wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L;  in wcn36xx_dxe_alloc_ctl_blks()
106 	wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H;  in wcn36xx_dxe_alloc_ctl_blks()
107 	wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L;  in wcn36xx_dxe_alloc_ctl_blks()
108 	wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H;  in wcn36xx_dxe_alloc_ctl_blks()
110 	wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L;  in wcn36xx_dxe_alloc_ctl_blks()
111 	wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H;  in wcn36xx_dxe_alloc_ctl_blks()
112 	wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L;  in wcn36xx_dxe_alloc_ctl_blks()
113 	wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H;  in wcn36xx_dxe_alloc_ctl_blks()
115 	wcn->dxe_tx_l_ch.dxe_wq =  WCN36XX_DXE_WQ_TX_L(wcn);  in wcn36xx_dxe_alloc_ctl_blks()
116 	wcn->dxe_tx_h_ch.dxe_wq =  WCN36XX_DXE_WQ_TX_H(wcn);  in wcn36xx_dxe_alloc_ctl_blks()
118 	wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD;  in wcn36xx_dxe_alloc_ctl_blks()
119 	wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD;  in wcn36xx_dxe_alloc_ctl_blks()
121 	wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB;  in wcn36xx_dxe_alloc_ctl_blks()
122 	wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB;  in wcn36xx_dxe_alloc_ctl_blks()
124 	wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L;  in wcn36xx_dxe_alloc_ctl_blks()
125 	wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H;  in wcn36xx_dxe_alloc_ctl_blks()
127 	wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L;  in wcn36xx_dxe_alloc_ctl_blks()
128 	wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H;  in wcn36xx_dxe_alloc_ctl_blks()
131 	ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch);  in wcn36xx_dxe_alloc_ctl_blks()
134 	ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch);  in wcn36xx_dxe_alloc_ctl_blks()
137 	ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch);  in wcn36xx_dxe_alloc_ctl_blks()
140 	ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch);  in wcn36xx_dxe_alloc_ctl_blks()
145 	ret = qcom_smem_state_update_bits(wcn->tx_enable_state,  in wcn36xx_dxe_alloc_ctl_blks()
156 	wcn36xx_dxe_free_ctl_blks(wcn);  in wcn36xx_dxe_alloc_ctl_blks()
160 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn)  in wcn36xx_dxe_free_ctl_blks()  argument
162 	wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch);  in wcn36xx_dxe_free_ctl_blks()
163 	wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch);  in wcn36xx_dxe_free_ctl_blks()
164 	wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch);  in wcn36xx_dxe_free_ctl_blks()
165 	wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch);  in wcn36xx_dxe_free_ctl_blks()
168 static int wcn36xx_dxe_init_descs(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *wcn_ch)  in wcn36xx_dxe_init_descs()  argument
170 	struct device *dev = wcn->dev;  in wcn36xx_dxe_init_descs()
194 			cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L(wcn);  in wcn36xx_dxe_init_descs()
198 			cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H(wcn);  in wcn36xx_dxe_init_descs()
260 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)  in wcn36xx_dxe_enable_ch_int()  argument
264 	wcn36xx_dxe_read_register(wcn,  in wcn36xx_dxe_enable_ch_int()
270 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_enable_ch_int()
276 static void wcn36xx_dxe_disable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)  in wcn36xx_dxe_disable_ch_int()  argument
280 	wcn36xx_dxe_read_register(wcn,  in wcn36xx_dxe_disable_ch_int()
286 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_disable_ch_int()
316 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,  in wcn36xx_dxe_ch_alloc_skb()  argument
325 		wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl, GFP_KERNEL);  in wcn36xx_dxe_ch_alloc_skb()
332 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,  in wcn36xx_dxe_ch_free_skbs()  argument
344 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status)  in wcn36xx_dxe_tx_ack_ind()  argument
350 	spin_lock_irqsave(&wcn->dxe_lock, flags);  in wcn36xx_dxe_tx_ack_ind()
351 	skb = wcn->tx_ack_skb;  in wcn36xx_dxe_tx_ack_ind()
352 	wcn->tx_ack_skb = NULL;  in wcn36xx_dxe_tx_ack_ind()
353 	del_timer(&wcn->tx_ack_timer);  in wcn36xx_dxe_tx_ack_ind()
354 	spin_unlock_irqrestore(&wcn->dxe_lock, flags);  in wcn36xx_dxe_tx_ack_ind()
370 	ieee80211_tx_status_irqsafe(wcn->hw, skb);  in wcn36xx_dxe_tx_ack_ind()
371 	ieee80211_wake_queues(wcn->hw);  in wcn36xx_dxe_tx_ack_ind()
376 	struct wcn36xx *wcn = from_timer(wcn, t, tx_ack_timer);  in wcn36xx_dxe_tx_timer()  local
384 	spin_lock_irqsave(&wcn->dxe_lock, flags);  in wcn36xx_dxe_tx_timer()
385 	skb = wcn->tx_ack_skb;  in wcn36xx_dxe_tx_timer()
386 	wcn->tx_ack_skb = NULL;  in wcn36xx_dxe_tx_timer()
387 	spin_unlock_irqrestore(&wcn->dxe_lock, flags);  in wcn36xx_dxe_tx_timer()
396 	ieee80211_tx_status_irqsafe(wcn->hw, skb);  in wcn36xx_dxe_tx_timer()
397 	ieee80211_wake_queues(wcn->hw);  in wcn36xx_dxe_tx_timer()
400 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)  in reap_tx_dxes()  argument
419 			dma_unmap_single(wcn->dev, ctl->desc->src_addr_l,  in reap_tx_dxes()
425 					ieee80211_tx_status_irqsafe(wcn->hw, ctl->skb);  in reap_tx_dxes()
428 					spin_lock(&wcn->dxe_lock);  in reap_tx_dxes()
429 					if (WARN_ON(wcn->tx_ack_skb))  in reap_tx_dxes()
430 						ieee80211_free_txskb(wcn->hw, wcn->tx_ack_skb);  in reap_tx_dxes()
431 					wcn->tx_ack_skb = ctl->skb; /* Tracking ref */  in reap_tx_dxes()
432 					mod_timer(&wcn->tx_ack_timer, jiffies + HZ / 10);  in reap_tx_dxes()
433 					spin_unlock(&wcn->dxe_lock);  in reap_tx_dxes()
437 				ieee80211_free_txskb(wcn->hw, ctl->skb);  in reap_tx_dxes()
440 			if (wcn->queues_stopped) {  in reap_tx_dxes()
441 				wcn->queues_stopped = false;  in reap_tx_dxes()
442 				ieee80211_wake_queues(wcn->hw);  in reap_tx_dxes()
456 	struct wcn36xx *wcn = (struct wcn36xx *)dev;  in wcn36xx_irq_tx_complete()  local
459 	wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);  in wcn36xx_irq_tx_complete()
462 		wcn36xx_dxe_read_register(wcn,  in wcn36xx_irq_tx_complete()
466 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
471 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
480 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
486 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
496 			reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);  in wcn36xx_irq_tx_complete()
501 		wcn36xx_dxe_read_register(wcn,  in wcn36xx_irq_tx_complete()
505 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
510 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
519 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
525 			wcn36xx_dxe_write_register(wcn,  in wcn36xx_irq_tx_complete()
535 			reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);  in wcn36xx_irq_tx_complete()
544 	struct wcn36xx *wcn = (struct wcn36xx *)dev;  in wcn36xx_irq_rx_ready()  local
546 	wcn36xx_dxe_rx_frame(wcn);  in wcn36xx_irq_rx_ready()
551 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)  in wcn36xx_dxe_request_irqs()  argument
555 	ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete,  in wcn36xx_dxe_request_irqs()
556 			  IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn);  in wcn36xx_dxe_request_irqs()
562 	ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH,  in wcn36xx_dxe_request_irqs()
563 			  "wcn36xx_rx", wcn);  in wcn36xx_dxe_request_irqs()
569 	enable_irq_wake(wcn->rx_irq);  in wcn36xx_dxe_request_irqs()
574 	free_irq(wcn->tx_irq, wcn);  in wcn36xx_dxe_request_irqs()
580 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,  in wcn36xx_rx_handle_packets()  argument
594 	wcn36xx_dxe_read_register(wcn, status_reg, &int_reason);  in wcn36xx_rx_handle_packets()
595 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR, int_mask);  in wcn36xx_rx_handle_packets()
598 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_rx_handle_packets()
606 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_rx_handle_packets()
611 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_rx_handle_packets()
631 		ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl, GFP_ATOMIC);  in wcn36xx_rx_handle_packets()
636 			dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE,  in wcn36xx_rx_handle_packets()
638 			wcn36xx_rx_skb(wcn, skb);  in wcn36xx_rx_handle_packets()
651 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, en_mask);  in wcn36xx_rx_handle_packets()
660 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn)  in wcn36xx_dxe_rx_frame()  argument
664 	wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);  in wcn36xx_dxe_rx_frame()
668 		wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_l_ch,  in wcn36xx_dxe_rx_frame()
676 		wcn36xx_rx_handle_packets(wcn, &wcn->dxe_rx_h_ch,  in wcn36xx_dxe_rx_frame()
686 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn)  in wcn36xx_dxe_allocate_mem_pools()  argument
694 	wcn->mgmt_mem_pool.chunk_size =	WCN36XX_BD_CHUNK_SIZE +  in wcn36xx_dxe_allocate_mem_pools()
697 	s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H;  in wcn36xx_dxe_allocate_mem_pools()
698 	cpu_addr = dma_alloc_coherent(wcn->dev, s,  in wcn36xx_dxe_allocate_mem_pools()
699 				      &wcn->mgmt_mem_pool.phy_addr,  in wcn36xx_dxe_allocate_mem_pools()
704 	wcn->mgmt_mem_pool.virt_addr = cpu_addr;  in wcn36xx_dxe_allocate_mem_pools()
709 	wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +  in wcn36xx_dxe_allocate_mem_pools()
712 	s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L;  in wcn36xx_dxe_allocate_mem_pools()
713 	cpu_addr = dma_alloc_coherent(wcn->dev, s,  in wcn36xx_dxe_allocate_mem_pools()
714 				      &wcn->data_mem_pool.phy_addr,  in wcn36xx_dxe_allocate_mem_pools()
719 	wcn->data_mem_pool.virt_addr = cpu_addr;  in wcn36xx_dxe_allocate_mem_pools()
724 	wcn36xx_dxe_free_mem_pools(wcn);  in wcn36xx_dxe_allocate_mem_pools()
729 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn)  in wcn36xx_dxe_free_mem_pools()  argument
731 	if (wcn->mgmt_mem_pool.virt_addr)  in wcn36xx_dxe_free_mem_pools()
732 		dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size *  in wcn36xx_dxe_free_mem_pools()
734 				  wcn->mgmt_mem_pool.virt_addr,  in wcn36xx_dxe_free_mem_pools()
735 				  wcn->mgmt_mem_pool.phy_addr);  in wcn36xx_dxe_free_mem_pools()
737 	if (wcn->data_mem_pool.virt_addr) {  in wcn36xx_dxe_free_mem_pools()
738 		dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size *  in wcn36xx_dxe_free_mem_pools()
740 				  wcn->data_mem_pool.virt_addr,  in wcn36xx_dxe_free_mem_pools()
741 				  wcn->data_mem_pool.phy_addr);  in wcn36xx_dxe_free_mem_pools()
745 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,  in wcn36xx_dxe_tx_frame()  argument
757 	ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;  in wcn36xx_dxe_tx_frame()
769 		ieee80211_stop_queues(wcn->hw);  in wcn36xx_dxe_tx_frame()
770 		wcn->queues_stopped = true;  in wcn36xx_dxe_tx_frame()
802 	desc_skb->src_addr_l = dma_map_single(wcn->dev,  in wcn36xx_dxe_tx_frame()
806 	if (dma_mapping_error(wcn->dev, desc_skb->src_addr_l)) {  in wcn36xx_dxe_tx_frame()
807 		dev_err(wcn->dev, "unable to DMA map src_addr_l\n");  in wcn36xx_dxe_tx_frame()
836 		qcom_smem_state_update_bits(wcn->tx_rings_empty_state,  in wcn36xx_dxe_tx_frame()
843 		wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_tx_frame()
881 int wcn36xx_dxe_tx_flush(struct wcn36xx *wcn)  in wcn36xx_dxe_tx_flush()  argument
887 		if (_wcn36xx_dxe_tx_channel_is_empty(&wcn->dxe_tx_l_ch) &&  in wcn36xx_dxe_tx_flush()
888 		    _wcn36xx_dxe_tx_channel_is_empty(&wcn->dxe_tx_h_ch)) {  in wcn36xx_dxe_tx_flush()
900 int wcn36xx_dxe_init(struct wcn36xx *wcn)  in wcn36xx_dxe_init()  argument
905 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);  in wcn36xx_dxe_init()
910 	if (wcn->is_pronto)  in wcn36xx_dxe_init()
911 		wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data);  in wcn36xx_dxe_init()
913 		wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data);  in wcn36xx_dxe_init()
918 	ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_tx_l_ch);  in wcn36xx_dxe_init()
920 		dev_err(wcn->dev, "Error allocating descriptor\n");  in wcn36xx_dxe_init()
923 	wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool);  in wcn36xx_dxe_init()
926 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,  in wcn36xx_dxe_init()
927 		wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr);  in wcn36xx_dxe_init()
930 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
932 		WCN36XX_DXE_WQ_TX_L(wcn));  in wcn36xx_dxe_init()
934 	wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, &reg_data);  in wcn36xx_dxe_init()
939 	ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_tx_h_ch);  in wcn36xx_dxe_init()
941 		dev_err(wcn->dev, "Error allocating descriptor\n");  in wcn36xx_dxe_init()
945 	wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool);  in wcn36xx_dxe_init()
948 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,  in wcn36xx_dxe_init()
949 		wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr);  in wcn36xx_dxe_init()
952 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
954 		WCN36XX_DXE_WQ_TX_H(wcn));  in wcn36xx_dxe_init()
956 	wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, &reg_data);  in wcn36xx_dxe_init()
961 	ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_rx_l_ch);  in wcn36xx_dxe_init()
963 		dev_err(wcn->dev, "Error allocating descriptor\n");  in wcn36xx_dxe_init()
968 	wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch);  in wcn36xx_dxe_init()
971 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,  in wcn36xx_dxe_init()
972 		wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr);  in wcn36xx_dxe_init()
975 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
980 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
982 		wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l);  in wcn36xx_dxe_init()
985 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
992 	ret = wcn36xx_dxe_init_descs(wcn, &wcn->dxe_rx_h_ch);  in wcn36xx_dxe_init()
994 		dev_err(wcn->dev, "Error allocating descriptor\n");  in wcn36xx_dxe_init()
999 	wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch);  in wcn36xx_dxe_init()
1002 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,  in wcn36xx_dxe_init()
1003 		wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr);  in wcn36xx_dxe_init()
1006 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
1011 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
1013 		 wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l);  in wcn36xx_dxe_init()
1016 	wcn36xx_dxe_write_register(wcn,  in wcn36xx_dxe_init()
1020 	ret = wcn36xx_dxe_request_irqs(wcn);  in wcn36xx_dxe_init()
1024 	timer_setup(&wcn->tx_ack_timer, wcn36xx_dxe_tx_timer, 0);  in wcn36xx_dxe_init()
1027 	wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);  in wcn36xx_dxe_init()
1028 	wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);  in wcn36xx_dxe_init()
1029 	wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);  in wcn36xx_dxe_init()
1030 	wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);  in wcn36xx_dxe_init()
1035 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);  in wcn36xx_dxe_init()
1037 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);  in wcn36xx_dxe_init()
1039 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);  in wcn36xx_dxe_init()
1041 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);  in wcn36xx_dxe_init()
1046 void wcn36xx_dxe_deinit(struct wcn36xx *wcn)  in wcn36xx_dxe_deinit()  argument
1051 	wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);  in wcn36xx_dxe_deinit()
1052 	wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);  in wcn36xx_dxe_deinit()
1053 	wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);  in wcn36xx_dxe_deinit()
1054 	wcn36xx_dxe_disable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);  in wcn36xx_dxe_deinit()
1056 	free_irq(wcn->tx_irq, wcn);  in wcn36xx_dxe_deinit()
1057 	free_irq(wcn->rx_irq, wcn);  in wcn36xx_dxe_deinit()
1058 	del_timer(&wcn->tx_ack_timer);  in wcn36xx_dxe_deinit()
1060 	if (wcn->tx_ack_skb) {  in wcn36xx_dxe_deinit()
1061 		ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb);  in wcn36xx_dxe_deinit()
1062 		wcn->tx_ack_skb = NULL;  in wcn36xx_dxe_deinit()
1067 	wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);  in wcn36xx_dxe_deinit()
1069 	wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch);  in wcn36xx_dxe_deinit()
1070 	wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch);  in wcn36xx_dxe_deinit()
1072 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_l_ch);  in wcn36xx_dxe_deinit()
1073 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_tx_h_ch);  in wcn36xx_dxe_deinit()
1074 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_l_ch);  in wcn36xx_dxe_deinit()
1075 	wcn36xx_dxe_deinit_descs(wcn->dev, &wcn->dxe_rx_h_ch);  in wcn36xx_dxe_deinit()