775 struct ath_hw {  struct
776 	struct ath_ops reg_ops;
778 	struct device *dev;
779 	struct ieee80211_hw *hw;
780 	struct ath_common common;
781 	struct ath9k_hw_version hw_version;
782 	struct ath9k_ops_config config;
783 	struct ath9k_hw_capabilities caps;
784 	struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
785 	struct ath9k_channel *curchan;
787 	union {
792 	} eeprom;
793 	const struct eeprom_ops *eep_ops;
795 	bool sw_mgmt_crypto_tx;
796 	bool sw_mgmt_crypto_rx;
797 	bool is_pciexpress;
798 	bool aspm_enabled;
799 	bool is_monitoring;
800 	bool need_an_top2_fixup;
801 	u16 tx_trig_level;
803 	u32 nf_regs[6];
804 	struct ath_nf_limits nf_2g;
805 	struct ath_nf_limits nf_5g;
806 	u16 rfsilent;
807 	u32 rfkill_gpio;
808 	u32 rfkill_polarity;
809 	u32 ah_flags;
810 	s16 nf_override;
812 	bool reset_power_on;
813 	bool htc_reset_init;
815 	enum nl80211_iftype opmode;
816 	enum ath9k_power_mode power_mode;
818 	s8 noise;
819 	struct ath9k_hw_cal_data *caldata;
820 	struct ath9k_pacal_info pacal_info;
821 	struct ar5416Stats stats;
822 	struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
825 	enum ath9k_int imask;
826 	u32 imrs2_reg;
827 	u32 txok_interrupt_mask;
828 	u32 txerr_interrupt_mask;
829 	u32 txdesc_interrupt_mask;
830 	u32 txeol_interrupt_mask;
831 	u32 txurn_interrupt_mask;
832 	atomic_t intr_ref_cnt;
833 	bool chip_fullsleep;
834 	u32 modes_index;
837 	u32 supp_cals;
838 	unsigned long cal_start_time;
839 	struct ath9k_cal_list iq_caldata;
840 	struct ath9k_cal_list adcgain_caldata;
841 	struct ath9k_cal_list adcdc_caldata;
842 	struct ath9k_cal_list *cal_list;
843 	struct ath9k_cal_list *cal_list_last;
844 	struct ath9k_cal_list *cal_list_curr;
879 	struct ath_hw_private_ops private_ops;  argument
881 	struct ath_hw_ops ops;  argument
904 	struct ath_hw_radar_conf radar_conf;  argument
906 	u32 originalGain[22];
907 	int initPDADC;
908 	int PDADCdelta;
909 	int led_pin;
910 	u32 gpio_mask;
911 	u32 gpio_val;
913 	struct ar5416IniArray ini_dfs;
914 	struct ar5416IniArray iniModes;
915 	struct ar5416IniArray iniCommon;
916 	struct ar5416IniArray iniBB_RfGain;
917 	struct ar5416IniArray iniBank6;
918 	struct ar5416IniArray iniAddac;
919 	struct ar5416IniArray iniPcieSerdes;
920 	struct ar5416IniArray iniPcieSerdesLowPower;
921 	struct ar5416IniArray iniModesFastClock;
922 	struct ar5416IniArray iniAdditional;
923 	struct ar5416IniArray iniModesRxGain;
924 	struct ar5416IniArray ini_modes_rx_gain_bounds;
925 	struct ar5416IniArray iniModesTxGain;
926 	struct ar5416IniArray iniCckfirNormal;
927 	struct ar5416IniArray iniCckfirJapan2484;
928 	struct ar5416IniArray iniModes_9271_ANI_reg;
929 	struct ar5416IniArray ini_radio_post_sys2ant;
930 	struct ar5416IniArray ini_modes_rxgain_xlna;
931 	struct ar5416IniArray ini_modes_rxgain_bb_core;
932 	struct ar5416IniArray ini_modes_rxgain_bb_postamble;
934 	struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
935 	struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
936 	struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
937 	struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
939 	u32 intr_gen_timer_trigger;
940 	u32 intr_gen_timer_thresh;
941 	struct ath_gen_timer_table hw_gen_timers;
943 	struct ar9003_txs *ts_ring;
944 	u32 ts_paddr_start;
945 	u32 ts_paddr_end;
946 	u16 ts_tail;
947 	u16 ts_size;
949 	u32 bb_watchdog_last_status;
950 	u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
951 	u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
953 	unsigned int paprd_target_power;
954 	unsigned int paprd_training_power;
955 	unsigned int paprd_ratemask;
956 	unsigned int paprd_ratemask_ht40;
957 	bool paprd_table_write_done;
958 	u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
959 	u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
965 	u32 WARegVal;
968 	u32 ent_mode;
971 	struct ath9k_hw_wow wow;
973 	bool is_clk_25mhz;
974 	int (*get_mac_revision)(void);
975 	int (*external_reset)(void);
976 	bool disable_2ghz;
977 	bool disable_5ghz;
1001 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)  in ath9k_hw_common()  argument