Lines Matching refs:ah
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) in ar9003_hw_set_channel() argument
156 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_channel()
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || in ar9003_hw_set_channel()
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_channel()
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
171 } else if (AR_SREV_9340(ah)) { in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || in ar9003_hw_set_channel()
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) && in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
209 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, in ar9003_hw_spur_mitigate_mrc_cck() argument
245 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_mrc_cck()
252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
253 AR_SREV_9550(ah) || AR_SREV_9561(ah)) { in ar9003_hw_spur_mitigate_mrc_cck()
259 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_mrc_cck()
269 range = AR_SREV_9462(ah) ? 5 : 10; in ar9003_hw_spur_mitigate_mrc_cck()
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || in ar9003_hw_spur_mitigate_mrc_cck()
280 AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_spur_mitigate_mrc_cck()
299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_spur_mitigate_mrc_cck()
301 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
303 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
306 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
309 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah), in ar9003_hw_spur_mitigate_mrc_cck()
319 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, in ar9003_hw_spur_mitigate_mrc_cck()
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) in ar9003_hw_spur_ofdm_clear() argument
328 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
330 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
332 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
334 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm_clear()
336 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
338 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm_clear()
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
342 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm_clear()
353 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm_clear()
357 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
359 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
361 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_clear()
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm_clear()
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm_clear()
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah, in ar9003_hw_spur_ofdm() argument
380 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
382 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
384 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
386 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_spur_ofdm()
388 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
391 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) in ar9003_hw_spur_ofdm()
392 REG_RMW_FIELD(ah, AR_PHY_TIMING11, in ar9003_hw_spur_ofdm()
395 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
397 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
399 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
402 if (!AR_SREV_9340(ah) && in ar9003_hw_spur_ofdm()
403 REG_READ_FIELD(ah, AR_PHY_MODE, in ar9003_hw_spur_ofdm()
405 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
416 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
418 REG_RMW_FIELD(ah, AR_PHY_TIMING4, in ar9003_hw_spur_ofdm()
420 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm()
424 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
426 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm()
428 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm()
430 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah), in ar9003_hw_spur_ofdm()
432 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, in ar9003_hw_spur_ofdm()
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, in ar9003_hw_spur_ofdm_9565() argument
447 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
452 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah), in ar9003_hw_spur_ofdm_9565()
456 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
459 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
461 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, in ar9003_hw_spur_ofdm_9565()
465 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah), in ar9003_hw_spur_ofdm_9565()
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, in ar9003_hw_spur_ofdm_work() argument
481 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
490 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_ofdm_work()
511 ar9003_hw_spur_ofdm(ah, in ar9003_hw_spur_ofdm_work()
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, in ar9003_hw_spur_mitigate_ofdm() argument
526 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); in ar9003_hw_spur_mitigate_ofdm()
534 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, in ar9003_hw_spur_mitigate_ofdm()
544 ar9003_hw_spur_ofdm_clear(ah); in ar9003_hw_spur_mitigate_ofdm()
551 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, in ar9003_hw_spur_mitigate_ofdm()
554 if (AR_SREV_9565(ah) && (i < 4)) { in ar9003_hw_spur_mitigate_ofdm()
560 ar9003_hw_spur_ofdm_9565(ah, freq_offset); in ar9003_hw_spur_mitigate_ofdm()
568 static void ar9003_hw_spur_mitigate(struct ath_hw *ah, in ar9003_hw_spur_mitigate() argument
571 if (!AR_SREV_9565(ah)) in ar9003_hw_spur_mitigate()
572 ar9003_hw_spur_mitigate_mrc_cck(ah, chan); in ar9003_hw_spur_mitigate()
573 ar9003_hw_spur_mitigate_ofdm(ah, chan); in ar9003_hw_spur_mitigate()
576 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, in ar9003_hw_compute_pll_control_soc() argument
593 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, in ar9003_hw_compute_pll_control() argument
610 static void ar9003_hw_set_channel_regs(struct ath_hw *ah, in ar9003_hw_set_channel_regs() argument
617 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); in ar9003_hw_set_channel_regs()
622 if (!AR_SREV_9561(ah)) in ar9003_hw_set_channel_regs()
635 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); in ar9003_hw_set_channel_regs()
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); in ar9003_hw_set_channel_regs()
642 ath9k_hw_set11nmac2040(ah, chan); in ar9003_hw_set_channel_regs()
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
650 static void ar9003_hw_init_bb(struct ath_hw *ah, in ar9003_hw_init_bb() argument
660 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_init_bb()
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); in ar9003_hw_init_bb()
664 ath9k_hw_synth_delay(ah, chan, synthDelay); in ar9003_hw_init_bb()
667 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) in ar9003_hw_set_chain_masks() argument
669 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); in ar9003_hw_set_chain_masks()
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx); in ar9003_hw_set_chain_masks()
685 static void ar9003_hw_override_ini(struct ath_hw *ah) in ar9003_hw_override_ini() argument
694 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
703 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); in ar9003_hw_override_ini()
707 REG_WRITE(ah, AR_PCU_MISC_MODE2, val); in ar9003_hw_override_ini()
709 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_override_ini()
710 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, in ar9003_hw_override_ini()
713 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah), in ar9003_hw_override_ini()
715 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
717 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
721 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) in ar9003_hw_override_ini()
722 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
724 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
726 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || in ar9003_hw_override_ini()
727 AR_SREV_9561(ah)) { in ar9003_hw_override_ini()
728 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
729 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1); in ar9003_hw_override_ini()
730 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
731 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
733 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1); in ar9003_hw_override_ini()
734 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
735 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
741 static void ar9003_hw_prog_ini(struct ath_hw *ah, in ar9003_hw_prog_ini() argument
763 REG_WRITE(ah, reg, val); in ar9003_hw_prog_ini()
769 static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9550_hw_get_modes_txgain_index() argument
794 static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, in ar9561_hw_get_modes_txgain_index() argument
807 static void ar9003_doubler_fix(struct ath_hw *ah) in ar9003_doubler_fix() argument
809 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { in ar9003_doubler_fix()
810 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
813 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
816 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
822 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
824 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
826 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
831 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, in ar9003_doubler_fix()
833 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, in ar9003_doubler_fix()
835 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, in ar9003_doubler_fix()
840 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, in ar9003_doubler_fix()
843 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
846 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
849 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
855 static int ar9003_hw_process_ini(struct ath_hw *ah, in ar9003_hw_process_ini() argument
870 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
871 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
872 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
873 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
874 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_process_ini()
875 ar9003_hw_prog_ini(ah, in ar9003_hw_process_ini()
876 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
880 ar9003_doubler_fix(ah); in ar9003_hw_process_ini()
885 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
887 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_process_ini()
891 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_process_ini()
892 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
894 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
901 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || in ar9003_hw_process_ini()
902 (ar9003_hw_get_rx_gain_idx(ah) == 3)) { in ar9003_hw_process_ini()
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
908 if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) in ar9003_hw_process_ini()
909 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
912 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) in ar9003_hw_process_ini()
913 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
918 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { in ar9003_hw_process_ini()
921 if (AR_SREV_9550(ah)) in ar9003_hw_process_ini()
922 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
924 if (AR_SREV_9561(ah)) in ar9003_hw_process_ini()
926 ar9561_hw_get_modes_txgain_index(ah, chan); in ar9003_hw_process_ini()
931 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
934 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
941 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_process_ini()
942 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
948 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
954 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
956 if (AR_SREV_9531(ah)) in ar9003_hw_process_ini()
957 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, in ar9003_hw_process_ini()
961 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
962 ar9003_hw_override_ini(ah); in ar9003_hw_process_ini()
963 ar9003_hw_set_channel_regs(ah, chan); in ar9003_hw_process_ini()
964 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
965 ath9k_hw_apply_txpower(ah, chan, false); in ar9003_hw_process_ini()
970 static void ar9003_hw_set_rfmode(struct ath_hw *ah, in ar9003_hw_set_rfmode() argument
983 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_set_rfmode()
987 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, in ar9003_hw_set_rfmode()
990 REG_WRITE(ah, AR_PHY_MODE, rfMode); in ar9003_hw_set_rfmode()
993 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) in ar9003_hw_mark_phy_inactive() argument
995 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); in ar9003_hw_mark_phy_inactive()
998 static void ar9003_hw_set_delta_slope(struct ath_hw *ah, in ar9003_hw_set_delta_slope() argument
1018 ath9k_hw_get_channel_centers(ah, chan, ¢ers); in ar9003_hw_set_delta_slope()
1021 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1024 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1026 REG_RMW_FIELD(ah, AR_PHY_TIMING3, in ar9003_hw_set_delta_slope()
1035 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, in ar9003_hw_set_delta_slope()
1039 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1041 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, in ar9003_hw_set_delta_slope()
1045 static bool ar9003_hw_rfbus_req(struct ath_hw *ah) in ar9003_hw_rfbus_req() argument
1047 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); in ar9003_hw_rfbus_req()
1048 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, in ar9003_hw_rfbus_req()
1056 static void ar9003_hw_rfbus_done(struct ath_hw *ah) in ar9003_hw_rfbus_done() argument
1058 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; in ar9003_hw_rfbus_done()
1060 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1062 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1065 static bool ar9003_hw_ani_control(struct ath_hw *ah, in ar9003_hw_ani_control() argument
1068 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control()
1069 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1070 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1078 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1089 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) in ar9003_hw_ani_control()
1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR, in ar9003_hw_ani_control()
1128 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1131 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1140 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, in ar9003_hw_ani_control()
1145 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1148 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1159 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1161 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1187 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, in ar9003_hw_ani_control()
1203 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, in ar9003_hw_ani_control()
1224 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1226 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1251 REG_RMW_FIELD(ah, AR_PHY_TIMING5, in ar9003_hw_ani_control()
1267 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, in ar9003_hw_ani_control()
1288 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1290 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1302 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1305 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1307 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, in ar9003_hw_ani_control()
1315 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1317 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1339 static void ar9003_hw_do_getnf(struct ath_hw *ah, in ar9003_hw_do_getnf() argument
1351 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1352 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1356 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1359 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1367 static void ar9003_hw_set_nf_limits(struct ath_hw *ah) in ar9003_hw_set_nf_limits() argument
1369 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1370 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1371 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1372 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1373 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1374 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1376 if (AR_SREV_9330(ah)) in ar9003_hw_set_nf_limits()
1377 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1379 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { in ar9003_hw_set_nf_limits()
1380 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1381 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1382 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1383 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1392 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) in ar9003_hw_ani_cache_ini_regs() argument
1395 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs()
1396 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1400 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1404 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1405 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1406 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1409 val = REG_READ(ah, AR_PHY_SFCORR); in ar9003_hw_ani_cache_ini_regs()
1414 val = REG_READ(ah, AR_PHY_SFCORR_LOW); in ar9003_hw_ani_cache_ini_regs()
1419 val = REG_READ(ah, AR_PHY_SFCORR_EXT); in ar9003_hw_ani_cache_ini_regs()
1424 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1427 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1430 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1433 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1444 static void ar9003_hw_set_radar_params(struct ath_hw *ah, in ar9003_hw_set_radar_params() argument
1451 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); in ar9003_hw_set_radar_params()
1462 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); in ar9003_hw_set_radar_params()
1471 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); in ar9003_hw_set_radar_params()
1472 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); in ar9003_hw_set_radar_params()
1474 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1476 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1478 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { in ar9003_hw_set_radar_params()
1479 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1480 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1484 static void ar9003_hw_set_radar_conf(struct ath_hw *ah) in ar9003_hw_set_radar_conf() argument
1486 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1498 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_get() argument
1503 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_get()
1511 if (AR_SREV_9330_11(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1515 } else if (AR_SREV_9485(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1519 } else if (AR_SREV_9565(ah)) { in ar9003_hw_antdiv_comb_conf_get()
1530 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, in ar9003_hw_antdiv_comb_conf_set() argument
1535 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_antdiv_comb_conf_set()
1552 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_antdiv_comb_conf_set()
1557 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) in ar9003_hw_set_bt_ant_diversity() argument
1559 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1563 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) in ar9003_hw_set_bt_ant_diversity()
1566 if (AR_SREV_9485(ah)) { in ar9003_hw_set_bt_ant_diversity()
1567 regval = ar9003_hw_ant_ctrl_common_2_get(ah, in ar9003_hw_set_bt_ant_diversity()
1568 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1571 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1573 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, in ar9003_hw_set_bt_ant_diversity()
1577 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1583 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1586 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1588 if (AR_SREV_9485_11_OR_LATER(ah)) { in ar9003_hw_set_bt_ant_diversity()
1592 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1598 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1603 regval = REG_READ(ah, AR_PHY_CCK_DETECT); in ar9003_hw_set_bt_ant_diversity()
1609 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); in ar9003_hw_set_bt_ant_diversity()
1612 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1625 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1627 } else if (AR_SREV_9565(ah)) { in ar9003_hw_set_bt_ant_diversity()
1629 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1631 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1635 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1637 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1640 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1642 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_set_bt_ant_diversity()
1644 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_set_bt_ant_diversity()
1646 REG_CLR_BIT(ah, AR_PHY_RESTART, in ar9003_hw_set_bt_ant_diversity()
1648 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_set_bt_ant_diversity()
1651 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); in ar9003_hw_set_bt_ant_diversity()
1660 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); in ar9003_hw_set_bt_ant_diversity()
1667 static int ar9003_hw_fast_chan_change(struct ath_hw *ah, in ar9003_hw_fast_chan_change() argument
1679 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; in ar9003_hw_fast_chan_change()
1681 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1686 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1687 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1688 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1689 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1691 if (AR_SREV_9462_20_OR_LATER(ah)) in ar9003_hw_fast_chan_change()
1692 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1695 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1697 if (AR_SREV_9462_20_OR_LATER(ah)) { in ar9003_hw_fast_chan_change()
1701 if (ar9003_hw_get_rx_gain_idx(ah) == 2) { in ar9003_hw_fast_chan_change()
1702 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1704 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1713 if (IS_CHAN_A_FAST_CLOCK(ah, chan)) in ar9003_hw_fast_chan_change()
1714 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1716 if (AR_SREV_9565(ah)) in ar9003_hw_fast_chan_change()
1717 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1723 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1725 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1729 ar9003_hw_set_rfmode(ah, chan); in ar9003_hw_fast_chan_change()
1733 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, in ar9003_hw_spectral_scan_config() argument
1739 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1744 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1745 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
1758 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1761 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1764 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1766 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1768 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_config()
1774 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) in ar9003_hw_spectral_scan_trigger() argument
1776 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1779 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_trigger()
1783 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) in ar9003_hw_spectral_scan_wait() argument
1785 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait()
1788 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, in ar9003_hw_spectral_scan_wait()
1796 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) in ar9003_hw_tx99_start() argument
1798 REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR); in ar9003_hw_tx99_start()
1799 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_start()
1800 REG_WRITE(ah, AR_CR, AR_CR_RXD); in ar9003_hw_tx99_start()
1801 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1802 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ in ar9003_hw_tx99_start()
1803 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); in ar9003_hw_tx99_start()
1804 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1805 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1806 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); in ar9003_hw_tx99_start()
1809 static void ar9003_hw_tx99_stop(struct ath_hw *ah) in ar9003_hw_tx99_stop() argument
1811 REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR); in ar9003_hw_tx99_stop()
1812 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); in ar9003_hw_tx99_stop()
1815 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) in ar9003_hw_tx99_set_txpower() argument
1824 ar9003_hw_tx_power_regwrite(ah, p_pwr_array); in ar9003_hw_tx99_set_txpower()
1827 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) in ar9003_hw_init_txpower_cck() argument
1829 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1830 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1831 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1833 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1837 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ofdm() argument
1845 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1849 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_txpower_ht() argument
1858 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1864 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1870 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1875 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, in ar9003_hw_init_txpower_stbc() argument
1878 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1880 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1882 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1886 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, in ar9003_hw_init_rate_txpower() argument
1890 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1893 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1898 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1904 ar9003_hw_init_txpower_cck(ah, rate_array); in ar9003_hw_init_rate_txpower()
1905 ar9003_hw_init_txpower_ofdm(ah, rate_array, in ar9003_hw_init_rate_txpower()
1908 ar9003_hw_init_txpower_ht(ah, rate_array, in ar9003_hw_init_rate_txpower()
1913 ar9003_hw_init_txpower_stbc(ah, in ar9003_hw_init_rate_txpower()
1921 void ar9003_hw_attach_phy_ops(struct ath_hw *ah) in ar9003_hw_attach_phy_ops() argument
1923 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); in ar9003_hw_attach_phy_ops()
1924 struct ath_hw_ops *ops = ath9k_hw_ops(ah); in ar9003_hw_attach_phy_ops()
1937 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || in ar9003_hw_attach_phy_ops()
1938 AR_SREV_9561(ah)) in ar9003_hw_attach_phy_ops()
1970 ar9003_hw_set_nf_limits(ah); in ar9003_hw_attach_phy_ops()
1971 ar9003_hw_set_radar_conf(ah); in ar9003_hw_attach_phy_ops()
1972 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
2001 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) in ar9003_hw_bb_watchdog_check() argument
2005 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2007 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2010 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2012 val = REG_READ(ah, AR_PHY_RADAR_0); in ar9003_hw_bb_watchdog_check()
2015 REG_WRITE(ah, AR_PHY_RADAR_0, val); in ar9003_hw_bb_watchdog_check()
2024 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) in ar9003_hw_bb_watchdog_check()
2038 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) in ar9003_hw_bb_watchdog_config() argument
2040 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config()
2041 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2046 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2047 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & in ar9003_hw_bb_watchdog_config()
2052 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2053 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & in ar9003_hw_bb_watchdog_config()
2062 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; in ar9003_hw_bb_watchdog_config()
2063 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, in ar9003_hw_bb_watchdog_config()
2081 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2088 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, in ar9003_hw_bb_watchdog_config()
2097 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) in ar9003_hw_bb_watchdog_read() argument
2103 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2109 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, in ar9003_hw_bb_watchdog_read()
2110 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2113 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) in ar9003_hw_bb_watchdog_dbg_info() argument
2115 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info()
2121 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2137 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), in ar9003_hw_bb_watchdog_dbg_info()
2138 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); in ar9003_hw_bb_watchdog_dbg_info()
2140 REG_READ(ah, AR_PHY_GEN_CTRL)); in ar9003_hw_bb_watchdog_dbg_info()
2152 void ar9003_hw_disable_phy_restart(struct ath_hw *ah) in ar9003_hw_disable_phy_restart() argument
2162 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2164 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2165 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()
2166 val = REG_READ(ah, AR_PHY_RESTART); in ar9003_hw_disable_phy_restart()
2168 REG_WRITE(ah, AR_PHY_RESTART, val); in ar9003_hw_disable_phy_restart()