2  * Copyright (c) 2008-2011 Atheros Communications Inc.
18 #include "hw-ops.h"
91 	struct ar5416IniArray *array = &ah->iniBank6;  in ar5008_write_bank6()
92 	u32 *data = ah->analogBank6Data;  in ar5008_write_bank6()
97 	for (r = 0; r < array->ia_rows; r++) {  in ar5008_write_bank6()
106  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
108  * Performs analog "swizzling" of parameters into their location.
119 	arrayEntry = (firstBit - 1) / 8;  in ar5008_hw_phy_modify_rx_buffer()
120 	bitPosition = (firstBit - 1) % 8;  in ar5008_hw_phy_modify_rx_buffer()
125 		mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<  in ar5008_hw_phy_modify_rx_buffer()
130 		bitsLeft -= 8 - bitPosition;  in ar5008_hw_phy_modify_rx_buffer()
131 		tmp32 = tmp32 >> (8 - bitPosition);  in ar5008_hw_phy_modify_rx_buffer()
183 	/* pre-reverse this field */  in ar5008_hw_force_bias()
190 	ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);  in ar5008_hw_force_bias()
197  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
200  * the channel value. Assumes writes enabled to analog bus and bank6 register
201  * cache in ah->analogBank6Data.
219 		if (((freq - 2192) % 5) == 0) {  in ar5008_hw_set_channel()
220 			channelSel = ((freq - 672) * 2 - 3040) / 10;  in ar5008_hw_set_channel()
222 		} else if (((freq - 2224) % 5) == 0) {  in ar5008_hw_set_channel()
223 			channelSel = ((freq - 704) * 2 - 3040) / 10;  in ar5008_hw_set_channel()
227 			return -EINVAL;  in ar5008_hw_set_channel()
245 		    ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);  in ar5008_hw_set_channel()
249 		    ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);  in ar5008_hw_set_channel()
255 		channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);  in ar5008_hw_set_channel()
259 		return -EINVAL;  in ar5008_hw_set_channel()
270 	ah->curchan = chan;  in ar5008_hw_set_channel()
295 	cur_bin = -6000;  in ar5008_hw_cmn_spur_mitigate()
297 	lower = bin - 100;  in ar5008_hw_cmn_spur_mitigate()
318 	lower = bin - 120;  in ar5008_hw_cmn_spur_mitigate()
323 			volatile int tmp_v = abs(cur_vit_mask - bin);  in ar5008_hw_cmn_spur_mitigate()
334 		cur_vit_mask -= 100;  in ar5008_hw_cmn_spur_mitigate()
427  * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
429  * For non single-chip solutions. Converts to baseband spur frequency given the
447 		cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);  in ar5008_hw_spur_mitigate()
450 		cur_bb_spur = cur_bb_spur - (chan->channel * 10);  in ar5008_hw_spur_mitigate()
451 		if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {  in ar5008_hw_spur_mitigate()
492  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
499 	int size = ah->iniBank6.ia_rows * sizeof(u32);  in ar5008_hw_rf_alloc_ext_banks()
504 	ah->analogBank6Data = devm_kzalloc(ah->dev, size, GFP_KERNEL);  in ar5008_hw_rf_alloc_ext_banks()
505 	if (!ah->analogBank6Data)  in ar5008_hw_rf_alloc_ext_banks()
506 		return -ENOMEM;  in ar5008_hw_rf_alloc_ext_banks()
513  * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
521  * all rf registers. This routine requires access to the analog
522  * rf device. This is not required for single-chip devices.
543 	eepMinorRev = ah->eep_ops->get_eeprom_rev(ah);  in ar5008_hw_set_rf_regs()
545 	for (i = 0; i < ah->iniBank6.ia_rows; i++)  in ar5008_hw_set_rf_regs()
546 		ah->analogBank6Data[i] = INI_RA(&ah->iniBank6, i, modesIndex);  in ar5008_hw_set_rf_regs()
551 			ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);  in ar5008_hw_set_rf_regs()
552 			db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);  in ar5008_hw_set_rf_regs()
553 			ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,  in ar5008_hw_set_rf_regs()
555 			ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,  in ar5008_hw_set_rf_regs()
558 			ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);  in ar5008_hw_set_rf_regs()
559 			db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);  in ar5008_hw_set_rf_regs()
560 			ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,  in ar5008_hw_set_rf_regs()
562 			ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,  in ar5008_hw_set_rf_regs()
567 	/* Write Analog registers */  in ar5008_hw_set_rf_regs()
594 	rx_chainmask = ah->rxchainmask;  in ar5008_hw_init_chain_masks()
595 	tx_chainmask = ah->txchainmask;  in ar5008_hw_init_chain_masks()
604 		if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {  in ar5008_hw_init_chain_masks()
738 	 * Set correct baseband to analog shift setting to  in ar5008_hw_process_ini()
739 	 * access analog chips.  in ar5008_hw_process_ini()
745 	if (ah->eep_ops->set_addac)  in ar5008_hw_process_ini()
746 		ah->eep_ops->set_addac(ah, chan);  in ar5008_hw_process_ini()
748 	REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);  in ar5008_hw_process_ini()
753 	for (i = 0; i < ah->iniModes.ia_rows; i++) {  in ar5008_hw_process_ini()
754 		u32 reg = INI_RA(&ah->iniModes, i, 0);  in ar5008_hw_process_ini()
755 		u32 val = INI_RA(&ah->iniModes, i, modesIndex);  in ar5008_hw_process_ini()
757 		if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)  in ar5008_hw_process_ini()
763 		    && ah->config.analog_shiftreg  in ar5008_hw_process_ini()
764 		    && (common->bus_ops->ath_bus_type != ATH_USB)) {  in ar5008_hw_process_ini()
774 		REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);  in ar5008_hw_process_ini()
778 		REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);  in ar5008_hw_process_ini()
788 	for (i = 0; i < ah->iniCommon.ia_rows; i++) {  in ar5008_hw_process_ini()
789 		u32 reg = INI_RA(&ah->iniCommon, i, 0);  in ar5008_hw_process_ini()
790 		u32 val = INI_RA(&ah->iniCommon, i, 1);  in ar5008_hw_process_ini()
795 		    && ah->config.analog_shiftreg  in ar5008_hw_process_ini()
796 		    && (common->bus_ops->ath_bus_type != ATH_USB)) {  in ar5008_hw_process_ini()
805 	REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);  in ar5008_hw_process_ini()
808 		REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex,  in ar5008_hw_process_ini()
817 	/* Write analog registers */  in ar5008_hw_process_ini()
820 		return -EIO;  in ar5008_hw_process_ini()
898 	ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);  in ar5008_hw_rfbus_done()
905 	int rx_chainmask = ah->rxchainmask;  in ar5008_restore_chainmask()
958 	struct ath9k_channel *chan = ah->curchan;  in ar5008_hw_ani_control_new()
959 	struct ar5416AniState *aniState = &ah->ani;  in ar5008_hw_ani_control_new()
962 	switch (cmd & ah->ani_function) {  in ar5008_hw_ani_control_new()
977 			aniState->iniDef.m1ThreshLow : m1ThreshLow_off;  in ar5008_hw_ani_control_new()
979 			aniState->iniDef.m2ThreshLow : m2ThreshLow_off;  in ar5008_hw_ani_control_new()
981 			aniState->iniDef.m1Thresh : m1Thresh_off;  in ar5008_hw_ani_control_new()
983 			aniState->iniDef.m2Thresh : m2Thresh_off;  in ar5008_hw_ani_control_new()
985 			aniState->iniDef.m2CountThr : m2CountThr_off;  in ar5008_hw_ani_control_new()
987 			aniState->iniDef.m2CountThrLow : m2CountThrLow_off;  in ar5008_hw_ani_control_new()
989 			aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;  in ar5008_hw_ani_control_new()
991 			aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;  in ar5008_hw_ani_control_new()
993 			aniState->iniDef.m1ThreshExt : m1ThreshExt_off;  in ar5008_hw_ani_control_new()
995 			aniState->iniDef.m2ThreshExt : m2ThreshExt_off;  in ar5008_hw_ani_control_new()
1029 		if (on != aniState->ofdmWeakSigDetect) {  in ar5008_hw_ani_control_new()
1032 				chan->channel,  in ar5008_hw_ani_control_new()
1033 				aniState->ofdmWeakSigDetect ?  in ar5008_hw_ani_control_new()
1037 				ah->stats.ast_ani_ofdmon++;  in ar5008_hw_ani_control_new()
1039 				ah->stats.ast_ani_ofdmoff++;  in ar5008_hw_ani_control_new()
1040 			aniState->ofdmWeakSigDetect = on;  in ar5008_hw_ani_control_new()
1045 		u32 level = param;  in ar5008_hw_ani_control_new()  local
1047 		value = level * 2;  in ar5008_hw_ani_control_new()
1053 		if (level != aniState->firstepLevel) {  in ar5008_hw_ani_control_new()
1055 				"** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",  in ar5008_hw_ani_control_new()
1056 				chan->channel,  in ar5008_hw_ani_control_new()
1057 				aniState->firstepLevel,  in ar5008_hw_ani_control_new()
1058 				level,  in ar5008_hw_ani_control_new()
1061 				aniState->iniDef.firstep);  in ar5008_hw_ani_control_new()
1063 				"** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",  in ar5008_hw_ani_control_new()
1064 				chan->channel,  in ar5008_hw_ani_control_new()
1065 				aniState->firstepLevel,  in ar5008_hw_ani_control_new()
1066 				level,  in ar5008_hw_ani_control_new()
1069 				aniState->iniDef.firstepLow);  in ar5008_hw_ani_control_new()
1070 			if (level > aniState->firstepLevel)  in ar5008_hw_ani_control_new()
1071 				ah->stats.ast_ani_stepup++;  in ar5008_hw_ani_control_new()
1072 			else if (level < aniState->firstepLevel)  in ar5008_hw_ani_control_new()
1073 				ah->stats.ast_ani_stepdown++;  in ar5008_hw_ani_control_new()
1074 			aniState->firstepLevel = level;  in ar5008_hw_ani_control_new()
1079 		u32 level = param;  in ar5008_hw_ani_control_new()  local
1081 		value = (level + 1) * 2;  in ar5008_hw_ani_control_new()
1086 				  AR_PHY_EXT_TIMING5_CYCPWR_THR1, value - 1);  in ar5008_hw_ani_control_new()
1088 		if (level != aniState->spurImmunityLevel) {  in ar5008_hw_ani_control_new()
1090 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",  in ar5008_hw_ani_control_new()
1091 				chan->channel,  in ar5008_hw_ani_control_new()
1092 				aniState->spurImmunityLevel,  in ar5008_hw_ani_control_new()
1093 				level,  in ar5008_hw_ani_control_new()
1096 				aniState->iniDef.cycpwrThr1);  in ar5008_hw_ani_control_new()
1098 				"** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",  in ar5008_hw_ani_control_new()
1099 				chan->channel,  in ar5008_hw_ani_control_new()
1100 				aniState->spurImmunityLevel,  in ar5008_hw_ani_control_new()
1101 				level,  in ar5008_hw_ani_control_new()
1104 				aniState->iniDef.cycpwrThr1Ext);  in ar5008_hw_ani_control_new()
1105 			if (level > aniState->spurImmunityLevel)  in ar5008_hw_ani_control_new()
1106 				ah->stats.ast_ani_spurup++;  in ar5008_hw_ani_control_new()
1107 			else if (level < aniState->spurImmunityLevel)  in ar5008_hw_ani_control_new()
1108 				ah->stats.ast_ani_spurdown++;  in ar5008_hw_ani_control_new()
1109 			aniState->spurImmunityLevel = level;  in ar5008_hw_ani_control_new()
1127 		aniState->spurImmunityLevel,  in ar5008_hw_ani_control_new()
1128 		aniState->ofdmWeakSigDetect ? "on" : "off",  in ar5008_hw_ani_control_new()
1129 		aniState->firstepLevel,  in ar5008_hw_ani_control_new()
1130 		aniState->mrcCCK ? "on" : "off",  in ar5008_hw_ani_control_new()
1131 		aniState->listenTime,  in ar5008_hw_ani_control_new()
1132 		aniState->ofdmPhyErrCount,  in ar5008_hw_ani_control_new()
1133 		aniState->cckPhyErrCount);  in ar5008_hw_ani_control_new()
1151 	if (!IS_CHAN_HT40(ah->curchan))  in ar5008_hw_do_getnf()
1172 	struct ath9k_channel *chan = ah->curchan;  in ar5008_hw_ani_cache_ini_regs()
1173 	struct ar5416AniState *aniState = &ah->ani;  in ar5008_hw_ani_cache_ini_regs()
1177 	iniDef = &aniState->iniDef;  in ar5008_hw_ani_cache_ini_regs()
1180 		ah->hw_version.macVersion,  in ar5008_hw_ani_cache_ini_regs()
1181 		ah->hw_version.macRev,  in ar5008_hw_ani_cache_ini_regs()
1182 		ah->opmode,  in ar5008_hw_ani_cache_ini_regs()
1183 		chan->channel);  in ar5008_hw_ani_cache_ini_regs()
1186 	iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);  in ar5008_hw_ani_cache_ini_regs()
1187 	iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);  in ar5008_hw_ani_cache_ini_regs()
1188 	iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);  in ar5008_hw_ani_cache_ini_regs()
1191 	iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);  in ar5008_hw_ani_cache_ini_regs()
1192 	iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);  in ar5008_hw_ani_cache_ini_regs()
1193 	iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);  in ar5008_hw_ani_cache_ini_regs()
1196 	iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);  in ar5008_hw_ani_cache_ini_regs()
1197 	iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);  in ar5008_hw_ani_cache_ini_regs()
1198 	iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);  in ar5008_hw_ani_cache_ini_regs()
1199 	iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);  in ar5008_hw_ani_cache_ini_regs()
1200 	iniDef->firstep = REG_READ_FIELD(ah,  in ar5008_hw_ani_cache_ini_regs()
1203 	iniDef->firstepLow = REG_READ_FIELD(ah,  in ar5008_hw_ani_cache_ini_regs()
1206 	iniDef->cycpwrThr1 = REG_READ_FIELD(ah,  in ar5008_hw_ani_cache_ini_regs()
1209 	iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,  in ar5008_hw_ani_cache_ini_regs()
1214 	aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;  in ar5008_hw_ani_cache_ini_regs()
1215 	aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;  in ar5008_hw_ani_cache_ini_regs()
1216 	aniState->ofdmWeakSigDetect = true;  in ar5008_hw_ani_cache_ini_regs()
1217 	aniState->mrcCCK = false; /* not available on pre AR9003 */  in ar5008_hw_ani_cache_ini_regs()
1222 	ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;  in ar5008_hw_set_nf_limits()
1223 	ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;  in ar5008_hw_set_nf_limits()
1224 	ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;  in ar5008_hw_set_nf_limits()
1225 	ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;  in ar5008_hw_set_nf_limits()
1226 	ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;  in ar5008_hw_set_nf_limits()
1227 	ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;  in ar5008_hw_set_nf_limits()
1241 	radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);  in ar5008_hw_set_radar_params()
1242 	radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);  in ar5008_hw_set_radar_params()
1243 	radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);  in ar5008_hw_set_radar_params()
1244 	radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);  in ar5008_hw_set_radar_params()
1245 	radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);  in ar5008_hw_set_radar_params()
1252 	radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);  in ar5008_hw_set_radar_params()
1253 	radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);  in ar5008_hw_set_radar_params()
1254 	radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);  in ar5008_hw_set_radar_params()
1258 	if (conf->ext_channel)  in ar5008_hw_set_radar_params()
1266 	struct ath_hw_radar_conf *conf = &ah->radar_conf;  in ar5008_hw_set_radar_conf()
1268 	conf->fir_power = -33;  in ar5008_hw_set_radar_conf()
1269 	conf->radar_rssi = 20;  in ar5008_hw_set_radar_conf()
1270 	conf->pulse_height = 10;  in ar5008_hw_set_radar_conf()
1271 	conf->pulse_rssi = 15;  in ar5008_hw_set_radar_conf()
1272 	conf->pulse_inband = 15;  in ar5008_hw_set_radar_conf()
1273 	conf->pulse_maxlen = 255;  in ar5008_hw_set_radar_conf()
1274 	conf->pulse_inband_step = 12;  in ar5008_hw_set_radar_conf()
1275 	conf->radar_inband = 8;  in ar5008_hw_set_radar_conf()
1280 #define CCK_DELTA(_ah, x) ((OLC_FOR_AR9280_20_LATER(_ah)) ? max((x) - 2, 0) : (x))  in ar5008_hw_init_txpower_cck()
1281 	ah->tx_power[0] = CCK_DELTA(ah, rate_array[rate1l]);  in ar5008_hw_init_txpower_cck()
1282 	ah->tx_power[1] = CCK_DELTA(ah, min(rate_array[rate2l],  in ar5008_hw_init_txpower_cck()
1284 	ah->tx_power[2] = CCK_DELTA(ah, min(rate_array[rate5_5l],  in ar5008_hw_init_txpower_cck()
1286 	ah->tx_power[3] = CCK_DELTA(ah, min(rate_array[rate11l],  in ar5008_hw_init_txpower_cck()
1297 		ah->tx_power[i] = rate_array[idx];  in ar5008_hw_init_txpower_ofdm()
1309 		ah->tx_power[i] = rate_array[mcs_idx] + ht40_delta;  in ar5008_hw_init_txpower_ht()
1312 	memcpy(&ah->tx_power[ds_offset], &ah->tx_power[ss_offset],  in ar5008_hw_init_txpower_ht()
1360 	priv_ops->rf_set_freq = ar5008_hw_set_channel;  in ar5008_hw_attach_phy_ops()
1361 	priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;  in ar5008_hw_attach_phy_ops()
1363 	priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;  in ar5008_hw_attach_phy_ops()
1364 	priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;  in ar5008_hw_attach_phy_ops()
1365 	priv_ops->init_bb = ar5008_hw_init_bb;  in ar5008_hw_attach_phy_ops()
1366 	priv_ops->process_ini = ar5008_hw_process_ini;  in ar5008_hw_attach_phy_ops()
1367 	priv_ops->set_rfmode = ar5008_hw_set_rfmode;  in ar5008_hw_attach_phy_ops()
1368 	priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;  in ar5008_hw_attach_phy_ops()
1369 	priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;  in ar5008_hw_attach_phy_ops()
1370 	priv_ops->rfbus_req = ar5008_hw_rfbus_req;  in ar5008_hw_attach_phy_ops()
1371 	priv_ops->rfbus_done = ar5008_hw_rfbus_done;  in ar5008_hw_attach_phy_ops()
1372 	priv_ops->restore_chainmask = ar5008_restore_chainmask;  in ar5008_hw_attach_phy_ops()
1373 	priv_ops->do_getnf = ar5008_hw_do_getnf;  in ar5008_hw_attach_phy_ops()
1374 	priv_ops->set_radar_params = ar5008_hw_set_radar_params;  in ar5008_hw_attach_phy_ops()
1376 	priv_ops->ani_control = ar5008_hw_ani_control_new;  in ar5008_hw_attach_phy_ops()
1377 	priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;  in ar5008_hw_attach_phy_ops()
1380 		priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;  in ar5008_hw_attach_phy_ops()
1382 		priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;  in ar5008_hw_attach_phy_ops()
1386 	memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));  in ar5008_hw_attach_phy_ops()