2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4  * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
5  * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
6  * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
30 #include <linux/pci.h>		/* To determine if a card is pci-e */
52  * ath5k_hw_register_timeout() - Poll a register for a flag/field change
64  * Returns -EAGAIN if we exceeded AR5K_TUNE_REGISTER_TIMEOUT * 15us or 0
73 	for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {  in ath5k_hw_register_timeout()
82 	return (i <= 0) ? -EAGAIN : 0;  in ath5k_hw_register_timeout()
91  * ath5k_hw_htoclock() - Translate usec to hw clock units
104 	return usec * common->clockrate;  in ath5k_hw_htoclock()
108  * ath5k_hw_clocktoh() - Translate hw clock units to usec
121 	return clock / common->clockrate;  in ath5k_hw_clocktoh()
125  * ath5k_hw_init_core_clock() - Initialize core clock
134 	struct ieee80211_channel *channel = ah->ah_current_channel;  in ath5k_hw_init_core_clock()
141 	switch (channel->hw_value) {  in ath5k_hw_init_core_clock()
154 	/* Use clock multiplier for non-default  in ath5k_hw_init_core_clock()
156 	switch (ah->ah_bwmode) {  in ath5k_hw_init_core_clock()
170 	common->clockrate = clock;  in ath5k_hw_init_core_clock()
176 	usec = clock - 1;  in ath5k_hw_init_core_clock()
180 	if (ah->ah_version != AR5K_AR5210)  in ath5k_hw_init_core_clock()
186 	if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_init_core_clock()
187 	    (ah->ah_radio == AR5K_RF2413) ||  in ath5k_hw_init_core_clock()
188 	    (ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_init_core_clock()
189 	    (ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_init_core_clock()
190 	    (ah->ah_radio == AR5K_RF2317))  in ath5k_hw_init_core_clock()
192 		sclock = 40 - 1;  in ath5k_hw_init_core_clock()
194 		sclock = 32 - 1;  in ath5k_hw_init_core_clock()
214 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_init_core_clock()
220 	if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_init_core_clock()
227 		 * are the same for turbo mode */  in ath5k_hw_init_core_clock()
231 	switch (ah->ah_bwmode) {  in ath5k_hw_init_core_clock()
260 	if (ah->ah_radio == AR5K_RF5112) {  in ath5k_hw_init_core_clock()
268  * ath5k_hw_set_sleep_clock() - Setup sleep clock operation
277  * NOTE: When operating on 32KHz certain PHY registers (27 - 31,
278  * 123 - 127) require delay on access.
283 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_set_sleep_clock()
288 	if ((AR5K_EEPROM_HAS32KHZCRYSTAL(ee->ee_misc1) ||  in ath5k_hw_set_sleep_clock()
289 	AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(ee->ee_misc1)) &&  in ath5k_hw_set_sleep_clock()
301 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
302 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
303 		(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
304 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))  in ath5k_hw_set_sleep_clock()
310 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
311 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
312 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {  in ath5k_hw_set_sleep_clock()
346 		if (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))  in ath5k_hw_set_sleep_clock()
348 		else if (ee->ee_is_hb63)  in ath5k_hw_set_sleep_clock()
357 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
358 		(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
359 		(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
360 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))  in ath5k_hw_set_sleep_clock()
369 		if ((ah->ah_radio == AR5K_RF5112) ||  in ath5k_hw_set_sleep_clock()
370 			(ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_set_sleep_clock()
371 			(ah->ah_radio == AR5K_RF2316) ||  in ath5k_hw_set_sleep_clock()
372 			(ah->ah_radio == AR5K_RF2317))  in ath5k_hw_set_sleep_clock()
373 			sclock = 40 - 1;  in ath5k_hw_set_sleep_clock()
375 			sclock = 32 - 1;  in ath5k_hw_set_sleep_clock()
386  * ath5k_hw_nic_reset() - Reset the various chipset units
394  * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
402 	/* Read-and-clear RX Descriptor Pointer*/  in ath5k_hw_nic_reset()
413 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_nic_reset()
426 	 * Reset configuration register (for hw byte-swap). Note that this  in ath5k_hw_nic_reset()
437  * ath5k_hw_wisoc_reset() -  Reset AHB chipset
443  * Returns 0 if we are O.K. or -EAGAIN (from athk5_hw_register_timeout)
453 	/* ah->ah_mac_srev is not available at this point yet */  in ath5k_hw_wisoc_reset()
454 	if (ah->devid >= AR5K_SREV_AR2315_R6) {  in ath5k_hw_wisoc_reset()
462 		if (to_platform_device(ah->dev)->id == 0) {  in ath5k_hw_wisoc_reset()
488 	 * Reset configuration register (for hw byte-swap). Note that this  in ath5k_hw_wisoc_reset()
499  * ath5k_hw_set_power_mode() - Set power mode
501  * @mode: One of enum ath5k_power_mode
510  * Returns 0 on success, -EIO if chip didn't wake up or -EINVAL if an invalid
511  * mode is requested.
514 ath5k_hw_set_power_mode(struct ath5k_hw *ah, enum ath5k_power_mode mode,  in ath5k_hw_set_power_mode()  argument
522 	switch (mode) {  in ath5k_hw_set_power_mode()
566 		for (i = 200; i > 0; i--) {  in ath5k_hw_set_power_mode()
580 			return -EIO;  in ath5k_hw_set_power_mode()
585 		return -EINVAL;  in ath5k_hw_set_power_mode()
595  * ath5k_hw_on_hold() - Put device on hold
604  * Returns 0 on success or -EIO on error
609 	struct pci_dev *pdev = ah->pdev;  in ath5k_hw_on_hold()
626 	 * Note: putting PCI core on warm reset on PCI-E cards  in ath5k_hw_on_hold()
628 	 * we ignore that flag for PCI-E cards. On PCI cards  in ath5k_hw_on_hold()
633 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_on_hold()
645 		return -EIO;  in ath5k_hw_on_hold()
659  * ath5k_hw_nic_wakeup() - Force card out of sleep
666  * Returns 0 on success, -EIO on hw failure or -EINVAL for false channel infos
671 	struct pci_dev *pdev = ah->pdev;  in ath5k_hw_nic_wakeup()
672 	u32 turbo, mode, clock, bus_flags;  in ath5k_hw_nic_wakeup()  local
676 	mode = 0;  in ath5k_hw_nic_wakeup()
691 	 * Note: putting PCI core on warm reset on PCI-E cards  in ath5k_hw_nic_wakeup()
693 	 * we ignore that flag for PCI-E cards. On PCI cards  in ath5k_hw_nic_wakeup()
698 	if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
714 		return -EIO;  in ath5k_hw_nic_wakeup()
734 		return -EIO;  in ath5k_hw_nic_wakeup()
738 	 * a channel / mode set yet */  in ath5k_hw_nic_wakeup()
742 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
744 		 * Get channel mode flags  in ath5k_hw_nic_wakeup()
747 		if (ah->ah_radio >= AR5K_RF5112) {  in ath5k_hw_nic_wakeup()
748 			mode = AR5K_PHY_MODE_RAD_RF5112;  in ath5k_hw_nic_wakeup()
751 			mode = AR5K_PHY_MODE_RAD_RF5111;	/*Zero*/  in ath5k_hw_nic_wakeup()
755 		if (channel->band == NL80211_BAND_2GHZ) {  in ath5k_hw_nic_wakeup()
756 			mode |= AR5K_PHY_MODE_FREQ_2GHZ;  in ath5k_hw_nic_wakeup()
759 			if (channel->hw_value == AR5K_MODE_11B) {  in ath5k_hw_nic_wakeup()
760 				mode |= AR5K_PHY_MODE_MOD_CCK;  in ath5k_hw_nic_wakeup()
765 				 * this, 5211 might support ofdm-only g after  in ath5k_hw_nic_wakeup()
767 				 * in the code for g mode (see initvals.c).  in ath5k_hw_nic_wakeup()
769 				if (ah->ah_version == AR5K_AR5211)  in ath5k_hw_nic_wakeup()
770 					mode |= AR5K_PHY_MODE_MOD_OFDM;  in ath5k_hw_nic_wakeup()
772 					mode |= AR5K_PHY_MODE_MOD_DYN;  in ath5k_hw_nic_wakeup()
774 		} else if (channel->band == NL80211_BAND_5GHZ) {  in ath5k_hw_nic_wakeup()
775 			mode |= (AR5K_PHY_MODE_FREQ_5GHZ |  in ath5k_hw_nic_wakeup()
779 			if (ah->ah_radio == AR5K_RF5413)  in ath5k_hw_nic_wakeup()
784 			ATH5K_ERR(ah, "invalid radio frequency mode\n");  in ath5k_hw_nic_wakeup()
785 			return -EINVAL;  in ath5k_hw_nic_wakeup()
788 		/*XXX: Can bwmode be used with dynamic mode ?  in ath5k_hw_nic_wakeup()
791 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {  in ath5k_hw_nic_wakeup()
793 			if (ah->ah_radio != AR5K_RF2425)  in ath5k_hw_nic_wakeup()
795 		} else if (ah->ah_bwmode != AR5K_BWMODE_DEFAULT) {  in ath5k_hw_nic_wakeup()
796 			if (ah->ah_radio == AR5K_RF5413) {  in ath5k_hw_nic_wakeup()
797 				mode |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?  in ath5k_hw_nic_wakeup()
800 			} else if (ah->ah_version == AR5K_AR5212) {  in ath5k_hw_nic_wakeup()
801 				clock |= (ah->ah_bwmode == AR5K_BWMODE_10MHZ) ?  in ath5k_hw_nic_wakeup()
809 		/* ...enable Atheros turbo mode if requested */  in ath5k_hw_nic_wakeup()
810 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)  in ath5k_hw_nic_wakeup()
815 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_nic_wakeup()
823 		/* ...set the PHY operating mode */  in ath5k_hw_nic_wakeup()
824 		ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);  in ath5k_hw_nic_wakeup()
833 * Post-initvals register modifications *
837  * ath5k_hw_tweak_initval_settings() - Tweak initial settings
851 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_tweak_initval_settings()
852 	    ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {  in ath5k_hw_tweak_initval_settings()
878 	if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212B)  in ath5k_hw_tweak_initval_settings()
882 	if (ah->ah_phy_revision > AR5K_SREV_PHY_5212B)  in ath5k_hw_tweak_initval_settings()
886 	/* Set fast ADC */  in ath5k_hw_tweak_initval_settings()
887 	if ((ah->ah_radio == AR5K_RF5413) ||  in ath5k_hw_tweak_initval_settings()
888 		(ah->ah_radio == AR5K_RF2317) ||  in ath5k_hw_tweak_initval_settings()
889 		(ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4))) {  in ath5k_hw_tweak_initval_settings()
892 		if (channel->center_freq == 2462 ||  in ath5k_hw_tweak_initval_settings()
893 		channel->center_freq == 2467)  in ath5k_hw_tweak_initval_settings()
903 	if (ah->ah_radio == AR5K_RF5112 &&  in ath5k_hw_tweak_initval_settings()
904 			ah->ah_radio_5ghz_revision <  in ath5k_hw_tweak_initval_settings()
909 		if (channel->band == NL80211_BAND_5GHZ)  in ath5k_hw_tweak_initval_settings()
916 	if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_tweak_initval_settings()
927 	if (ah->ah_bwmode) {  in ath5k_hw_tweak_initval_settings()
929 		 * on turbo mode (ath5k_hw_commit_eeprom_settings  in ath5k_hw_tweak_initval_settings()
931 		if (ah->ah_bwmode == AR5K_BWMODE_40MHZ) {  in ath5k_hw_tweak_initval_settings()
940 			if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_tweak_initval_settings()
945 			if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_tweak_initval_settings()
954 		} else if ((ah->ah_mac_srev >= AR5K_SREV_AR5424) &&  in ath5k_hw_tweak_initval_settings()
955 		(ah->ah_mac_srev <= AR5K_SREV_AR5414)) {  in ath5k_hw_tweak_initval_settings()
960 	} else if (ah->ah_version == AR5K_AR5210) {  in ath5k_hw_tweak_initval_settings()
968  * ath5k_hw_commit_eeprom_settings() - Commit settings from EEPROM
973  * based on various infos and per-mode calibration data.
979 	struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;  in ath5k_hw_commit_eeprom_settings()
984 	if (ah->ah_version == AR5K_AR5210)  in ath5k_hw_commit_eeprom_settings()
990 	if (channel->center_freq == 2484)  in ath5k_hw_commit_eeprom_settings()
992 			((ee->ee_cck_ofdm_power_delta -  in ath5k_hw_commit_eeprom_settings()
993 			ee->ee_scaled_cck_delta) * 2) / 10;  in ath5k_hw_commit_eeprom_settings()
996 			(ee->ee_cck_ofdm_power_delta * 2) / 10;  in ath5k_hw_commit_eeprom_settings()
1000 	if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {  in ath5k_hw_commit_eeprom_settings()
1001 		if (channel->hw_value == AR5K_MODE_11G)  in ath5k_hw_commit_eeprom_settings()
1003 			AR5K_REG_SM((ee->ee_cck_ofdm_gain_delta * -1),  in ath5k_hw_commit_eeprom_settings()
1005 			AR5K_REG_SM((cck_ofdm_pwr_delta * -1),  in ath5k_hw_commit_eeprom_settings()
1013 		ah->ah_txpower.txp_cck_ofdm_pwr_delta = cck_ofdm_pwr_delta;  in ath5k_hw_commit_eeprom_settings()
1014 		ah->ah_txpower.txp_cck_ofdm_gainf_delta =  in ath5k_hw_commit_eeprom_settings()
1015 						ee->ee_cck_ofdm_gain_delta;  in ath5k_hw_commit_eeprom_settings()
1024 		AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),  in ath5k_hw_commit_eeprom_settings()
1027 	if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&  in ath5k_hw_commit_eeprom_settings()
1028 	(ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_0)) {  in ath5k_hw_commit_eeprom_settings()
1032 				ee->ee_switch_settling_turbo[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1037 				ee->ee_atn_tx_rx_turbo[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1042 				ee->ee_adc_desired_size_turbo[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1046 				ee->ee_pga_desired_size_turbo[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1051 				ee->ee_margin_tx_rx_turbo[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1057 				ee->ee_switch_settling[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1062 				ee->ee_atn_tx_rx[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1067 				ee->ee_adc_desired_size[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1071 				ee->ee_pga_desired_size[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1074 		if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)  in ath5k_hw_commit_eeprom_settings()
1077 				ee->ee_margin_tx_rx[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1082 		(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |  in ath5k_hw_commit_eeprom_settings()
1083 		(ee->ee_tx_end2xpa_disable[ee_mode] << 16) |  in ath5k_hw_commit_eeprom_settings()
1084 		(ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |  in ath5k_hw_commit_eeprom_settings()
1085 		(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY_RF_CTL4);  in ath5k_hw_commit_eeprom_settings()
1090 			ee->ee_tx_end2xlna_enable[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1095 			ee->ee_thr_62[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1104 				ee->ee_false_detect[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1112 	if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {  in ath5k_hw_commit_eeprom_settings()
1114 			    ee->ee_i_cal[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1116 			    ee->ee_q_cal[ee_mode]);  in ath5k_hw_commit_eeprom_settings()
1120 	/* Heavy clipping -disable for now */  in ath5k_hw_commit_eeprom_settings()
1121 	if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_5_1)  in ath5k_hw_commit_eeprom_settings()
1131  * ath5k_hw_reset() - The main reset function
1135  * @fast: Enable fast channel switching
1142  * Returns 0 on success, -EINVAL on false op_mode or channel infos, or -EIO
1147 		struct ieee80211_channel *channel, bool fast, bool skip_pcu)  in ath5k_hw_reset()  argument
1150 	u8 mode;  in ath5k_hw_reset()  local
1155 	mode = 0;  in ath5k_hw_reset()
1158 	 * Sanity check for fast flag  in ath5k_hw_reset()
1159 	 * Fast channel change only available  in ath5k_hw_reset()
1162 	if (fast && (ah->ah_radio != AR5K_RF2413) &&  in ath5k_hw_reset()
1163 	(ah->ah_radio != AR5K_RF5413))  in ath5k_hw_reset()
1164 		fast = false;  in ath5k_hw_reset()
1169 	if (ah->ah_version == AR5K_AR5212)  in ath5k_hw_reset()
1172 	mode = channel->hw_value;  in ath5k_hw_reset()
1173 	switch (mode) {  in ath5k_hw_reset()
1177 		if (ah->ah_version <= AR5K_AR5211) {  in ath5k_hw_reset()
1179 				"G mode not available on 5210/5211");  in ath5k_hw_reset()
1180 			return -EINVAL;  in ath5k_hw_reset()
1184 		if (ah->ah_version < AR5K_AR5211) {  in ath5k_hw_reset()
1186 				"B mode not available on 5210");  in ath5k_hw_reset()
1187 			return -EINVAL;  in ath5k_hw_reset()
1192 			"invalid channel: %d\n", channel->center_freq);  in ath5k_hw_reset()
1193 		return -EINVAL;  in ath5k_hw_reset()
1197 	 * If driver requested fast channel change and DMA has stopped  in ath5k_hw_reset()
1200 	if (fast) {  in ath5k_hw_reset()
1201 		ret = ath5k_hw_phy_init(ah, channel, mode, true);  in ath5k_hw_reset()
1204 				"fast chan change failed, falling back to normal reset\n");  in ath5k_hw_reset()
1206 			 * on mode change */  in ath5k_hw_reset()
1210 				"fast chan change successful\n");  in ath5k_hw_reset()
1218 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_reset()
1224 		if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_reset()
1238 		 * reset. This way it'll get re-synced on the  in ath5k_hw_reset()
1239 		 * next beacon without breaking ad-hoc.  in ath5k_hw_reset()
1248 		if (ah->ah_version == AR5K_AR5211) {  in ath5k_hw_reset()
1267 	if (ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_reset()
1268 	(ah->ah_radio <= AR5K_RF5112)) {  in ath5k_hw_reset()
1269 		if (!fast && ah->ah_rf_banks != NULL)  in ath5k_hw_reset()
1279 	if (ah->ah_mac_srev >= AR5K_SREV_AR5211)  in ath5k_hw_reset()
1286 	ret = ath5k_hw_write_initvals(ah, mode, skip_pcu);  in ath5k_hw_reset()
1309 	if (ah->ah_version != AR5K_AR5210) {  in ath5k_hw_reset()
1310 		if (ah->ah_mac_srev < AR5K_SREV_AR5211) {  in ath5k_hw_reset()
1319 		if (ah->ah_version == AR5K_AR5211) {  in ath5k_hw_reset()
1340 	ret = ath5k_hw_phy_init(ah, channel, mode, false);  in ath5k_hw_reset()
1370 	if (ah->ah_use_32khz_clock && ah->ah_version == AR5K_AR5212 &&  in ath5k_hw_reset()