Lines Matching refs:ah
35 static int ath5k_hw_post(struct ath5k_hw *ah) in ath5k_hw_post() argument
54 init_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
58 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
59 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
62 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
68 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
73 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
74 cur_val = ath5k_hw_reg_read(ah, cur_reg); in ath5k_hw_post()
77 ATH5K_ERR(ah, "POST Failed !!!\n"); in ath5k_hw_post()
83 ath5k_hw_reg_write(ah, var_pattern, cur_reg); in ath5k_hw_post()
87 ath5k_hw_reg_write(ah, init_val, cur_reg); in ath5k_hw_post()
104 int ath5k_hw_init(struct ath5k_hw *ah) in ath5k_hw_init() argument
107 struct ath_common *common = ath5k_hw_common(ah); in ath5k_hw_init()
108 struct pci_dev *pdev = ah->pdev; in ath5k_hw_init()
116 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; in ath5k_hw_init()
117 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER; in ath5k_hw_init()
118 ah->ah_imr = 0; in ath5k_hw_init()
119 ah->ah_retry_short = AR5K_INIT_RETRY_SHORT; in ath5k_hw_init()
120 ah->ah_retry_long = AR5K_INIT_RETRY_LONG; in ath5k_hw_init()
121 ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT; in ath5k_hw_init()
122 ah->ah_noise_floor = -95; /* until first NF calibration is run */ in ath5k_hw_init()
123 ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO; in ath5k_hw_init()
124 ah->ah_current_channel = &ah->channels[0]; in ath5k_hw_init()
129 ath5k_hw_read_srev(ah); in ath5k_hw_init()
130 srev = ah->ah_mac_srev; in ath5k_hw_init()
132 ah->ah_version = AR5K_AR5210; in ath5k_hw_init()
134 ah->ah_version = AR5K_AR5211; in ath5k_hw_init()
136 ah->ah_version = AR5K_AR5212; in ath5k_hw_init()
139 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER); in ath5k_hw_init()
142 ret = ath5k_hw_init_desc_functions(ah); in ath5k_hw_init()
147 ret = ath5k_hw_nic_wakeup(ah, NULL); in ath5k_hw_init()
152 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) & in ath5k_hw_init()
154 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
158 switch (ah->ah_radio_5ghz_revision & 0xf0) { in ath5k_hw_init()
160 ah->ah_radio = AR5K_RF5111; in ath5k_hw_init()
161 ah->ah_single_chip = false; in ath5k_hw_init()
162 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
167 ah->ah_radio = AR5K_RF5112; in ath5k_hw_init()
168 ah->ah_single_chip = false; in ath5k_hw_init()
169 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
173 ah->ah_radio = AR5K_RF2413; in ath5k_hw_init()
174 ah->ah_single_chip = true; in ath5k_hw_init()
177 ah->ah_radio = AR5K_RF5413; in ath5k_hw_init()
178 ah->ah_single_chip = true; in ath5k_hw_init()
181 ah->ah_radio = AR5K_RF2316; in ath5k_hw_init()
182 ah->ah_single_chip = true; in ath5k_hw_init()
185 ah->ah_radio = AR5K_RF2317; in ath5k_hw_init()
186 ah->ah_single_chip = true; in ath5k_hw_init()
189 if (ah->ah_mac_version == AR5K_SREV_AR2425 || in ath5k_hw_init()
190 ah->ah_mac_version == AR5K_SREV_AR2417) { in ath5k_hw_init()
191 ah->ah_radio = AR5K_RF2425; in ath5k_hw_init()
192 ah->ah_single_chip = true; in ath5k_hw_init()
194 ah->ah_radio = AR5K_RF5413; in ath5k_hw_init()
195 ah->ah_single_chip = true; in ath5k_hw_init()
200 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_init()
201 ah->ah_radio = AR5K_RF5110; in ath5k_hw_init()
202 ah->ah_single_chip = false; in ath5k_hw_init()
203 } else if (ah->ah_version == AR5K_AR5211) { in ath5k_hw_init()
204 ah->ah_radio = AR5K_RF5111; in ath5k_hw_init()
205 ah->ah_single_chip = false; in ath5k_hw_init()
206 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah, in ath5k_hw_init()
208 } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) || in ath5k_hw_init()
209 ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) || in ath5k_hw_init()
210 ah->ah_phy_revision == AR5K_SREV_PHY_2425) { in ath5k_hw_init()
211 ah->ah_radio = AR5K_RF2425; in ath5k_hw_init()
212 ah->ah_single_chip = true; in ath5k_hw_init()
213 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425; in ath5k_hw_init()
215 ah->ah_phy_revision == AR5K_SREV_PHY_5212B) { in ath5k_hw_init()
216 ah->ah_radio = AR5K_RF5112; in ath5k_hw_init()
217 ah->ah_single_chip = false; in ath5k_hw_init()
218 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B; in ath5k_hw_init()
219 } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) || in ath5k_hw_init()
220 ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) { in ath5k_hw_init()
221 ah->ah_radio = AR5K_RF2316; in ath5k_hw_init()
222 ah->ah_single_chip = true; in ath5k_hw_init()
223 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316; in ath5k_hw_init()
224 } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) || in ath5k_hw_init()
225 ah->ah_phy_revision == AR5K_SREV_PHY_5413) { in ath5k_hw_init()
226 ah->ah_radio = AR5K_RF5413; in ath5k_hw_init()
227 ah->ah_single_chip = true; in ath5k_hw_init()
228 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413; in ath5k_hw_init()
229 } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) || in ath5k_hw_init()
230 ah->ah_phy_revision == AR5K_SREV_PHY_2413) { in ath5k_hw_init()
231 ah->ah_radio = AR5K_RF2413; in ath5k_hw_init()
232 ah->ah_single_chip = true; in ath5k_hw_init()
233 ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413; in ath5k_hw_init()
235 ATH5K_ERR(ah, "Couldn't identify radio revision.\n"); in ath5k_hw_init()
244 ATH5K_ERR(ah, "Device not yet supported.\n"); in ath5k_hw_init()
252 ret = ath5k_hw_post(ah); in ath5k_hw_init()
258 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX); in ath5k_hw_init()
264 ret = ath5k_eeprom_init(ah); in ath5k_hw_init()
266 ATH5K_ERR(ah, "unable to init EEPROM\n"); in ath5k_hw_init()
270 ee = &ah->ah_capabilities.cap_eeprom; in ath5k_hw_init()
275 if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) { in ath5k_hw_init()
276 ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES); in ath5k_hw_init()
277 ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES); in ath5k_hw_init()
280 ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES); in ath5k_hw_init()
281 ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES); in ath5k_hw_init()
287 ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES); in ath5k_hw_init()
289 ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES); in ath5k_hw_init()
292 ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES); in ath5k_hw_init()
295 ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES); in ath5k_hw_init()
296 ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES); in ath5k_hw_init()
297 ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES); in ath5k_hw_init()
300 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET); in ath5k_hw_init()
305 ret = ath5k_hw_set_capabilities(ah); in ath5k_hw_init()
307 ATH5K_ERR(ah, "unable to get device capabilities\n"); in ath5k_hw_init()
312 common->keymax = (ah->ah_version == AR5K_AR5210 ? in ath5k_hw_init()
322 AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE, in ath5k_hw_init()
327 ath5k_hw_set_lladdr(ah, zero_mac); in ath5k_hw_init()
331 ath5k_hw_set_bssid(ah); in ath5k_hw_init()
332 ath5k_hw_set_opmode(ah, ah->opmode); in ath5k_hw_init()
334 ath5k_hw_rfgain_opt_init(ah); in ath5k_hw_init()
336 ath5k_hw_init_nfcal_hist(ah); in ath5k_hw_init()
339 ath5k_hw_set_ledstate(ah, AR5K_LED_INIT); in ath5k_hw_init()
350 void ath5k_hw_deinit(struct ath5k_hw *ah) in ath5k_hw_deinit() argument
352 __set_bit(ATH_STAT_INVALID, ah->status); in ath5k_hw_deinit()
354 kfree(ah->ah_rf_banks); in ath5k_hw_deinit()
356 ath5k_eeprom_detach(ah); in ath5k_hw_deinit()