Lines Matching +full:0 +full:x00070000
32 #define WMI_HOST_RC_DS_FLAG 0x01
33 #define WMI_HOST_RC_CW40_FLAG 0x02
34 #define WMI_HOST_RC_SGI_FLAG 0x04
35 #define WMI_HOST_RC_HT_FLAG 0x08
36 #define WMI_HOST_RC_RTSCTS_FLAG 0x10
37 #define WMI_HOST_RC_TX_STBC_FLAG 0x20
38 #define WMI_HOST_RC_RX_STBC_FLAG 0xC0
40 #define WMI_HOST_RC_WEP_TKIP_FLAG 0x100
41 #define WMI_HOST_RC_TS_FLAG 0x200
42 #define WMI_HOST_RC_UAPSD_FLAG 0x400
44 #define WMI_HT_CAP_ENABLED 0x0001
45 #define WMI_HT_CAP_HT20_SGI 0x0002
46 #define WMI_HT_CAP_DYNAMIC_SMPS 0x0004
47 #define WMI_HT_CAP_TX_STBC 0x0008
49 #define WMI_HT_CAP_RX_STBC 0x0030
51 #define WMI_HT_CAP_LDPC 0x0040
52 #define WMI_HT_CAP_L_SIG_TXOP_PROT 0x0080
53 #define WMI_HT_CAP_MPDU_DENSITY 0x0700
55 #define WMI_HT_CAP_HT40_SGI 0x0800
56 #define WMI_HT_CAP_RX_LDPC 0x1000
57 #define WMI_HT_CAP_TX_LDPC 0x2000
58 #define WMI_HT_CAP_IBF_BFER 0x4000
63 #define WMI_HT_CAP_RX_STBC_1SS 0x0010
64 #define WMI_HT_CAP_RX_STBC_2SS 0x0020
65 #define WMI_HT_CAP_RX_STBC_3SS 0x0030
74 #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK 0x00000003
75 #define WMI_VHT_CAP_RX_LDPC 0x00000010
76 #define WMI_VHT_CAP_SGI_80MHZ 0x00000020
77 #define WMI_VHT_CAP_SGI_160MHZ 0x00000040
78 #define WMI_VHT_CAP_TX_STBC 0x00000080
79 #define WMI_VHT_CAP_RX_STBC_MASK 0x00000300
81 #define WMI_VHT_CAP_SU_BFER 0x00000800
82 #define WMI_VHT_CAP_SU_BFEE 0x00001000
83 #define WMI_VHT_CAP_MAX_CS_ANT_MASK 0x0000E000
85 #define WMI_VHT_CAP_MAX_SND_DIM_MASK 0x00070000
87 #define WMI_VHT_CAP_MU_BFER 0x00080000
88 #define WMI_VHT_CAP_MU_BFEE 0x00100000
89 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP 0x03800000
91 #define WMI_VHT_CAP_RX_FIXED_ANT 0x10000000
92 #define WMI_VHT_CAP_TX_FIXED_ANT 0x20000000
94 #define WMI_VHT_CAP_MAX_MPDU_LEN_11454 0x00000002
99 #define WMI_VHT_CAP_RX_STBC_1SS 0x00000100
100 #define WMI_VHT_CAP_RX_STBC_2SS 0x00000200
101 #define WMI_VHT_CAP_RX_STBC_3SS 0x00000300
120 #define ATH11K_PEER_RX_NSS_160MHZ GENMASK(2, 0)
132 #define ATH11K_11D_INVALID_VDEV_ID 0xFFFF