Lines Matching +full:0 +full:x03c00000
25 #define QCA988X_HOST_INTEREST_ADDRESS 0x00400800
26 #define HOST_INTEREST_MAX_SIZE 0x200
39 u32 hi_app_host_interest; /* 0x00 */
42 u32 hi_failure_state; /* 0x04 */
45 u32 hi_dbglog_hdr; /* 0x08 */
47 u32 hi_unused0c; /* 0x0c */
53 u32 hi_option_flag; /* 0x10 */
59 u32 hi_serial_enable; /* 0x14 */
62 u32 hi_dset_list_head; /* 0x18 */
65 u32 hi_app_start; /* 0x1c */
68 u32 hi_skip_clock_init; /* 0x20 */
69 u32 hi_core_clock_setting; /* 0x24 */
70 u32 hi_cpu_clock_setting; /* 0x28 */
71 u32 hi_system_sleep_setting; /* 0x2c */
72 u32 hi_xtal_control_setting; /* 0x30 */
73 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
74 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
75 u32 hi_ref_voltage_trim_setting; /* 0x3c */
76 u32 hi_clock_info; /* 0x40 */
79 u32 hi_be; /* 0x44 */
81 u32 hi_stack; /* normal stack */ /* 0x48 */
82 u32 hi_err_stack; /* error stack */ /* 0x4c */
83 u32 hi_desired_cpu_speed_hz; /* 0x50 */
86 u32 hi_board_data; /* 0x54 */
90 * 0: board data is not yet initialized.
94 u32 hi_board_data_initialized; /* 0x58 */
96 u32 hi_dset_ram_index_table; /* 0x5c */
98 u32 hi_desired_baud_rate; /* 0x60 */
99 u32 hi_dbglog_config; /* 0x64 */
100 u32 hi_end_ram_reserve_sz; /* 0x68 */
101 u32 hi_mbox_io_block_sz; /* 0x6c */
103 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
104 u32 hi_mbox_isr_yield_limit; /* 0x74 */
106 u32 hi_refclk_hz; /* 0x78 */
107 u32 hi_ext_clk_detected; /* 0x7c */
108 u32 hi_dbg_uart_txpin; /* 0x80 */
109 u32 hi_dbg_uart_rxpin; /* 0x84 */
110 u32 hi_hci_uart_baud; /* 0x88 */
111 u32 hi_hci_uart_pin_assignments; /* 0x8C */
113 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
114 u32 hi_hci_uart_baud_step_val; /* 0x94 */
116 u32 hi_allocram_start; /* 0x98 */
117 u32 hi_allocram_sz; /* 0x9c */
118 u32 hi_hci_bridge_flags; /* 0xa0 */
119 u32 hi_hci_uart_support_pins; /* 0xa4 */
121 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
124 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
128 u32 hi_board_ext_data; /* 0xac */
129 u32 hi_board_ext_data_config; /* 0xb0 */
131 * Bit [0] : valid
139 u32 hi_reset_flag; /* 0xb4 */
141 u32 hi_reset_flag_valid; /* 0xb8 */
142 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
143 /* 0xbc - [31:0]: idle timeout in ms */
145 u32 hi_acs_flags; /* 0xc0 */
146 u32 hi_console_flags; /* 0xc4 */
147 u32 hi_nvram_state; /* 0xc8 */
148 u32 hi_option_flag2; /* 0xcc */
151 u32 hi_sw_version_override; /* 0xd0 */
152 u32 hi_abi_version_override; /* 0xd4 */
158 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
161 u32 hi_test_apps_related; /* 0xdc */
163 u32 hi_ota_testscript; /* 0xe0 */
165 u32 hi_cal_data; /* 0xe4 */
168 u32 hi_pktlog_num_buffers; /* 0xe8 */
171 u32 hi_wow_ext_config; /* 0xec */
172 u32 hi_pwr_save_flags; /* 0xf0 */
175 u32 hi_smps_options; /* 0xf4 */
178 u32 hi_interconnect_state; /* 0xf8 */
181 u32 hi_coex_config; /* 0xfc */
184 u32 hi_early_alloc; /* 0x100 */
191 * Bit 0 -- AP Nart descriptor no swap. When this bit is set
196 u32 hi_fw_swap; /* 0x104 */
199 u32 hi_dynamic_mem_arenas_addr; /* 0x108 */
202 u32 hi_dynamic_mem_allocated; /* 0x10C */
205 u32 hi_dynamic_mem_remaining; /* 0x110 */
208 u32 hi_dynamic_mem_track_max; /* 0x114 */
211 u32 hi_minidump; /* 0x118 */
214 u32 hi_bd_sig_key; /* 0x11c */
222 #define HI_OPTION_TIMER_WAR 0x01
224 #define HI_OPTION_BMI_CRED_LIMIT 0x02
226 #define HI_OPTION_RELAY_DOT11_HDR 0x04
227 /* MAC addr method 0-locally administred 1-globally unique addrs */
228 #define HI_OPTION_MAC_ADDR_METHOD 0x08
230 #define HI_OPTION_FW_BRIDGE 0x10
232 #define HI_OPTION_ENABLE_PROFILE 0x20
234 #define HI_OPTION_DISABLE_DBGLOG 0x40
236 #define HI_OPTION_SKIP_ERA_TRACKING 0x80
238 #define HI_OPTION_PAPRD_DISABLE 0x100
239 #define HI_OPTION_NUM_DEV_LSB 0x200
240 #define HI_OPTION_NUM_DEV_MSB 0x800
241 #define HI_OPTION_DEV_MODE_LSB 0x1000
242 #define HI_OPTION_DEV_MODE_MSB 0x8000000
244 #define HI_OPTION_NO_LFT_STBL 0x10000000
246 #define HI_OPTION_SKIP_REG_SCAN 0x20000000
251 #define HI_OPTION_INIT_REG_SCAN 0x40000000
254 #define HI_OPTION_SKIP_MEMMAP 0x80000000
259 #define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
260 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
261 #define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
262 #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
265 #define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
266 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
267 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
268 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
271 #define HI_OPTION_NUM_DEV_MASK 0x7
272 #define HI_OPTION_NUM_DEV_SHIFT 0x9
275 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04
281 *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0]
285 #define HI_OPTION_FW_MODE_BITS 0x2
286 #define HI_OPTION_FW_MODE_MASK 0x3
287 #define HI_OPTION_FW_MODE_SHIFT 0xC
288 #define HI_OPTION_ALL_FW_MODE_MASK 0xFF
290 #define HI_OPTION_FW_SUBMODE_BITS 0x2
291 #define HI_OPTION_FW_SUBMODE_MASK 0x3
292 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14
293 #define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
294 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
297 #define HI_OPTION_OFFLOAD_AMSDU 0x01
298 #define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
299 #define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature*/
300 #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
301 #define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
303 #define HI_OPTION_RF_KILL_SHIFT 0x2
304 #define HI_OPTION_RF_KILL_MASK 0x1
308 #define HI_RESET_FLAG_PRESERVE_APP_START 0x01
310 #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
312 #define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04
313 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
314 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
315 #define HI_RESET_FLAG_WARM_RESET 0x20
318 #define HI_DESC_IN_FW_BIT 0x01
321 #define HI_RESET_FLAG_IS_VALID 0x12345678
324 #define HI_ACS_FLAGS_ENABLED (1 << 0)
330 #define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET (1 << 0)
342 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400
345 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW 0x800
352 * 2..0 UART ID (0 = Default)
353 * 3 Baud Select (0 = 9600, 1 = 115200)
360 #define HI_CONSOLE_FLAGS_UART_MASK (0x7)
361 #define HI_CONSOLE_FLAGS_UART_SHIFT 0
365 #define HI_SMPS_ALLOW_MASK (0x00000001)
366 #define HI_SMPS_MODE_MASK (0x00000002)
367 #define HI_SMPS_MODE_STATIC (0x00000000)
368 #define HI_SMPS_MODE_DYNAMIC (0x00000002)
369 #define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
370 #define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
372 #define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
374 #define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
376 #define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
384 * 8..0 Size of each WOW pattern (max 511)
395 #define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
397 #define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
398 #define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
399 #define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
424 * [0:3] number of bank assigned to be IRAM
430 * would consider the bits[0:15] are valid and base on that to calculate
438 #define HI_EARLY_ALLOC_MAGIC 0x6d8a
439 #define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
441 #define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
442 #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
452 #define HI_PWR_SAVE_LPL_ENABLED 0x1
454 /*b4-b5 : dev0 LPL type : 0 - none
460 #define HI_PWR_SAVE_LPL_DEV_MASK 0x3
473 #define QCA988X_BOARD_EXT_DATA_SZ 0
476 #define QCA9887_BOARD_EXT_DATA_SZ 0
479 #define QCA6174_BOARD_EXT_DATA_SZ 0
482 #define QCA9377_BOARD_EXT_DATA_SZ 0
485 #define QCA99X0_BOARD_EXT_DATA_SZ 0
489 #define EXT_BOARD_ADDRESS_OFFSET 0x3000
492 #define QCA4019_BOARD_EXT_DATA_SZ 0