Lines Matching refs:MDIO_MMD_VEND1
397 ts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
399 ts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
401 ts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
403 ts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in _nxp_c45_ptp_gettimex64()
428 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_0, in _nxp_c45_ptp_settime64()
430 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_nsec_1, in _nxp_c45_ptp_settime64()
432 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_0, in _nxp_c45_ptp_settime64()
434 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, regmap->vend1_ltc_wr_sec_1, in _nxp_c45_ptp_settime64()
468 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
476 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_adjfine()
523 extts->tv_nsec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
525 extts->tv_nsec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
527 extts->tv_sec = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
529 extts->tv_sec |= phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
531 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, in nxp_c45_get_extts()
542 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_extts_is_valid()
558 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
570 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_extts()
609 phy_write_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_CTRL, in nxp_c45_get_hwtxts()
611 reg = phy_read_mmd(priv->phydev, MDIO_MMD_VEND1, VEND1_EGR_RING_DATA_0); in nxp_c45_get_hwtxts()
627 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S); in tja1120_egress_ts_is_valid()
642 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_END); in tja1120_get_hwtxts()
652 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_get_hwtxts()
659 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, TJA1120_EGRESS_TS_DATA_S, in tja1120_get_hwtxts()
758 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_gpio_config()
827 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
831 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_or_falling()
843 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
847 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
852 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
856 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_set_rising_and_falling()
1057 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1062 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_hwtstamp()
1101 NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 8, 6), },
1103 NXP_C45_REG_FIELD(0x8352, MDIO_MMD_VEND1, 0, 6), },
1105 NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 10, 6), },
1107 NXP_C45_REG_FIELD(0x8353, MDIO_MMD_VEND1, 0, 10), },
1109 NXP_C45_REG_FIELD(0x8350, MDIO_MMD_VEND1, 0, 16) },
1114 NXP_C45_REG_FIELD(0xAFCE, MDIO_MMD_VEND1, 0, 6), },
1116 NXP_C45_REG_FIELD(0xAFCF, MDIO_MMD_VEND1, 0, 6), },
1118 NXP_C45_REG_FIELD(0xAFD0, MDIO_MMD_VEND1, 0, 9), },
1120 NXP_C45_REG_FIELD(0xAFD1, MDIO_MMD_VEND1, 0, 9), },
1125 NXP_C45_REG_FIELD(0x8351, MDIO_MMD_VEND1, 0, 14) },
1127 NXP_C45_REG_FIELD(0xACA1, MDIO_MMD_VEND1, 0, 8), },
1129 NXP_C45_REG_FIELD(0xACA0, MDIO_MMD_VEND1, 0, 16), },
1131 NXP_C45_REG_FIELD(0xACA3, MDIO_MMD_VEND1, 0, 8), },
1133 NXP_C45_REG_FIELD(0xACA2, MDIO_MMD_VEND1, 0, 16), },
1135 NXP_C45_REG_FIELD(0xACA5, MDIO_MMD_VEND1, 0, 8), },
1137 NXP_C45_REG_FIELD(0xACA4, MDIO_MMD_VEND1, 0, 16), },
1139 NXP_C45_REG_FIELD(0xACA7, MDIO_MMD_VEND1, 0, 8), },
1141 NXP_C45_REG_FIELD(0xACA6, MDIO_MMD_VEND1, 0, 16), },
1198 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_config_enable()
1203 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_CONTROL, in nxp_c45_config_enable()
1205 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_config_enable()
1207 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_INFRA_CONTROL, in nxp_c45_config_enable()
1215 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONTROL, in nxp_c45_start_op()
1222 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1225 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_config_intr()
1234 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_ALWAYS_ACCESSIBLE, in tja1103_config_intr()
1247 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1251 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_config_intr()
1268 irq = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_STATUS); in nxp_c45_handle_interrupt()
1270 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_IRQ_ACK, in nxp_c45_handle_interrupt()
1283 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_handle_interrupt()
1300 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONTROL, in nxp_c45_soft_reset()
1305 return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, in nxp_c45_soft_reset()
1315 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_start()
1317 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_start()
1356 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, regmap->cable_test, in nxp_c45_cable_test_get_status()
1358 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_cable_test_get_status()
1368 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_SIGNAL_QUALITY); in nxp_c45_get_sqi()
1383 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1385 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_link_change_notify()
1414 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_LINK_DROP_COUNTER, in nxp_c45_counters_enable()
1424 phy_write_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_ptp_init()
1445 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, ID_ENABLE); in nxp_c45_disable_delays()
1446 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, ID_ENABLE); in nxp_c45_disable_delays()
1459 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1462 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TXID, in nxp_c45_set_delays()
1469 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1472 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RXID, in nxp_c45_set_delays()
1521 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_ABILITIES); in nxp_c45_set_phy_mode()
1530 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1541 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1554 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1562 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1570 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1578 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_MII_BASIC_CONFIG, in nxp_c45_set_phy_mode()
1603 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F8, 1); in nxp_c45_config_init()
1604 phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x01F9, 2); in nxp_c45_config_init()
1606 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PHY_CONFIG, in nxp_c45_config_init()
1648 ptp_ability = phy_read_mmd(phydev, MDIO_MMD_VEND1, in nxp_c45_probe()
1686 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_PREAMBLE_COUNT, in tja1103_counters_enable()
1688 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_PREAMBLE_COUNT, in tja1103_counters_enable()
1690 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_IPG_LENGTH, in tja1103_counters_enable()
1692 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_TX_IPG_LENGTH, in tja1103_counters_enable()
1698 phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RX_TS_INSRT_CTRL, in tja1103_ptp_init()
1700 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in tja1103_ptp_init()
1707 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1711 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1103_ptp_enable()
1721 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1724 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1103_nmi_handler()
1735 NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 3, 1),
1737 NXP_C45_REG_FIELD(0x1102, MDIO_MMD_VEND1, 2, 1),
1739 NXP_C45_REG_FIELD(0x1115, MDIO_MMD_VEND1, 0, 1),
1741 NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 2, 1),
1743 NXP_C45_REG_FIELD(0x1105, MDIO_MMD_VEND1, 0, 1),
1755 NXP_C45_REG_FIELD(0x1131, MDIO_MMD_VEND1, 0, 1),
1757 NXP_C45_REG_FIELD(0x1132, MDIO_MMD_VEND1, 0, 1),
1759 NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 0, 8),
1761 NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 8, 4),
1763 NXP_C45_REG_FIELD(0x114F, MDIO_MMD_VEND1, 0, 16),
1765 NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 14, 2),
1767 NXP_C45_REG_FIELD(0x114E, MDIO_MMD_VEND1, 12, 3),
1769 NXP_C45_REG_FIELD(0x1150, MDIO_MMD_VEND1, 0, 16),
1771 NXP_C45_REG_FIELD(0x1151, MDIO_MMD_VEND1, 0, 14),
1779 NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 13, 1),
1781 NXP_C45_REG_FIELD(0x8330, MDIO_MMD_VEND1, 0, 3),
1801 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_SYMBOL_ERROR_CNT_XTD, in tja1120_counters_enable()
1803 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_STATUS, in tja1120_counters_enable()
1805 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_MONITOR_CONFIG, in tja1120_counters_enable()
1811 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_RX_TS_INSRT_CTRL, in tja1120_ptp_init()
1813 phy_write_mmd(phydev, MDIO_MMD_VEND1, TJA1120_VEND1_EXT_TS_MODE, in tja1120_ptp_init()
1815 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_DEVICE_CONFIG, in tja1120_ptp_init()
1822 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1826 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, in tja1120_ptp_enable()
1836 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()
1839 phy_write_mmd(phydev, MDIO_MMD_VEND1, in tja1120_nmi_handler()
1850 NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 4, 1),
1852 NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 5, 1),
1854 NXP_C45_REG_FIELD(0x1006, MDIO_MMD_VEND1, 2, 1),
1856 NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 1, 1),
1858 NXP_C45_REG_FIELD(0x1000, MDIO_MMD_VEND1, 2, 1),
1870 NXP_C45_REG_FIELD(0x900A, MDIO_MMD_VEND1, 1, 1),
1872 NXP_C45_REG_FIELD(0x900C, MDIO_MMD_VEND1, 1, 1),
1874 NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 8, 8),
1876 NXP_C45_REG_FIELD(0x9061, MDIO_MMD_VEND1, 4, 4),
1878 NXP_C45_REG_FIELD(0x9062, MDIO_MMD_VEND1, 0, 16),
1880 NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 0, 2),
1882 NXP_C45_REG_FIELD(0x9065, MDIO_MMD_VEND1, 2, 3),
1884 NXP_C45_REG_FIELD(0x9063, MDIO_MMD_VEND1, 0, 16),
1886 NXP_C45_REG_FIELD(0x9064, MDIO_MMD_VEND1, 0, 14),
1894 NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 15, 1),
1896 NXP_C45_REG_FIELD(0x8361, MDIO_MMD_VEND1, 0, 3),