Lines Matching refs:phy_write_mmd
768 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A); in ksz8061_config_init()
956 return phy_write_mmd(phydev, 2, reg, newval); in ksz9031_of_load_skew_values()
964 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, in ksz9031_center_flp_timing()
969 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, in ksz9031_center_flp_timing()
985 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD, in ksz9031_enable_edpd()
1023 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW, in ksz9031_config_rgmii_delay()
1029 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1037 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW, in ksz9031_config_rgmii_delay()
1045 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW, in ksz9031_config_rgmii_delay()
1198 return phy_write_mmd(phydev, 2, reg, newval); in ksz9131_of_load_skew_values()
1842 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val); in ksz9477_config_init()
3348 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3350 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3352 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3354 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3356 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3358 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG, in lan8841_config_init()
3362 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3365 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3375 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3378 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3389 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG, in lan8841_config_init()
3394 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, in lan8841_config_init()
3396 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG, in lan8841_config_init()
3518 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, in lan8841_gpio_process_cap()
3542 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0); in lan8841_gpio_process_cap()
3736 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg); in lan8841_hwtstamp()
3737 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg); in lan8841_hwtstamp()
3741 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable); in lan8841_hwtstamp()
3742 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable); in lan8841_hwtstamp()
3819 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event), in lan8841_ptp_set_target()
3824 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event), in lan8841_ptp_set_target()
3829 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff, in lan8841_ptp_set_target()
3834 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event), in lan8841_ptp_set_target()
3858 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event), in lan8841_ptp_set_reload()
3863 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event), in lan8841_ptp_set_reload()
3868 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff, in lan8841_ptp_set_reload()
3873 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event), in lan8841_ptp_set_reload()
3895 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec)); in lan8841_ptp_settime64()
3896 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec)); in lan8841_ptp_settime64()
3897 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff); in lan8841_ptp_settime64()
3898 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec)); in lan8841_ptp_settime64()
3899 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff); in lan8841_ptp_settime64()
3902 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_settime64()
3932 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_gettime64()
3961 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_getseconds()
4037 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec); in lan8841_ptp_adjtime()
4038 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI, in lan8841_ptp_adjtime()
4040 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_adjtime()
4045 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, in lan8841_ptp_adjtime()
4047 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI, in lan8841_ptp_adjtime()
4049 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL, in lan8841_ptp_adjtime()
4087 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI, in lan8841_ptp_adjfine()
4090 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate)); in lan8841_ptp_adjfine()
4396 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp); in lan8841_ptp_extts_on()