24 #define DP83822_DEVADDR		0x1f  macro
139 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA1,  in dp83822_set_wol()
141 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA2,  in dp83822_set_wol()
143 		phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_DA3,  in dp83822_set_wol()
146 		value = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
154 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
157 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
160 			phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
174 		return phy_write_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
177 		return phy_clear_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_set_wol()
191 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_get_wol()
197 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
202 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
207 		sopass_val = phy_read_mmd(phydev, DP83822_DEVADDR,  in dp83822_get_wol()
329 	return phy_clear_bits_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG,  in dp8382x_disable_wol()
406 			err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
412 		phy_set_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
415 		phy_clear_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
467 			err = phy_set_bits_mmd(phydev, DP83822_DEVADDR,  in dp83822_config_init()
525 	val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);  in dp83822_read_straps()
574 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_suspend()
588 	value = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG);  in dp83822_resume()
590 	phy_write_mmd(phydev, DP83822_DEVADDR, MII_DP83822_WOL_CFG, value |  in dp83822_resume()