Lines Matching +full:0 +full:- +full:31
1 // SPDX-License-Identifier: GPL-2.0
11 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0),
33 /* Bits 25-29 reserved */
35 [GEN_QMB_0_DYNAMIC_ASIZE] = BIT(31),
38 REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c);
41 [CLKON_RX] = BIT(0),
72 [DRBIP] = BIT(31),
75 REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044);
78 [ROUTE_DIS] = BIT(0),
83 /* Bits 22-23 reserved */
85 /* Bits 25-31 reserved */
88 REG_FIELDS(ROUTE, route, 0x00000048);
91 [MEM_SIZE] = GENMASK(15, 0),
92 [MEM_BADDR] = GENMASK(31, 16),
95 REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054);
98 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0),
100 /* Bits 8-31 reserved */
103 REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074);
106 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0),
108 /* Bits 8-15 reserved */
110 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24),
113 REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078);
116 [IPV6_ROUTER_HASH] = BIT(0),
117 /* Bits 1-3 reserved */
119 /* Bits 5-7 reserved */
121 /* Bits 9-11 reserved */
123 /* Bits 13-31 reserved */
126 REG_FIELDS(FILT_ROUT_HASH_EN, filt_rout_hash_en, 0x0000148);
129 [IPV6_ROUTER_HASH] = BIT(0),
130 /* Bits 1-3 reserved */
132 /* Bits 5-7 reserved */
134 /* Bits 9-11 reserved */
136 /* Bits 13-31 reserved */
139 REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c);
141 /* Valid bits defined by ipa->available */
142 REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004);
145 [IPA_BASE_ADDR] = GENMASK(17, 0),
146 /* Bits 18-31 reserved */
150 REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8);
152 /* Valid bits defined by ipa->available */
153 REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004);
156 /* Bits 0-1 reserved */
165 /* Bits 19-31 reserved */
168 REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc);
171 [MAX_PIPES] = GENMASK(3, 0),
172 /* Bits 4-7 reserved */
174 /* Bits 13-15 reserved */
176 /* Bits 21-23 reserved */
178 /* Bits 28-31 reserved */
181 REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210);
184 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0),
186 /* Bits 17-31 reserved */
189 REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240);
192 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0),
193 /* Bits 5-6 reserved */
196 /* Bits 13-15 reserved */
198 /* Bits 21-31 reserved */
201 REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c);
204 [DIV_VALUE] = GENMASK(8, 0),
205 /* Bits 9-30 reserved */
206 [DIV_ENABLE] = BIT(31),
209 REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250);
212 [PULSE_GRAN_0] = GENMASK(2, 0),
217 REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254);
220 [X_MIN_LIM] = GENMASK(5, 0),
221 /* Bits 6-7 reserved */
223 /* Bits 14-15 reserved */
225 /* Bits 22-23 reserved */
227 /* Bits 30-31 reserved */
231 0x00000400, 0x0020);
234 [X_MIN_LIM] = GENMASK(5, 0),
235 /* Bits 6-7 reserved */
237 /* Bits 14-15 reserved */
239 /* Bits 22-23 reserved */
241 /* Bits 30-31 reserved */
245 0x00000404, 0x0020);
248 [X_MIN_LIM] = GENMASK(5, 0),
249 /* Bits 6-7 reserved */
251 /* Bits 14-15 reserved */
253 /* Bits 22-23 reserved */
255 /* Bits 30-31 reserved */
259 0x00000500, 0x0020);
262 [X_MIN_LIM] = GENMASK(5, 0),
263 /* Bits 6-7 reserved */
265 /* Bits 14-15 reserved */
267 /* Bits 22-23 reserved */
269 /* Bits 30-31 reserved */
273 0x00000504, 0x0020);
276 [FRAG_OFFLOAD_EN] = BIT(0),
281 /* Bits 9-31 reserved */
284 REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070);
287 [NAT_EN] = GENMASK(1, 0),
288 /* Bits 2-31 reserved */
291 REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070);
294 [HDR_LEN] = GENMASK(5, 0),
302 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30),
305 REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070);
308 [HDR_ENDIANNESS] = BIT(0),
314 /* Bits 14-15 reserved */
318 /* Bits 22-31 reserved */
321 REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070);
324 0x00000818, 0x0070);
327 [ENDP_MODE] = GENMASK(2, 0),
330 /* Bits 9-11 reserved */
335 /* Bit 31 reserved */
338 REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070);
341 [AGGR_EN] = GENMASK(1, 0),
352 /* Bits 28-31 reserved */
355 REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070);
358 [HOL_BLOCK_EN] = BIT(0),
359 /* Bits 1-31 reserved */
363 0x0000082c, 0x0070);
366 [TIMER_LIMIT] = GENMASK(4, 0),
367 /* Bits 5-7 reserved */
369 /* Bits 9-31 reserved */
373 0x00000830, 0x0070);
376 [DEAGGR_HDR_LEN] = GENMASK(5, 0),
382 [MAX_PACKET_LEN] = GENMASK(31, 16),
385 REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070);
388 [ENDP_RSRC_GRP] = GENMASK(1, 0),
389 /* Bits 2-31 reserved */
392 REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070);
395 [SEQ_TYPE] = GENMASK(7, 0),
396 /* Bits 8-31 reserved */
399 REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070);
402 [STATUS_EN] = BIT(0),
404 /* Bits 6-8 reserved */
406 /* Bits 10-31 reserved */
409 REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070);
412 [FILTER_HASH_MSK_SRC_ID] = BIT(0),
419 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0),
420 /* Bits 7-15 reserved */
429 /* Bits 23-31 reserved */
433 0x0000085c, 0x0070);
436 REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00004008 + 0x1000 * GSI_EE_AP);
439 REG(IPA_IRQ_EN, ipa_irq_en, 0x0000400c + 0x1000 * GSI_EE_AP);
442 REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00004010 + 0x1000 * GSI_EE_AP);
445 [UC_INTR] = BIT(0),
446 /* Bits 1-31 reserved */
449 REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000401c + 0x1000 * GSI_EE_AP);
451 /* Valid bits defined by ipa->available */
453 0x00004030 + 0x1000 * GSI_EE_AP, 0x0004);
455 /* Valid bits defined by ipa->available */
457 0x00004034 + 0x1000 * GSI_EE_AP, 0x0004);
459 /* Valid bits defined by ipa->available */
461 0x00004038 + 0x1000 * GSI_EE_AP, 0x0004);