Lines Matching +full:5 +full:a
21 * Device Tree. Each register has a specified offset within that space,
23 * has a unique identifer, taken from the ipa_reg_id enumerated type.
26 * Certain "parameterized" register types are duplicated for a number of
30 * ID multiplied and a "stride" value for the register. Similarly, some
32 * this case, the stride is multiplied by a member of the gsi_ee_id
37 * (for parameterized registers) a non-zero stride value. Not all versions
38 * of IPA define all registers. The offset for a register is returned by
43 * such a register has a unique identifier (from an enumerated type).
44 * The position and width of the fields in a register are defined by
47 * argument. To encode a value to be represented in a register field,
49 * a value encoded in a register field, the field ID is passed to
51 * can be used to either encode the bit value, or to generate a mask
67 IPA_BCR, /* Not IPA v4.5+ */
70 COUNTER_CFG, /* Not IPA v4.5+ */
71 IPA_TX_CFG, /* IPA v3.5+ */
72 FLAVOR_0, /* IPA v3.5+ */
73 IDLE_INDICATION_CFG, /* IPA v3.5+ */
74 QTIME_TIMESTAMP_CFG, /* IPA v4.5+ */
75 TIMERS_XO_CLK_DIV_CFG, /* IPA v4.5+ */
76 TIMERS_PULSE_GRAN_CFG, /* IPA v4.5+ */
79 SRC_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
80 SRC_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
83 DST_RSRC_GRP_45_RSRC_TYPE, /* Not IPA v3.5+; IPA v4.5, IPA v5.0 */
84 DST_RSRC_GRP_67_RSRC_TYPE, /* Not IPA v3.5+; IPA v5.0 */
120 IPA_DCMP_FAST_CLK_EN, /* Not IPA v4.5+ */
139 FULL_FLUSH_WAIT_RS_CLOSURE_EN, /* IPA v4.5+ */
161 CLKON_DCMP, /* IPA v4.5+ */
162 NTF_TX_CMDQS, /* IPA v3.5+ */
163 CLKON_TX_0, /* IPA v3.5+ */
164 CLKON_TX_1, /* IPA v3.5+ */
174 DPL_FIFO, /* IPA v4.5+ */
229 BCR_DUAL_TX = 0x5, /* IPA v3.5+ */
230 BCR_ENABLE_FILTER_DATA_CACHE = 0x6, /* IPA v3.5+ */
231 BCR_NOTIF_PRIORITY_OVER_ZLT = 0x7, /* IPA v3.5+ */
232 BCR_FILTER_PREFETCH_EN = 0x8, /* IPA v3.5+ */
233 BCR_ROUTER_PREFETCH_EN = 0x9, /* IPA v3.5+ */
243 EOT_COAL_GRANULARITY, /* Not v3.5+ */
258 DUAL_TX_ENABLE, /* v4.5+ */
259 SSPND_PA_NO_START_STATE, /* v4,2+, not v4.5 */
337 IPA_CS_OFFLOAD_UL /* TX */ = 0x1, /* Not IPA v4.5+ */
338 IPA_CS_OFFLOAD_DL /* RX */ = 0x2, /* Not IPA v4.5+ */
339 IPA_CS_OFFLOAD_INLINE /* TX and RX */ = 0x1, /* IPA v4.5+ */
364 HDR_METADATA_REG_VALID, /* Not v4.5+ */
365 HDR_LEN_MSB, /* v4.5+ */
366 HDR_OFST_METADATA_MSB, /* v4.5+ */
377 HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB, /* v4.5+ */
378 HDR_OFST_PKT_SIZE_MSB, /* v4.5+ */
379 HDR_ADDITIONAL_CONST_LEN_MSB, /* v4.5+ */
387 DCPH_ENABLE, /* v4.5+ */
392 HDR_FTCH_DISABLE, /* v4.5+ */
442 TIMER_BASE_VALUE, /* Not v4.5+ */
444 TIMER_LIMIT, /* v4.5+ */
445 TIMER_GRAN_SEL, /* v4.5+ */
466 SEQ_REP_TYPE, /* Not v4.5+ */
480 * passes a packet takes through the IPA pipeline. The last pass through can
515 STATUS_LOCATION, /* Not v4.5+ */
591 /* The next bit is not present for IPA v3.5+ */
613 /* The next bit is not present for IPA v4.5+ */
618 /* The next bit is present for IPA v4.5+ */