188 	writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP,  in rr_init_one()
231 		writel(HALT_NIC, &rr->regs->HostCtrl);  in rr_remove_one()
272 	writel(*(u32*)(cmd), &regs->CmdRing[idx]);  in rr_issue_cmd()
300 	writel(0x01000000, &regs->TX_state);  in rr_reset()
301 	writel(0xff800000, &regs->RX_state);  in rr_reset()
302 	writel(0, &regs->AssistState);  in rr_reset()
303 	writel(CLEAR_INTA, &regs->LocalCtrl);  in rr_reset()
304 	writel(0x01, &regs->BrkPt);  in rr_reset()
305 	writel(0, &regs->Timer);  in rr_reset()
306 	writel(0, &regs->TimerRef);  in rr_reset()
307 	writel(RESET_DMA, &regs->DmaReadState);  in rr_reset()
308 	writel(RESET_DMA, &regs->DmaWriteState);  in rr_reset()
309 	writel(0, &regs->DmaWriteHostHi);  in rr_reset()
310 	writel(0, &regs->DmaWriteHostLo);  in rr_reset()
311 	writel(0, &regs->DmaReadHostHi);  in rr_reset()
312 	writel(0, &regs->DmaReadHostLo);  in rr_reset()
313 	writel(0, &regs->DmaReadLen);  in rr_reset()
314 	writel(0, &regs->DmaWriteLen);  in rr_reset()
315 	writel(0, &regs->DmaWriteLcl);  in rr_reset()
316 	writel(0, &regs->DmaWriteIPchecksum);  in rr_reset()
317 	writel(0, &regs->DmaReadLcl);  in rr_reset()
318 	writel(0, &regs->DmaReadIPchecksum);  in rr_reset()
319 	writel(0, &regs->PciState);  in rr_reset()
321 	writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode);  in rr_reset()
323 	writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode);  in rr_reset()
325 	writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode);  in rr_reset()
332 	writel(0xdf000, &regs->RxBase);  in rr_reset()
333 	writel(0xdf000, &regs->RxPrd);  in rr_reset()
334 	writel(0xdf000, &regs->RxCon);  in rr_reset()
335 	writel(0xce000, &regs->TxBase);  in rr_reset()
336 	writel(0xce000, &regs->TxPrd);  in rr_reset()
337 	writel(0xce000, &regs->TxCon);  in rr_reset()
338 	writel(0, &regs->RxIndPro);  in rr_reset()
339 	writel(0, &regs->RxIndCon);  in rr_reset()
340 	writel(0, &regs->RxIndRef);  in rr_reset()
341 	writel(0, &regs->TxIndPro);  in rr_reset()
342 	writel(0, &regs->TxIndCon);  in rr_reset()
343 	writel(0, &regs->TxIndRef);  in rr_reset()
344 	writel(0xcc000, &regs->pad10[0]);  in rr_reset()
345 	writel(0, &regs->DrCmndPro);  in rr_reset()
346 	writel(0, &regs->DrCmndCon);  in rr_reset()
347 	writel(0, &regs->DwCmndPro);  in rr_reset()
348 	writel(0, &regs->DwCmndCon);  in rr_reset()
349 	writel(0, &regs->DwCmndRef);  in rr_reset()
350 	writel(0, &regs->DrDataPro);  in rr_reset()
351 	writel(0, &regs->DrDataCon);  in rr_reset()
352 	writel(0, &regs->DrDataRef);  in rr_reset()
353 	writel(0, &regs->DwDataPro);  in rr_reset()
354 	writel(0, &regs->DwDataCon);  in rr_reset()
355 	writel(0, &regs->DwDataRef);  in rr_reset()
358 	writel(0xffffffff, &regs->MbEvent);  in rr_reset()
359 	writel(0, &regs->Event);  in rr_reset()
361 	writel(0, &regs->TxPi);  in rr_reset()
362 	writel(0, &regs->IpRxPi);  in rr_reset()
364 	writel(0, &regs->EvtCon);  in rr_reset()
365 	writel(0, &regs->EvtPrd);  in rr_reset()
370 		writel(0, &regs->CmdRing[i]);  in rr_reset()
375 	writel(RBURST_64|WBURST_64, &regs->PciState);  in rr_reset()
386 	writel(start_pc + 0x800, &regs->Pc);  in rr_reset()
390 	writel(start_pc, &regs->Pc);  in rr_reset()
409 	writel(0, &regs->ExtIo);  in rr_read_eeprom()
411 	writel(0, &regs->LocalCtrl);  in rr_read_eeprom()
413 	writel(host | HALT_NIC, &regs->HostCtrl);  in rr_read_eeprom()
417 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);  in rr_read_eeprom()
423 	writel(host, &regs->HostCtrl);  in rr_read_eeprom()
424 	writel(misc, &regs->LocalCtrl);  in rr_read_eeprom()
425 	writel(io, &regs->ExtIo);  in rr_read_eeprom()
461 	writel(0, &regs->ExtIo);  in write_eeprom()
463 	writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl);  in write_eeprom()
467 		writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase);  in write_eeprom()
475 			writel(data, &regs->WinData);  in write_eeprom()
496 	writel(misc, &regs->LocalCtrl);  in write_eeprom()
497 	writel(io, &regs->ExtIo);  in write_eeprom()
573 	writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl);  in rr_init1()
599 		writel(0, &regs->CmdRing[i]);  in rr_init1()
626 	writel(0x5000, &regs->ConRetry);  in rr_init1()
627 	writel(0x100, &regs->ConRetryTmr);  in rr_init1()
628 	writel(0x500000, &regs->ConTmout);  in rr_init1()
629  	writel(0x60, &regs->IntrTmr);  in rr_init1()
630 	writel(0x500000, &regs->TxDataMvTimeout);  in rr_init1()
631 	writel(0x200000, &regs->RxDataMvTimeout);  in rr_init1()
632  	writel(0x80, &regs->WriteDmaThresh);  in rr_init1()
633  	writel(0x80, &regs->ReadDmaThresh);  in rr_init1()
639 	writel(hostctrl, &regs->HostCtrl);  in rr_init1()
744 			writel(RX_RING_ENTRIES - 1, &regs->IpRxPi);  in rr_handle_event()
764 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
771 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
795 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
807 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
814 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
821 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
828 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
882 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
889 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
896 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_handle_event()
1014 			writel(index, &regs->IpRxPi);  in rx_int()
1102 	writel(eidx, &regs->EvtCon);  in rr_interrupt()
1173 			writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT,  in rr_timer()
1220 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);  in rr_open()
1246 	writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl);  in rr_open()
1353 		writel(tmp, &regs->HostCtrl);  in rr_close()
1363 	writel(0, &regs->TxPi);  in rr_close()
1364 	writel(0, &regs->IpRxPi);  in rr_close()
1366 	writel(0, &regs->EvtCon);  in rr_close()
1367 	writel(0, &regs->EvtPrd);  in rr_close()
1370 		writel(0, &regs->CmdRing[i]);  in rr_close()
1451 	writel(txctrl->pi, &regs->TxPi);  in rr_start_xmit()
1493 	writel(0, &regs->LocalCtrl);  in rr_load_firmware()
1495 	writel(0, &regs->EvtPrd);  in rr_load_firmware()
1496 	writel(0, &regs->RxPrd);  in rr_load_firmware()
1497 	writel(0, &regs->TxPrd);  in rr_load_firmware()
1505 	writel(0, &regs->ExtIo);  in rr_load_firmware()
1509 		writel(i * 4, &regs->WinBase);  in rr_load_firmware()
1511 		writel(0, &regs->WinData);  in rr_load_firmware()
1514 	writel(io, &regs->ExtIo);  in rr_load_firmware()
1560 			writel(sptr, &regs->WinBase);  in rr_load_firmware()
1562 			writel(tmp, &regs->WinData);  in rr_load_firmware()
1570 	writel(localctrl, &regs->LocalCtrl);  in rr_load_firmware()