Lines Matching +full:0 +full:x1100
22 #define MAC_TCR 0x0000
23 #define MAC_RCR 0x0004
24 #define MAC_PFR 0x0008
25 #define MAC_HTR0 0x0010
26 #define MAC_VLANTR 0x0050
27 #define MAC_VLANHTR 0x0058
28 #define MAC_VLANIR 0x0060
29 #define MAC_Q0TFCR 0x0070
30 #define MAC_RFCR 0x0090
31 #define MAC_RQC0R 0x00a0
32 #define MAC_RQC1R 0x00a4
33 #define MAC_RQC2R 0x00a8
34 #define MAC_RQC3R 0x00ac
35 #define MAC_ISR 0x00b0
36 #define MAC_IER 0x00b4
37 #define MAC_VR 0x0110
38 #define MAC_HWF0R 0x011c
39 #define MAC_HWF1R 0x0120
40 #define MAC_HWF2R 0x0124
41 #define MAC_MACA0HR 0x0300
42 #define MAC_MACA0LR 0x0304
43 #define MAC_MACA1HR 0x0308
44 #define MAC_MACA1LR 0x030c
45 #define MAC_RSSCR 0x0c80
46 #define MAC_RSSAR 0x0c88
47 #define MAC_RSSDR 0x0c8c
100 #define MAC_HWF1R_RXFIFOSIZE_POS 0
114 #define MAC_HWF2R_RXQCNT_POS 0
140 #define MAC_PFR_PR_POS 0
162 #define MAC_RCR_RE_POS 0
166 #define MAC_RFCR_RFE_POS 0
170 #define MAC_RQC0R_RXQ0EN_POS 0
176 #define MAC_RSSAR_OB_POS 0
182 #define MAC_RSSCR_RSSE_POS 0
188 #define MAC_RSSDR_DMCH_POS 0
192 #define MAC_TCR_TE_POS 0
194 #define MAC_VLANHTR_VLHT_POS 0
212 #define MAC_VLANTR_VL_POS 0
220 #define MAC_VR_SNPSVER_POS 0
226 #define MMC_CR 0x0800
227 #define MMC_RISR 0x0804
228 #define MMC_TISR 0x0808
229 #define MMC_RIER 0x080c
230 #define MMC_TIER 0x0810
231 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
232 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
233 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
234 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
235 #define MMC_TX64OCTETS_GB_LO 0x0834
236 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
237 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
238 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
239 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
240 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
241 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
242 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
243 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
244 #define MMC_TXUNDERFLOWERROR_LO 0x087c
245 #define MMC_TXOCTETCOUNT_G_LO 0x0884
246 #define MMC_TXFRAMECOUNT_G_LO 0x088c
247 #define MMC_TXPAUSEFRAMES_LO 0x0894
248 #define MMC_TXVLANFRAMES_G_LO 0x089c
249 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
250 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
251 #define MMC_RXOCTETCOUNT_G_LO 0x0910
252 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
253 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
254 #define MMC_RXCRCERROR_LO 0x0928
255 #define MMC_RXRUNTERROR 0x0930
256 #define MMC_RXJABBERERROR 0x0934
257 #define MMC_RXUNDERSIZE_G 0x0938
258 #define MMC_RXOVERSIZE_G 0x093c
259 #define MMC_RX64OCTETS_GB_LO 0x0940
260 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
261 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
262 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
263 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
264 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
265 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
266 #define MMC_RXLENGTHERROR_LO 0x0978
267 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
268 #define MMC_RXPAUSEFRAMES_LO 0x0988
269 #define MMC_RXFIFOOVERFLOW_LO 0x0990
270 #define MMC_RXVLANFRAMES_GB_LO 0x0998
271 #define MMC_RXWATCHDOGERROR 0x09a0
274 #define MMC_CR_CR_POS 0
284 #define MMC_RIER_ALL_INTERRUPTS_POS 0
286 #define MMC_RISR_RXFRAMECOUNT_GB_POS 0
332 #define MMC_TIER_ALL_INTERRUPTS_POS 0
334 #define MMC_TISR_TXOCTETCOUNT_GB_POS 0
372 #define MTL_OMR 0x1000
373 #define MTL_FDDR 0x1010
374 #define MTL_RQDCM0R 0x1030
387 * that begin at 0x1100. Each subsequent queue has registers that
388 * are accessed using an offset of 0x80 from the previous queue.
390 #define MTL_Q_BASE 0x1100
391 #define MTL_Q_INC 0x80
393 #define MTL_Q_TQOMR 0x00
394 #define MTL_Q_RQOMR 0x40
395 #define MTL_Q_RQDR 0x48
396 #define MTL_Q_RQFCR 0x50
397 #define MTL_Q_IER 0x70
398 #define MTL_Q_ISR 0x74
419 #define MTL_Q_RQOMR_RTC_POS 0
421 #define MTL_Q_TQOMR_FTQ_POS 0
435 #define MTL_RSF_DISABLE 0x00
436 #define MTL_RSF_ENABLE 0x01
437 #define MTL_TSF_DISABLE 0x00
438 #define MTL_TSF_ENABLE 0x01
440 #define MTL_RX_THRESHOLD_64 0x00
441 #define MTL_RX_THRESHOLD_96 0x02
442 #define MTL_RX_THRESHOLD_128 0x03
443 #define MTL_TX_THRESHOLD_64 0x00
444 #define MTL_TX_THRESHOLD_96 0x02
445 #define MTL_TX_THRESHOLD_128 0x03
446 #define MTL_TX_THRESHOLD_192 0x04
447 #define MTL_TX_THRESHOLD_256 0x05
448 #define MTL_TX_THRESHOLD_384 0x06
449 #define MTL_TX_THRESHOLD_512 0x07
451 #define MTL_ETSALG_WRR 0x00
452 #define MTL_ETSALG_WFQ 0x01
453 #define MTL_ETSALG_DWRR 0x02
454 #define MTL_RAA_SP 0x00
455 #define MTL_RAA_WSP 0x01
457 #define MTL_Q_DISABLED 0x00
458 #define MTL_Q_ENABLED 0x02
460 #define MTL_RQDCM0R_Q0MDMACH 0x0
461 #define MTL_RQDCM0R_Q1MDMACH 0x00000100
462 #define MTL_RQDCM0R_Q2MDMACH 0x00020000
463 #define MTL_RQDCM0R_Q3MDMACH 0x03000000
464 #define MTL_RQDCM1R_Q4MDMACH 0x00000004
465 #define MTL_RQDCM1R_Q5MDMACH 0x00000500
466 #define MTL_RQDCM1R_Q6MDMACH 0x00060000
467 #define MTL_RQDCM1R_Q7MDMACH 0x07000000
468 #define MTL_RQDCM2R_Q8MDMACH 0x00000008
469 #define MTL_RQDCM2R_Q9MDMACH 0x00000900
470 #define MTL_RQDCM2R_Q10MDMACH 0x000A0000
471 #define MTL_RQDCM2R_Q11MDMACH 0x0B000000
475 * that begin at 0x1100. Each subsequent queue has registers that
476 * are accessed using an offset of 0x80 from the previous queue.
481 #define MTL_TC_ETSCR 0x10
482 #define MTL_TC_ETSSR 0x14
483 #define MTL_TC_QWR 0x18
486 #define MTL_TC_ETSCR_TSA_POS 0
488 #define MTL_TC_QWR_QW_POS 0
492 #define MTL_TSA_SP 0x00
493 #define MTL_TSA_ETS 0x02
496 #define DMA_MR 0x3000
497 #define DMA_SBMR 0x3004
498 #define DMA_ISR 0x3008
499 #define DMA_DSR0 0x3020
500 #define DMA_DSR1 0x3024
507 #define DMA_MR_SWR_POS 0
517 #define DMA_SBMR_UNDEF_POS 0
529 #define DMA_TPS_STOPPED 0x00
530 #define DMA_TPS_SUSPENDED 0x06
534 * that begin at 0x3100. Each subsequent channel has registers that
535 * are accessed using an offset of 0x80 from the previous channel.
537 #define DMA_CH_BASE 0x3100
538 #define DMA_CH_INC 0x80
540 #define DMA_CH_CR 0x00
541 #define DMA_CH_TCR 0x04
542 #define DMA_CH_RCR 0x08
543 #define DMA_CH_TDLR_HI 0x10
544 #define DMA_CH_TDLR_LO 0x14
545 #define DMA_CH_RDLR_HI 0x18
546 #define DMA_CH_RDLR_LO 0x1c
547 #define DMA_CH_TDTR_LO 0x24
548 #define DMA_CH_RDTR_LO 0x2c
549 #define DMA_CH_TDRLR 0x30
550 #define DMA_CH_RDRLR 0x34
551 #define DMA_CH_IER 0x38
552 #define DMA_CH_RIWT 0x3c
553 #define DMA_CH_SR 0x60
574 #define DMA_CH_IER_TIE_POS 0
582 #define DMA_CH_RCR_SR_POS 0
584 #define DMA_CH_RIWT_RWT_POS 0
596 #define DMA_CH_SR_TI_POS 0
604 #define DMA_CH_TCR_ST_POS 0
610 #define DMA_OSP_DISABLE 0x00
611 #define DMA_OSP_ENABLE 0x01
621 #define DMA_PBL_X8_DISABLE 0x00
622 #define DMA_PBL_X8_ENABLE 0x01
629 #define RX_PACKET_ERRORS_LENGTH_POS 0
634 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS 0
649 #define RX_NORMAL_DESC0_OVT_POS 0
651 #define RX_NORMAL_DESC2_HL_POS 0
671 #define RX_NORMAL_DESC3_PL_POS 0
688 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS 0
697 #define TX_CONTEXT_DESC2_MSS_POS 0
705 #define TX_CONTEXT_DESC3_VT_POS 0
708 #define TX_NORMAL_DESC2_HL_B1L_POS 0
724 #define TX_NORMAL_DESC3_FL_POS 0
732 #define TX_NORMAL_DESC3_TCPPL_POS 0
737 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2