22 		writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);  in spl2sw_mac_hw_stop()
23 		writel(0xffffffff, comm->l2sw_reg_base + L2SW_SW_INT_STATUS_0);  in spl2sw_mac_hw_stop()
28 		writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);  in spl2sw_mac_hw_stop()
34 	writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);  in spl2sw_mac_hw_stop()
45 	writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);  in spl2sw_mac_hw_start()
50 	writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);  in spl2sw_mac_hw_start()
60 	writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),  in spl2sw_mac_addr_add()
62 	writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +  in spl2sw_mac_addr_add()
69 	writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);  in spl2sw_mac_addr_add()
95 	writel((mac->mac_addr[0] << 0) + (mac->mac_addr[1] << 8),  in spl2sw_mac_addr_del()
97 	writel((mac->mac_addr[2] << 0) + (mac->mac_addr[3] << 8) +  in spl2sw_mac_addr_del()
105 	writel(reg, comm->l2sw_reg_base + L2SW_WT_MAC_AD0);  in spl2sw_mac_addr_del()
131 	writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);  in spl2sw_mac_hw_init()
134 	writel(comm->desc_dma, comm->l2sw_reg_base + L2SW_TX_LBASE_ADDR_0);  in spl2sw_mac_hw_init()
135 	writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * TX_DESC_NUM,  in spl2sw_mac_hw_init()
137 	writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +  in spl2sw_mac_hw_init()
139 	writel(comm->desc_dma + sizeof(struct spl2sw_mac_desc) * (TX_DESC_NUM +  in spl2sw_mac_hw_init()
144 	writel(0x4a3a2d1d, comm->l2sw_reg_base + L2SW_FL_CNTL_TH);  in spl2sw_mac_hw_init()
147 	writel(0x4a3a1212, comm->l2sw_reg_base + L2SW_CPU_FL_CNTL_TH);  in spl2sw_mac_hw_init()
150 	writel(0xf6680000, comm->l2sw_reg_base + L2SW_PRI_FL_CNTL);  in spl2sw_mac_hw_init()
155 	writel(reg, comm->l2sw_reg_base + L2SW_LED_PORT0);  in spl2sw_mac_hw_init()
166 	writel(reg, comm->l2sw_reg_base + L2SW_CPU_CNTL);  in spl2sw_mac_hw_init()
176 	writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL0);  in spl2sw_mac_hw_init()
181 	writel(reg, comm->l2sw_reg_base + L2SW_PORT_CNTL1);  in spl2sw_mac_hw_init()
190 	writel(reg, comm->l2sw_reg_base + L2SW_MAC_FORCE_MODE);  in spl2sw_mac_hw_init()
196 	writel(reg, comm->l2sw_reg_base + L2SW_PVID_CONFIG0);  in spl2sw_mac_hw_init()
202 	writel(reg, comm->l2sw_reg_base + L2SW_VLAN_MEMSET_CONFIG0);  in spl2sw_mac_hw_init()
213 	writel(reg, comm->l2sw_reg_base + L2SW_SW_GLB_CNTL);  in spl2sw_mac_hw_init()
215 	writel(MAC_INT_MASK_DEF, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0);  in spl2sw_mac_hw_init()
242 	writel((reg & (~mask)) | ((~rx_mode) & mask), comm->l2sw_reg_base + L2SW_CPU_CNTL);  in spl2sw_mac_rx_mode_set()