Lines Matching full:rgmii
36 * cycle of the 125MHz RGMII TX clock):
74 * Each step is 200ps. These bits are used with external RGMII PHYs
75 * because RGMII RX only has the small window. cfg_rxclk_dly can
220 /* enable RGMII mode */ in meson8b_set_phy_mode()
226 /* disable RGMII mode -> enables RMII mode */ in meson8b_set_phy_mode()
246 /* enable RGMII mode */ in meson_axg_set_phy_mode()
252 /* disable RGMII mode -> enables RMII mode */ in meson_axg_set_phy_mode()
355 /* only relevant for RMII mode -> disable in RGMII mode */ in meson8b_init_prg_eth()
359 /* Configure the 125MHz RGMII TX clock, the IP block changes in meson8b_init_prg_eth()
367 "failed to set RGMII TX clock\n"); in meson8b_init_prg_eth()
375 "failed to enable the RGMII TX clock\n"); in meson8b_init_prg_eth()
450 "The RGMII RX delay range is 0..3000ps in 200ps steps"); in meson8b_dwmac_probe()
457 "The only allowed RGMII RX delays values are: 0ps, 2000ps"); in meson8b_dwmac_probe()