40 #define PHY_ID_ANY		0x1f
41 #define MII_REG_ANY		0x1f
55 #define RX_BUF_MASK		0xfff8
57 #define SIS190_REGS_SIZE	0x80
65 #define EhnMIIread		0x0000
66 #define EhnMIIwrite		0x0020
70 #define EhnMIIreq		0x0010
71 #define EhnMIInotDone		0x0010
84 	TxControl		= 0x00,
85 	TxDescStartAddr		= 0x04,
86 	rsv0			= 0x08,	// reserved
87 	TxSts			= 0x0c,	// unused (Control/Status)
88 	RxControl		= 0x10,
89 	RxDescStartAddr		= 0x14,
90 	rsv1			= 0x18,	// reserved
91 	RxSts			= 0x1c,	// unused
92 	IntrStatus		= 0x20,
93 	IntrMask		= 0x24,
94 	IntrControl		= 0x28,
95 	IntrTimer		= 0x2c,	// unused (Interrupt Timer)
96 	PMControl		= 0x30,	// unused (Power Mgmt Control/Status)
97 	rsv2			= 0x34,	// reserved
98 	ROMControl		= 0x38,
99 	ROMInterface		= 0x3c,
100 	StationControl		= 0x40,
101 	GMIIControl		= 0x44,
102 	GIoCR			= 0x48, // unused (GMAC IO Compensation)
103 	GIoCtrl			= 0x4c, // unused (GMAC IO Control)
104 	TxMacControl		= 0x50,
105 	TxLimit			= 0x54, // unused (Tx MAC Timer/TryLimit)
106 	RGDelay			= 0x58, // unused (RGMII Tx Internal Delay)
107 	rsv3			= 0x5c, // reserved
108 	RxMacControl		= 0x60,
109 	RxMacAddr		= 0x62,
110 	RxHashTable		= 0x68,
111 	// Undocumented		= 0x6c,
112 	RxWolCtrl		= 0x70,
113 	RxWolData		= 0x74, // unused (Rx WOL Data Access)
114 	RxMPSControl		= 0x78,	// unused (Rx MPS Control)
115 	rsv4			= 0x7c, // reserved
120 	SoftInt			= 0x40000000,	// unused
121 	Timeup			= 0x20000000,	// unused
122 	PauseFrame		= 0x00080000,	// unused
123 	MagicPacket		= 0x00040000,	// unused
124 	WakeupFrame		= 0x00020000,	// unused
125 	LinkChange		= 0x00010000,
126 	RxQEmpty		= 0x00000080,
127 	RxQInt			= 0x00000040,
128 	TxQ1Empty		= 0x00000020,	// unused
129 	TxQ1Int			= 0x00000010,
130 	TxQ0Empty		= 0x00000008,	// unused
131 	TxQ0Int			= 0x00000004,
132 	RxHalt			= 0x00000002,
133 	TxHalt			= 0x00000001,
136 	CmdReset		= 0x10,
137 	CmdRxEnb		= 0x08,		// unused
138 	CmdTxEnb		= 0x01,
139 	RxBufEmpty		= 0x01,		// unused
142 	Cfg9346_Lock		= 0x00,		// unused
143 	Cfg9346_Unlock		= 0xc0,		// unused
146 	AcceptErr		= 0x20,		// unused
147 	AcceptRunt		= 0x10,		// unused
148 	AcceptBroadcast		= 0x0800,
149 	AcceptMulticast		= 0x0400,
150 	AcceptMyPhys		= 0x0200,
151 	AcceptAllPhys		= 0x0100,
155 	RxCfgDMAShift		= 8,		// 0x1a in RxControl ?
159 	TxDMAShift		= 8, /* DMA burst value (0-7) is shift this many bits */
161 	LinkStatus		= 0x02,		// unused
162 	FullDup			= 0x01,		// unused
165 	TBILinkOK		= 0x02000000,	// unused
184 	OWNbit		= 0x80000000, // RXOWN/TXOWN
185 	INTbit		= 0x40000000, // RXINT/TXINT
186 	CRCbit		= 0x00020000, // CRCOFF/CRCEN
187 	PADbit		= 0x00010000, // PREADD/PADEN
189 	RingEnd		= 0x80000000,
191 	LSEN		= 0x08000000, // TSO ? -- FR
192 	IPCS		= 0x04000000,
193 	TCPCS		= 0x02000000,
194 	UDPCS		= 0x01000000,
195 	BSTEN		= 0x00800000,
196 	EXTEN		= 0x00400000,
197 	DEFEN		= 0x00200000,
198 	BKFEN		= 0x00100000,
199 	CRSEN		= 0x00080000,
200 	COLEN		= 0x00040000,
201 	THOL3		= 0x30000000,
202 	THOL2		= 0x20000000,
203 	THOL1		= 0x10000000,
204 	THOL0		= 0x00000000,
206 	WND		= 0x00080000,
207 	TABRT		= 0x00040000,
208 	FIFO		= 0x00020000,
209 	LINK		= 0x00010000,
210 	ColCountMask	= 0x0000ffff,
212 	IPON		= 0x20000000,
213 	TCPON		= 0x10000000,
214 	UDPON		= 0x08000000,
215 	Wakup		= 0x00400000,
216 	Magic		= 0x00200000,
217 	Pause		= 0x00100000,
218 	DEFbit		= 0x00200000,
219 	BCAST		= 0x000c0000,
220 	MCAST		= 0x00080000,
221 	UCAST		= 0x00040000,
223 	TAGON		= 0x80000000,
224 	RxDescCountMask	= 0x7f000000, // multi-desc pkt when > 1 ? -- FR
225 	ABORT		= 0x00800000,
226 	SHORT		= 0x00400000,
227 	LIMIT		= 0x00200000,
228 	MIIER		= 0x00100000,
229 	OVRUN		= 0x00080000,
230 	NIBON		= 0x00040000,
231 	COLON		= 0x00020000,
232 	CRCOK		= 0x00010000,
233 	RxSizeMask	= 0x0000ffff
242 	EECS	= 0x00000001,	// unused
243 	EECLK	= 0x00000002,	// unused
244 	EEDO	= 0x00000008,	// unused
245 	EEDI	= 0x00000004,	// unused
246 	EEREQ	= 0x00000080,
247 	EEROP	= 0x00000200,
248 	EEWOP	= 0x00000100	// unused
253 	EEPROMSignature	= 0x00,
254 	EEPROMCLK	= 0x01,	// unused
255 	EEPROMInfo	= 0x02,
256 	EEPROMMACAddr	= 0x03
304 	UNKNOWN	= 0x00,
305 	HOME	= 0x01,
306 	LAN	= 0x02,
307 	MIX	= 0x03
316 	{ "Atheros PHY",          { 0x004d, 0xd010 }, LAN, 0 },
317 	{ "Atheros PHY AR8012",   { 0x004d, 0xd020 }, LAN, 0 },
318 	{ "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
319 	{ "Broadcom PHY AC131",   { 0x0143, 0xbc70 }, LAN, 0 },
320 	{ "Agere PHY ET1101B",    { 0x0282, 0xf010 }, LAN, 0 },
321 	{ "Marvell PHY 88E1111",  { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
322 	{ "Realtek PHY RTL8201",  { 0x0000, 0x8200 }, LAN, 0 },
334 	{ PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
335 	{ PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
336 	{ 0, },
348 module_param(rx_copybreak, int, 0);
350 module_param_named(debug, debug.msg_enable, int, 0);
351 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
373 	for (i = 0; i < 100; i++) {  in __mdio_cmd()
420 	u16 data = 0xffff;  in sis190_read_eeprom()
423 	if (!(SIS_R32(ROMControl) & 0x0002))  in sis190_read_eeprom()
424 		return 0;  in sis190_read_eeprom()
428 	for (i = 0; i < 200; i++) {  in sis190_read_eeprom()
430 			data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;  in sis190_read_eeprom()
441 	SIS_W32(IntrMask, 0x00);  in sis190_irq_mask_and_ack()
442 	SIS_W32(IntrStatus, 0xffffffff);  in sis190_irq_mask_and_ack()
450 	SIS_W32(TxControl, 0x1a00);  in sis190_asic_down()
451 	SIS_W32(RxControl, 0x1a00);  in sis190_asic_down()
465 	desc->PSize = 0x0;  in sis190_give_to_asic()
480 	desc->PSize = 0x0;  in sis190_make_unusable_by_asic()
481 	desc->addr = cpu_to_le32(0xdeadbeef);  in sis190_make_unusable_by_asic()
484 	desc->status = 0x0;  in sis190_make_unusable_by_asic()
547 	skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);  in sis190_try_rx_copy()
559 		return 0;  in sis190_rx_pkt_err()
584 	for (; rx_left > 0; rx_left--, cur_rx++) {  in sis190_rx_interrupt()
596 		if (sis190_rx_pkt_err(status, stats) < 0)  in sis190_rx_interrupt()
662 	memset(desc, 0x00, sizeof(*desc));  in sis190_unmap_tx_skb()
670 		return 0;  in sis190_tx_pkt_err()
712 		if (likely(sis190_tx_pkt_err(status, stats) == 0)) {  in sis190_tx_interrupt()
740 	unsigned int handled = 0;  in sis190_irq()
745 	if ((status == 0xffffffff) || !status)  in sis190_irq()
802 	for (i = 0; i < NUM_RX_DESC; i++) {  in sis190_rx_clear()
811 	tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;  in sis190_init_ring_indexes()
820 	memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));  in sis190_init_ring()
821 	memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));  in sis190_init_ring()
823 	if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)  in sis190_init_ring()
828 	return 0;  in sis190_init_ring()
847 		mc_filter[1] = mc_filter[0] = 0xffffffff;  in sis190_set_rx_mode()
852 		mc_filter[1] = mc_filter[0] = 0xffffffff;  in sis190_set_rx_mode()
857 		mc_filter[1] = mc_filter[0] = 0;  in sis190_set_rx_mode()
860 				ether_crc(ETH_ALEN, ha->addr) & 0x3f;  in sis190_set_rx_mode()
868 	SIS_W16(RxMacControl, rx_mode | 0x2);  in sis190_set_rx_mode()
869 	SIS_W32(RxHashTable, mc_filter[0]);  in sis190_set_rx_mode()
877 	SIS_W32(IntrControl, 0x8000);  in sis190_soft_reset()
879 	SIS_W32(IntrControl, 0x0);  in sis190_soft_reset()
893 	SIS_W32(IntrStatus, 0xffffffff);  in sis190_hw_start()
894 	SIS_W32(IntrMask, 0x0);  in sis190_hw_start()
895 	SIS_W32(GMIIControl, 0x0);  in sis190_hw_start()
896 	SIS_W32(TxMacControl, 0x60);  in sis190_hw_start()
897 	SIS_W16(RxMacControl, 0x02);  in sis190_hw_start()
898 	SIS_W32(RxHashTable, 0x0);  in sis190_hw_start()
899 	SIS_W32(0x6c, 0x0);  in sis190_hw_start()
900 	SIS_W32(RxWolCtrl, 0x0);  in sis190_hw_start()
901 	SIS_W32(RxWolData, 0x0);  in sis190_hw_start()
910 	SIS_W32(TxControl, 0x1a00 | CmdTxEnb);  in sis190_hw_start()
911 	SIS_W32(RxControl, 0x1a1d);  in sis190_hw_start()
949 			{ LPA_1000FULL, 0x07000c00 | 0x00001000,  in sis190_phy_task()
951 			{ LPA_1000HALF, 0x07000c00,  in sis190_phy_task()
953 			{ LPA_100FULL, 0x04000800 | 0x00001000,  in sis190_phy_task()
955 			{ LPA_100HALF, 0x04000800,  in sis190_phy_task()
957 			{ LPA_10FULL, 0x04000400 | 0x00001000,  in sis190_phy_task()
959 			{ LPA_10HALF, 0x04000400,  in sis190_phy_task()
961 			{ 0, 0x04000400, "unknown" }  in sis190_phy_task()
965 		val = mdio_read(ioaddr, phy_id, 0x1f);  in sis190_phy_task()
993 		p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;  in sis190_phy_task()
998 			mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);  in sis190_phy_task()
1000 			mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);  in sis190_phy_task()
1001 			p->ctl |= 0x03000000;  in sis190_phy_task()
1007 			SIS_W32(RGDelay, 0x0441);  in sis190_phy_task()
1008 			SIS_W32(RGDelay, 0x0440);  in sis190_phy_task()
1045 	timer_setup(timer, sis190_phy_timer, 0);  in sis190_request_timer()
1057 	if (tp->rx_buf_sz & 0x07) {  in sis190_set_rxbufsize()
1086 	if (rc < 0)  in sis190_open()
1092 	if (rc < 0)  in sis190_open()
1115 	for (i = 0; i < NUM_TX_DESC; i++) {  in sis190_tx_clear()
1127 	tp->cur_tx = tp->dirty_tx = 0;  in sis190_tx_clear()
1134 	unsigned int poll_locked = 0;  in sis190_down()
1177 	return 0;  in sis190_close()
1240 	SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);  in sis190_start_xmit()
1336 	phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);  in sis190_init_phy()
1340 		if ((p->id[0] == phy->id[0]) &&  in sis190_init_phy()
1341 		    (p->id[1] == (phy->id[1] & 0xfff0))) {  in sis190_init_phy()
1357 			pr_info("%s: unknown PHY 0x%x:0x%x transceiver at address %d\n",  in sis190_init_phy()
1359 				phy->id[0], (phy->id[1] & 0xfff0), phy_id);  in sis190_init_phy()
1369 			{ 0x808b, 0x0ce1 },  in sis190_mii_probe_88e1111_fixup()
1370 			{ 0x808f, 0x0c60 }  in sis190_mii_probe_88e1111_fixup()
1373 		p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];  in sis190_mii_probe_88e1111_fixup()
1375 		mdio_write(ioaddr, phy_id, 0x1b, p[0]);  in sis190_mii_probe_88e1111_fixup()
1377 		mdio_write(ioaddr, phy_id, 0x14, p[1]);  in sis190_mii_probe_88e1111_fixup()
1396 	int rc = 0;  in sis190_mii_probe()
1400 	for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {  in sis190_mii_probe()
1407 		if (status == 0xffff || status == 0x0000)  in sis190_mii_probe()
1482 	if (rc < 0) {  in sis190_init_board()
1490 	if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {  in sis190_init_board()
1492 			pr_err("%s: region #0 is no MMIO resource\n",  in sis190_init_board()
1496 	if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {  in sis190_init_board()
1504 	if (rc < 0) {  in sis190_init_board()
1512 	if (rc < 0) {  in sis190_init_board()
1521 	ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);  in sis190_init_board()
1566 	SIS_W32(IntrMask, 0x0000);  in sis190_tx_timeout()
1581 	tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;  in sis190_set_rgmii()
1599 	if ((sig == 0xffff) || (sig == 0x0000)) {  in sis190_get_mac_addr_from_eeprom()
1607 	for (i = 0; i < ETH_ALEN / 2; i++) {  in sis190_get_mac_addr_from_eeprom()
1616 	return 0;  in sis190_get_mac_addr_from_eeprom()
1631 	static const u16 ids[] = { 0x0965, 0x0966, 0x0968 };  in sis190_get_mac_addr_from_apc()
1641 	for (i = 0; i < ARRAY_SIZE(ids); i++) {  in sis190_get_mac_addr_from_apc()
1655 	pci_read_config_byte(isa_bridge, 0x48, &tmp8);  in sis190_get_mac_addr_from_apc()
1656 	reg = (tmp8 & ~0x02);  in sis190_get_mac_addr_from_apc()
1657 	pci_write_config_byte(isa_bridge, 0x48, reg);  in sis190_get_mac_addr_from_apc()
1659 	pci_read_config_byte(isa_bridge, 0x48, &reg);  in sis190_get_mac_addr_from_apc()
1661         for (i = 0; i < ETH_ALEN; i++) {  in sis190_get_mac_addr_from_apc()
1662                 outb(0x9 + i, 0x78);  in sis190_get_mac_addr_from_apc()
1663                 addr[i] = inb(0x79);  in sis190_get_mac_addr_from_apc()
1667 	outb(0x12, 0x78);  in sis190_get_mac_addr_from_apc()
1668 	reg = inb(0x79);  in sis190_get_mac_addr_from_apc()
1673 	pci_write_config_byte(isa_bridge, 0x48, tmp8);  in sis190_get_mac_addr_from_apc()
1676 	return 0;  in sis190_get_mac_addr_from_apc()
1699 	SIS_W16(RxMacControl, ctl & ~0x0f00);  in sis190_init_rxfilter()
1701 	for (i = 0; i < ETH_ALEN; i++)  in sis190_init_rxfilter()
1713 	if (rc < 0) {  in sis190_get_mac_addr()
1716 		pci_read_config_byte(pdev, 0x73, &reg);  in sis190_get_mac_addr()
1718 		if (reg & 0x00000001)  in sis190_get_mac_addr()
1735 	// Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0  in sis190_set_speed_auto()
1756 	return 0;  in sis190_get_link_ksettings()
1862 	static int printed_version = 0;  in sis190_init_one()
1886 	if (rc < 0)  in sis190_init_one()
1901 	if (rc < 0)  in sis190_init_one()
1905 	if (rc < 0)  in sis190_init_one()