1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright 2005-2006 Fen Systems Ltd.
5  * Copyright 2005-2013 Solarflare Communications Inc.
63 /* Checksum generation is a per-queue option in hardware, so each
86 #define EFX_RX_USR_BUF_SIZE	(2048 - 256)
89  * of every buffer.  Otherwise, we just need to ensure 4-byte
98 /* Non-standard XDP_PACKET_HEADROOM and tailroom to satisfy XDP_REDIRECT and
111  * struct efx_buffer - A general-purpose DMA buffer
126  * struct efx_tx_buffer - buffer state for a TX descriptor
131  * @option: When @flags & %EFX_TX_BUF_OPTION, an EF10-specific option
164  * struct efx_tx_queue - An Efx TX queue
179  *	Is our index within @channel->tx_queue array.
187  *	%EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
193  * @initialised: Has hardware queue been initialised?
200  *	only get the up-to-date value of @write_count if this
202  *	avoid cache-line ping-pong between the xmit path and the
217  *	Filled in iff @efx->type->option_descriptors; only used for PIO.
221  *	only get the up-to-date value of read_count if this
223  *	avoid cache-line ping-pong between the xmit path and the
237  *	@read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
255 	bool initialised;  member
292 #define EFX_TX_CB_SIZE	(1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
295  * struct efx_rx_buffer - An Efx RX data buffer
321  * struct efx_rx_page_state - Page-based rx buffer state
336  * struct efx_rx_queue - An Efx RX queue
367  * @min_fill: RX descriptor minimum non-zero fill level.
421  * struct efx_channel - An Efx channel
430  * @eventq_init: Event queue initialised flag
432  * @irq: IRQ number (MSI and MSI-X only)
550  * struct efx_msi_context - Context for each MSI
565  * struct efx_channel_type - distinguishes traffic and extra channels
579  * @keep_eventq: Flag for whether event queue should be kept initialised
611 	STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
620 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
675 /* Pseudo bit-mask flow control field */
681  * struct efx_link_state - Current state of the link
683  * @fd: Link is full-duplex
697 	return left->up == right->up && left->fd == right->fd &&  in efx_link_state_equal()
698 		left->fc == right->fc && left->speed == right->speed;  in efx_link_state_equal()
702  * enum efx_phy_mode - PHY operating mode flags
723  * struct efx_hw_stat_desc - Description of a hardware statistic
726  * @dma_width: Width in bits (0 for non-DMA statistics)
727  * @offset: Offset within stats (ignored for non-DMA statistics)
740  * struct efx_rss_context - A user-defined RSS context for filtering
742  * @context_id: the RSS_CONTEXT_ID returned by MC firmware, or
746  * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
763 #define EFX_ARFS_FILTER_ID_PENDING	-1
764 #define EFX_ARFS_FILTER_ID_ERROR	-2
765 #define EFX_ARFS_FILTER_ID_REMOVING	-3
767  * struct efx_arfs_rule - record of an ARFS filter and its IDs
769  * @spec: details of the filter (used as key for hash table).  Use efx->type to
790  * struct efx_async_filter_insertion - Request to asynchronously insert a filter
795  * @flow_id: Identifies the kernel-side flow for which this request was made
818  * struct efx_nic - an Efx NIC
836  * @vi_stride: step between per-VI registers / memory regions
851  * @extra_channel_types: Types of extra (non-traffic) channels that
884  *	(valid only if channel->sync_timestamps_enabled; always negative)
893  * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
898  * @selftest_work: Work item for asynchronous self-test
901  * @mcdi: Management-Controller-to-Driver Interface state
912  * @num_mac_stats: Number of MAC stats reported by firmware (MAC_STATS_NUM_STATS
916  * @phy_data: PHY private data (including PHY-specific stats)
926  * @fc_disable: When non-zero flow control is disabled. Typically used to
932  * @loopback_selftest: Offline self-test private state
935  * @filter_state: Architecture-dependent filter table state
937  * @rps_slot_map: bitmap of in-flight entries in @rps_slot
951  * @vf_init_count: Number of VFs that have been fully initialised.
1164  * struct efx_probe_data - State after hardware probe
1178 	return &probe_data->efx;  in efx_netdev_priv()
1183 	return efx->net_dev->reg_state == NETREG_REGISTERED;  in efx_dev_registered()
1188 	return efx->port_num;  in efx_port_num()
1206  * struct efx_nic_type - Efx device type definition
1248  *	The SDU length may be any value from 0 up to the protocol-
1261  * @irq_disable_non_ev: Disable non-event IRQs on the NIC.  Each event
1313  * @mtd_sync: Wait for write-back to complete on MTD partition.  This
1324  * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1328  * @print_additional_fwver: Dump NIC-specific additional FW version info
1336  * @evq_rptr_tbl_base: Event queue read-pointer table base address
1539 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);  in efx_get_channel()
1540 	return efx->channel[index];  in efx_get_channel()
1545 	for (_channel = (_efx)->channel[0];				\
1547 	     _channel = (_channel->channel + 1 < (_efx)->n_channels) ?	\
1548 		     (_efx)->channel[_channel->channel + 1] : NULL)
1552 	for (_channel = (_efx)->channel[(_efx)->n_channels - 1];	\
1554 	     _channel = _channel->channel ?				\
1555 		     (_efx)->channel[_channel->channel - 1] : NULL)
1560 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels);  in efx_get_tx_channel()
1561 	return efx->channel[efx->tx_channel_offset + index];  in efx_get_tx_channel()
1567 	EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_xdp_channels);  in efx_get_xdp_channel()
1568 	return efx->channel[efx->xdp_channel_offset + index];  in efx_get_xdp_channel()
1573 	return channel->channel - channel->efx->xdp_channel_offset <  in efx_channel_is_xdp_tx()
1574 	       channel->efx->n_xdp_channels;  in efx_channel_is_xdp_tx()
1579 	return channel && channel->channel >= channel->efx->tx_channel_offset;  in efx_channel_has_tx_queues()
1585 		return channel->efx->xdp_tx_per_channel;  in efx_channel_num_tx_queues()
1586 	return channel->efx->tx_queues_per_channel;  in efx_channel_num_tx_queues()
1593 	return channel->tx_queue_by_type[type];  in efx_channel_get_tx_queue()
1609 		for (_tx_queue = (_channel)->tx_queue;			\
1610 		     _tx_queue < (_channel)->tx_queue +			\
1616 	return channel->rx_queue.core_index >= 0;  in efx_channel_has_rx_queue()
1623 	return &channel->rx_queue;  in efx_channel_get_rx_queue()
1631 		for (_rx_queue = &(_channel)->rx_queue;			\
1643 	return efx_rx_queue_channel(rx_queue)->channel;  in efx_rx_queue_index()
1652 	return &rx_queue->buffer[index];  in efx_rx_buffer()
1658 	if (unlikely(rx_buf == efx_rx_buffer(rx_queue, rx_queue->ptr_mask)))  in efx_rx_buf_next()
1665  * EFX_MAX_FRAME_LEN - calculate maximum frame length
1673  * The 10G MAC requires 8-byte alignment on the frame
1676  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1687 	return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;  in efx_xmit_with_hwtstamp()
1691 	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;  in efx_xmit_hwtstamp_pending()
1703 				 tx_queue->insert_count - tx_queue->read_count);  in efx_channel_tx_fill_level()
1717 				 tx_queue->insert_count - tx_queue->old_read_count);  in efx_channel_tx_old_fill_level()
1729 	const struct net_device *net_dev = efx->net_dev;  in efx_supported_features()
1731 	return net_dev->features | net_dev->hw_features;  in efx_supported_features()
1738 	return tx_queue->insert_count & tx_queue->ptr_mask;  in efx_tx_queue_get_insert_index()
1745 	return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];  in __efx_tx_queue_get_insert_buffer()
1755 	EFX_WARN_ON_ONCE_PARANOID(buffer->len);  in efx_tx_queue_get_insert_buffer()
1756 	EFX_WARN_ON_ONCE_PARANOID(buffer->flags);  in efx_tx_queue_get_insert_buffer()
1757 	EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);  in efx_tx_queue_get_insert_buffer()