80 #define RTL_W8(tp, reg, val8)	writeb((val8), tp->mmio_addr + (reg))  argument
81 #define RTL_W16(tp, reg, val16)	writew((val16), tp->mmio_addr + (reg))  argument
82 #define RTL_W32(tp, reg, val32)	writel((val32), tp->mmio_addr + (reg))  argument
83 #define RTL_R8(tp, reg)		readb(tp->mmio_addr + (reg))  argument
84 #define RTL_R16(tp, reg)		readw(tp->mmio_addr + (reg))  argument
85 #define RTL_R32(tp, reg)		readl(tp->mmio_addr + (reg))  argument
639 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
666 static inline struct device *tp_to_dev(struct rtl8169_private *tp)  in tp_to_dev()  argument
668 	return &tp->pci_dev->dev;  in tp_to_dev()
671 static void rtl_lock_config_regs(struct rtl8169_private *tp)  in rtl_lock_config_regs()  argument
675 	raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);  in rtl_lock_config_regs()
676 	if (!--tp->cfg9346_usage_count)  in rtl_lock_config_regs()
677 		RTL_W8(tp, Cfg9346, Cfg9346_Lock);  in rtl_lock_config_regs()
678 	raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);  in rtl_lock_config_regs()
681 static void rtl_unlock_config_regs(struct rtl8169_private *tp)  in rtl_unlock_config_regs()  argument
685 	raw_spin_lock_irqsave(&tp->cfg9346_usage_lock, flags);  in rtl_unlock_config_regs()
686 	if (!tp->cfg9346_usage_count++)  in rtl_unlock_config_regs()
687 		RTL_W8(tp, Cfg9346, Cfg9346_Unlock);  in rtl_unlock_config_regs()
688 	raw_spin_unlock_irqrestore(&tp->cfg9346_usage_lock, flags);  in rtl_unlock_config_regs()
691 static void rtl_pci_commit(struct rtl8169_private *tp)  in rtl_pci_commit()  argument
694 	RTL_R8(tp, ChipCmd);  in rtl_pci_commit()
697 static void rtl_mod_config2(struct rtl8169_private *tp, u8 clear, u8 set)  in rtl_mod_config2()  argument
702 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in rtl_mod_config2()
703 	val = RTL_R8(tp, Config2);  in rtl_mod_config2()
704 	RTL_W8(tp, Config2, (val & ~clear) | set);  in rtl_mod_config2()
705 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in rtl_mod_config2()
708 static void rtl_mod_config5(struct rtl8169_private *tp, u8 clear, u8 set)  in rtl_mod_config5()  argument
713 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in rtl_mod_config5()
714 	val = RTL_R8(tp, Config5);  in rtl_mod_config5()
715 	RTL_W8(tp, Config5, (val & ~clear) | set);  in rtl_mod_config5()
716 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in rtl_mod_config5()
719 static bool rtl_is_8125(struct rtl8169_private *tp)  in rtl_is_8125()  argument
721 	return tp->mac_version >= RTL_GIGA_MAC_VER_61;  in rtl_is_8125()
724 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)  in rtl_is_8168evl_up()  argument
726 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_is_8168evl_up()
727 	       tp->mac_version != RTL_GIGA_MAC_VER_39 &&  in rtl_is_8168evl_up()
728 	       tp->mac_version <= RTL_GIGA_MAC_VER_53;  in rtl_is_8168evl_up()
731 static bool rtl_supports_eee(struct rtl8169_private *tp)  in rtl_supports_eee()  argument
733 	return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&  in rtl_supports_eee()
734 	       tp->mac_version != RTL_GIGA_MAC_VER_37 &&  in rtl_supports_eee()
735 	       tp->mac_version != RTL_GIGA_MAC_VER_39;  in rtl_supports_eee()
738 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)  in rtl_read_mac_from_reg()  argument
743 		mac[i] = RTL_R8(tp, reg + i);  in rtl_read_mac_from_reg()
751 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,  in rtl_loop_wait()  argument
757 		if (c->check(tp) == high)  in rtl_loop_wait()
763 		netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",  in rtl_loop_wait()
768 static bool rtl_loop_wait_high(struct rtl8169_private *tp,  in rtl_loop_wait_high()  argument
772 	return rtl_loop_wait(tp, c, d, n, true);  in rtl_loop_wait_high()
775 static bool rtl_loop_wait_low(struct rtl8169_private *tp,  in rtl_loop_wait_low()  argument
779 	return rtl_loop_wait(tp, c, d, n, false);  in rtl_loop_wait_low()
790 static bool name ## _check(struct rtl8169_private *tp)
792 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)  in r8168fp_adjust_ocp_cmd()  argument
796 	    (tp->mac_version == RTL_GIGA_MAC_VER_52 ||  in r8168fp_adjust_ocp_cmd()
797 	     tp->mac_version == RTL_GIGA_MAC_VER_53))  in r8168fp_adjust_ocp_cmd()
803 	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;  in DECLARE_RTL_COND()
806 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in _rtl_eri_write()  argument
814 	RTL_W32(tp, ERIDR, val);  in _rtl_eri_write()
815 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_write()
816 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_write()
818 	rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);  in _rtl_eri_write()
821 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,  in rtl_eri_write()  argument
824 	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);  in rtl_eri_write()
827 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)  in _rtl_eri_read()  argument
831 	r8168fp_adjust_ocp_cmd(tp, &cmd, type);  in _rtl_eri_read()
832 	RTL_W32(tp, ERIAR, cmd);  in _rtl_eri_read()
834 	return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?  in _rtl_eri_read()
835 		RTL_R32(tp, ERIDR) : ~0;  in _rtl_eri_read()
838 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)  in rtl_eri_read()  argument
840 	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);  in rtl_eri_read()
843 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)  in rtl_w0w1_eri()  argument
845 	u32 val = rtl_eri_read(tp, addr);  in rtl_w0w1_eri()
847 	rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);  in rtl_w0w1_eri()
850 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)  in rtl_eri_set_bits()  argument
852 	rtl_w0w1_eri(tp, addr, p, 0);  in rtl_eri_set_bits()
855 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)  in rtl_eri_clear_bits()  argument
857 	rtl_w0w1_eri(tp, addr, 0, m);  in rtl_eri_clear_bits()
867 	return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;  in DECLARE_RTL_COND()
870 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_phy_ocp_write()  argument
875 	RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);  in r8168_phy_ocp_write()
877 	rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);  in r8168_phy_ocp_write()
880 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_phy_ocp_read()  argument
885 	RTL_W32(tp, GPHY_OCP, reg << 15);  in r8168_phy_ocp_read()
887 	return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?  in r8168_phy_ocp_read()
888 		(RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;  in r8168_phy_ocp_read()
891 static void __r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in __r8168_mac_ocp_write()  argument
896 	RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);  in __r8168_mac_ocp_write()
899 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)  in r8168_mac_ocp_write()  argument
903 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_write()
904 	__r8168_mac_ocp_write(tp, reg, data);  in r8168_mac_ocp_write()
905 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_write()
908 static u16 __r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in __r8168_mac_ocp_read()  argument
913 	RTL_W32(tp, OCPDR, reg << 15);  in __r8168_mac_ocp_read()
915 	return RTL_R32(tp, OCPDR);  in __r8168_mac_ocp_read()
918 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)  in r8168_mac_ocp_read()  argument
923 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_read()
924 	val = __r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_read()
925 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_read()
930 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,  in r8168_mac_ocp_modify()  argument
936 	raw_spin_lock_irqsave(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_modify()
937 	data = __r8168_mac_ocp_read(tp, reg);  in r8168_mac_ocp_modify()
938 	__r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);  in r8168_mac_ocp_modify()
939 	raw_spin_unlock_irqrestore(&tp->mac_ocp_lock, flags);  in r8168_mac_ocp_modify()
945 static void rtl8168g_phy_suspend_quirk(struct rtl8169_private *tp, int value)  in rtl8168g_phy_suspend_quirk()  argument
947 	switch (tp->mac_version) {  in rtl8168g_phy_suspend_quirk()
950 			rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);  in rtl8168g_phy_suspend_quirk()
952 			rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);  in rtl8168g_phy_suspend_quirk()
959 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168g_mdio_write()  argument
962 		tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;  in r8168g_mdio_write()
966 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_write()
969 	if (tp->ocp_base == OCP_STD_PHY_BASE && reg == MII_BMCR)  in r8168g_mdio_write()
970 		rtl8168g_phy_suspend_quirk(tp, value);  in r8168g_mdio_write()
972 	r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);  in r8168g_mdio_write()
975 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)  in r8168g_mdio_read()  argument
978 		return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;  in r8168g_mdio_read()
980 	if (tp->ocp_base != OCP_STD_PHY_BASE)  in r8168g_mdio_read()
983 	return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);  in r8168g_mdio_read()
986 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)  in mac_mcu_write()  argument
989 		tp->ocp_base = value << 4;  in mac_mcu_write()
993 	r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);  in mac_mcu_write()
996 static int mac_mcu_read(struct rtl8169_private *tp, int reg)  in mac_mcu_read()  argument
998 	return r8168_mac_ocp_read(tp, tp->ocp_base + reg);  in mac_mcu_read()
1003 	return RTL_R32(tp, PHYAR) & 0x80000000;  in DECLARE_RTL_COND()
1006 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8169_mdio_write()  argument
1008 	RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));  in r8169_mdio_write()
1010 	rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);  in r8169_mdio_write()
1018 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)  in r8169_mdio_read()  argument
1022 	RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);  in r8169_mdio_read()
1024 	value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?  in r8169_mdio_read()
1025 		RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;  in r8169_mdio_read()
1038 	return RTL_R32(tp, OCPAR) & OCPAR_FLAG;  in DECLARE_RTL_COND()
1043 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)  in r8168dp_2_mdio_start()  argument
1045 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_start()
1048 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)  in r8168dp_2_mdio_stop()  argument
1050 	RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);  in r8168dp_2_mdio_stop()
1053 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)  in r8168dp_2_mdio_write()  argument
1055 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_write()
1057 	r8169_mdio_write(tp, reg, value);  in r8168dp_2_mdio_write()
1059 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_write()
1062 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)  in r8168dp_2_mdio_read()  argument
1070 	r8168dp_2_mdio_start(tp);  in r8168dp_2_mdio_read()
1072 	value = r8169_mdio_read(tp, reg);  in r8168dp_2_mdio_read()
1074 	r8168dp_2_mdio_stop(tp);  in r8168dp_2_mdio_read()
1079 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)  in rtl_writephy()  argument
1081 	switch (tp->mac_version) {  in rtl_writephy()
1084 		r8168dp_2_mdio_write(tp, location, val);  in rtl_writephy()
1087 		r8168g_mdio_write(tp, location, val);  in rtl_writephy()
1090 		r8169_mdio_write(tp, location, val);  in rtl_writephy()
1095 static int rtl_readphy(struct rtl8169_private *tp, int location)  in rtl_readphy()  argument
1097 	switch (tp->mac_version) {  in rtl_readphy()
1100 		return r8168dp_2_mdio_read(tp, location);  in rtl_readphy()
1102 		return r8168g_mdio_read(tp, location);  in rtl_readphy()
1104 		return r8169_mdio_read(tp, location);  in rtl_readphy()
1110 	return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;  in DECLARE_RTL_COND()
1113 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)  in rtl_ephy_write()  argument
1115 	RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |  in rtl_ephy_write()
1118 	rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);  in rtl_ephy_write()
1123 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)  in rtl_ephy_read()  argument
1125 	RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);  in rtl_ephy_read()
1127 	return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?  in rtl_ephy_read()
1128 		RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;  in rtl_ephy_read()
1131 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168dp_ocp_read()  argument
1133 	RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));  in r8168dp_ocp_read()
1134 	return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?  in r8168dp_ocp_read()
1135 		RTL_R32(tp, OCPDR) : ~0;  in r8168dp_ocp_read()
1138 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)  in r8168ep_ocp_read()  argument
1140 	return _rtl_eri_read(tp, reg, ERIAR_OOB);  in r8168ep_ocp_read()
1143 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168dp_ocp_write()  argument
1146 	RTL_W32(tp, OCPDR, data);  in r8168dp_ocp_write()
1147 	RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));  in r8168dp_ocp_write()
1148 	rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);  in r8168dp_ocp_write()
1151 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,  in r8168ep_ocp_write()  argument
1154 	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,  in r8168ep_ocp_write()
1158 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)  in r8168dp_oob_notify()  argument
1160 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);  in r8168dp_oob_notify()
1162 	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);  in r8168dp_oob_notify()
1169 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)  in rtl8168_get_ocp_reg()  argument
1171 	return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;  in rtl8168_get_ocp_reg()
1178 	reg = rtl8168_get_ocp_reg(tp);  in DECLARE_RTL_COND()
1180 	return r8168dp_ocp_read(tp, reg) & 0x00000800;  in DECLARE_RTL_COND()
1185 	return r8168ep_ocp_read(tp, 0x124) & 0x00000001;  in DECLARE_RTL_COND()
1190 	return RTL_R8(tp, IBISR0) & 0x20;  in DECLARE_RTL_COND()
1193 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)  in rtl8168ep_stop_cmac()  argument
1195 	RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);  in rtl8168ep_stop_cmac()
1196 	rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);  in rtl8168ep_stop_cmac()
1197 	RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);  in rtl8168ep_stop_cmac()
1198 	RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);  in rtl8168ep_stop_cmac()
1201 static void rtl8168dp_driver_start(struct rtl8169_private *tp)  in rtl8168dp_driver_start()  argument
1203 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);  in rtl8168dp_driver_start()
1204 	rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_start()
1207 static void rtl8168ep_driver_start(struct rtl8169_private *tp)  in rtl8168ep_driver_start()  argument
1209 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);  in rtl8168ep_driver_start()
1210 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_start()
1211 	rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_start()
1214 static void rtl8168_driver_start(struct rtl8169_private *tp)  in rtl8168_driver_start()  argument
1216 	if (tp->dash_type == RTL_DASH_DP)  in rtl8168_driver_start()
1217 		rtl8168dp_driver_start(tp);  in rtl8168_driver_start()
1219 		rtl8168ep_driver_start(tp);  in rtl8168_driver_start()
1222 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)  in rtl8168dp_driver_stop()  argument
1224 	r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);  in rtl8168dp_driver_stop()
1225 	rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);  in rtl8168dp_driver_stop()
1228 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)  in rtl8168ep_driver_stop()  argument
1230 	rtl8168ep_stop_cmac(tp);  in rtl8168ep_driver_stop()
1231 	r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);  in rtl8168ep_driver_stop()
1232 	r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);  in rtl8168ep_driver_stop()
1233 	rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);  in rtl8168ep_driver_stop()
1236 static void rtl8168_driver_stop(struct rtl8169_private *tp)  in rtl8168_driver_stop()  argument
1238 	if (tp->dash_type == RTL_DASH_DP)  in rtl8168_driver_stop()
1239 		rtl8168dp_driver_stop(tp);  in rtl8168_driver_stop()
1241 		rtl8168ep_driver_stop(tp);  in rtl8168_driver_stop()
1244 static bool r8168dp_check_dash(struct rtl8169_private *tp)  in r8168dp_check_dash()  argument
1246 	u16 reg = rtl8168_get_ocp_reg(tp);  in r8168dp_check_dash()
1248 	return r8168dp_ocp_read(tp, reg) & BIT(15);  in r8168dp_check_dash()
1251 static bool r8168ep_check_dash(struct rtl8169_private *tp)  in r8168ep_check_dash()  argument
1253 	return r8168ep_ocp_read(tp, 0x128) & BIT(0);  in r8168ep_check_dash()
1256 static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp)  in rtl_check_dash()  argument
1258 	switch (tp->mac_version) {  in rtl_check_dash()
1261 		return r8168dp_check_dash(tp) ? RTL_DASH_DP : RTL_DASH_NONE;  in rtl_check_dash()
1263 		return r8168ep_check_dash(tp) ? RTL_DASH_EP : RTL_DASH_NONE;  in rtl_check_dash()
1269 static void rtl_set_d3_pll_down(struct rtl8169_private *tp, bool enable)  in rtl_set_d3_pll_down()  argument
1271 	switch (tp->mac_version) {  in rtl_set_d3_pll_down()
1277 			RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN);  in rtl_set_d3_pll_down()
1279 			RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN);  in rtl_set_d3_pll_down()
1286 static void rtl_reset_packet_filter(struct rtl8169_private *tp)  in rtl_reset_packet_filter()  argument
1288 	rtl_eri_clear_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1289 	rtl_eri_set_bits(tp, 0xdc, BIT(0));  in rtl_reset_packet_filter()
1294 	return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;  in DECLARE_RTL_COND()
1297 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)  in rtl8168d_efuse_read()  argument
1299 	RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);  in rtl8168d_efuse_read()
1301 	return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?  in rtl8168d_efuse_read()
1302 		RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;  in rtl8168d_efuse_read()
1305 static u32 rtl_get_events(struct rtl8169_private *tp)  in rtl_get_events()  argument
1307 	if (rtl_is_8125(tp))  in rtl_get_events()
1308 		return RTL_R32(tp, IntrStatus_8125);  in rtl_get_events()
1310 		return RTL_R16(tp, IntrStatus);  in rtl_get_events()
1313 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)  in rtl_ack_events()  argument
1315 	if (rtl_is_8125(tp))  in rtl_ack_events()
1316 		RTL_W32(tp, IntrStatus_8125, bits);  in rtl_ack_events()
1318 		RTL_W16(tp, IntrStatus, bits);  in rtl_ack_events()
1321 static void rtl_irq_disable(struct rtl8169_private *tp)  in rtl_irq_disable()  argument
1323 	if (rtl_is_8125(tp))  in rtl_irq_disable()
1324 		RTL_W32(tp, IntrMask_8125, 0);  in rtl_irq_disable()
1326 		RTL_W16(tp, IntrMask, 0);  in rtl_irq_disable()
1329 static void rtl_irq_enable(struct rtl8169_private *tp)  in rtl_irq_enable()  argument
1331 	if (rtl_is_8125(tp))  in rtl_irq_enable()
1332 		RTL_W32(tp, IntrMask_8125, tp->irq_mask);  in rtl_irq_enable()
1334 		RTL_W16(tp, IntrMask, tp->irq_mask);  in rtl_irq_enable()
1337 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)  in rtl8169_irq_mask_and_ack()  argument
1339 	rtl_irq_disable(tp);  in rtl8169_irq_mask_and_ack()
1340 	rtl_ack_events(tp, 0xffffffff);  in rtl8169_irq_mask_and_ack()
1341 	rtl_pci_commit(tp);  in rtl8169_irq_mask_and_ack()
1344 static void rtl_link_chg_patch(struct rtl8169_private *tp)  in rtl_link_chg_patch()  argument
1346 	struct phy_device *phydev = tp->phydev;  in rtl_link_chg_patch()
1348 	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||  in rtl_link_chg_patch()
1349 	    tp->mac_version == RTL_GIGA_MAC_VER_38) {  in rtl_link_chg_patch()
1351 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1352 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1354 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1355 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1357 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1358 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1360 		rtl_reset_packet_filter(tp);  in rtl_link_chg_patch()
1361 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||  in rtl_link_chg_patch()
1362 		   tp->mac_version == RTL_GIGA_MAC_VER_36) {  in rtl_link_chg_patch()
1364 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);  in rtl_link_chg_patch()
1365 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);  in rtl_link_chg_patch()
1367 			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);  in rtl_link_chg_patch()
1368 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);  in rtl_link_chg_patch()
1370 	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {  in rtl_link_chg_patch()
1372 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);  in rtl_link_chg_patch()
1373 			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);  in rtl_link_chg_patch()
1375 			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_link_chg_patch()
1384 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_wol()  local
1387 	wol->wolopts = tp->saved_wolopts;  in rtl8169_get_wol()
1390 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)  in __rtl8169_set_wol()  argument
1408 	rtl_unlock_config_regs(tp);  in __rtl8169_set_wol()
1410 	if (rtl_is_8168evl_up(tp)) {  in __rtl8169_set_wol()
1413 			rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1415 			rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);  in __rtl8169_set_wol()
1416 	} else if (rtl_is_8125(tp)) {  in __rtl8169_set_wol()
1419 			r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));  in __rtl8169_set_wol()
1421 			r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);  in __rtl8169_set_wol()
1424 	raw_spin_lock_irqsave(&tp->config25_lock, flags);  in __rtl8169_set_wol()
1426 		options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;  in __rtl8169_set_wol()
1429 		RTL_W8(tp, cfg[i].reg, options);  in __rtl8169_set_wol()
1431 	raw_spin_unlock_irqrestore(&tp->config25_lock, flags);  in __rtl8169_set_wol()
1433 	switch (tp->mac_version) {  in __rtl8169_set_wol()
1435 		options = RTL_R8(tp, Config1) & ~PMEnable;  in __rtl8169_set_wol()
1438 		RTL_W8(tp, Config1, options);  in __rtl8169_set_wol()
1444 			rtl_mod_config2(tp, 0, PME_SIGNAL);  in __rtl8169_set_wol()
1446 			rtl_mod_config2(tp, PME_SIGNAL, 0);  in __rtl8169_set_wol()
1452 	rtl_lock_config_regs(tp);  in __rtl8169_set_wol()
1454 	device_set_wakeup_enable(tp_to_dev(tp), wolopts);  in __rtl8169_set_wol()
1456 	if (tp->dash_type == RTL_DASH_NONE) {  in __rtl8169_set_wol()
1457 		rtl_set_d3_pll_down(tp, !wolopts);  in __rtl8169_set_wol()
1458 		tp->dev->wol_enabled = wolopts ? 1 : 0;  in __rtl8169_set_wol()
1464 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_wol()  local
1469 	tp->saved_wolopts = wol->wolopts;  in rtl8169_set_wol()
1470 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_set_wol()
1478 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_drvinfo()  local
1479 	struct rtl_fw *rtl_fw = tp->rtl_fw;  in rtl8169_get_drvinfo()
1482 	strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));  in rtl8169_get_drvinfo()
1497 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_fix_features()  local
1503 	    tp->mac_version > RTL_GIGA_MAC_VER_06)  in rtl8169_fix_features()
1509 static void rtl_set_rx_config_features(struct rtl8169_private *tp,  in rtl_set_rx_config_features()  argument
1512 	u32 rx_config = RTL_R32(tp, RxConfig);  in rtl_set_rx_config_features()
1519 	if (rtl_is_8125(tp)) {  in rtl_set_rx_config_features()
1526 	RTL_W32(tp, RxConfig, rx_config);  in rtl_set_rx_config_features()
1532 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_features()  local
1534 	rtl_set_rx_config_features(tp, features);  in rtl8169_set_features()
1537 		tp->cp_cmd |= RxChkSum;  in rtl8169_set_features()
1539 		tp->cp_cmd &= ~RxChkSum;  in rtl8169_set_features()
1541 	if (!rtl_is_8125(tp)) {  in rtl8169_set_features()
1543 			tp->cp_cmd |= RxVlan;  in rtl8169_set_features()
1545 			tp->cp_cmd &= ~RxVlan;  in rtl8169_set_features()
1548 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl8169_set_features()
1549 	rtl_pci_commit(tp);  in rtl8169_set_features()
1571 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_regs()  local
1572 	u32 __iomem *data = tp->mmio_addr;  in rtl8169_get_regs()
1608 	return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);  in DECLARE_RTL_COND()
1611 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)  in rtl8169_do_counters()  argument
1613 	u32 cmd = lower_32_bits(tp->counters_phys_addr);  in rtl8169_do_counters()
1615 	RTL_W32(tp, CounterAddrHigh, upper_32_bits(tp->counters_phys_addr));  in rtl8169_do_counters()
1616 	rtl_pci_commit(tp);  in rtl8169_do_counters()
1617 	RTL_W32(tp, CounterAddrLow, cmd);  in rtl8169_do_counters()
1618 	RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);  in rtl8169_do_counters()
1620 	rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);  in rtl8169_do_counters()
1623 static void rtl8169_update_counters(struct rtl8169_private *tp)  in rtl8169_update_counters()  argument
1625 	u8 val = RTL_R8(tp, ChipCmd);  in rtl8169_update_counters()
1632 		rtl8169_do_counters(tp, CounterDump);  in rtl8169_update_counters()
1635 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)  in rtl8169_init_counter_offsets()  argument
1637 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_init_counter_offsets()
1654 	if (tp->tc_offset.inited)  in rtl8169_init_counter_offsets()
1657 	if (tp->mac_version >= RTL_GIGA_MAC_VER_19) {  in rtl8169_init_counter_offsets()
1658 		rtl8169_do_counters(tp, CounterReset);  in rtl8169_init_counter_offsets()
1660 		rtl8169_update_counters(tp);  in rtl8169_init_counter_offsets()
1661 		tp->tc_offset.tx_errors = counters->tx_errors;  in rtl8169_init_counter_offsets()
1662 		tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;  in rtl8169_init_counter_offsets()
1663 		tp->tc_offset.tx_aborted = counters->tx_aborted;  in rtl8169_init_counter_offsets()
1664 		tp->tc_offset.rx_missed = counters->rx_missed;  in rtl8169_init_counter_offsets()
1667 	tp->tc_offset.inited = true;  in rtl8169_init_counter_offsets()
1673 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_ethtool_stats()  local
1676 	counters = tp->counters;  in rtl8169_get_ethtool_stats()
1677 	rtl8169_update_counters(tp);  in rtl8169_get_ethtool_stats()
1757 rtl_coalesce_info(struct rtl8169_private *tp)  in rtl_coalesce_info()  argument
1761 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_coalesce_info()
1767 	if (tp->phydev->speed == SPEED_UNKNOWN)  in rtl_coalesce_info()
1771 		if (tp->phydev->speed == ci->speed)  in rtl_coalesce_info()
1783 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_get_coalesce()  local
1788 	if (rtl_is_8125(tp))  in rtl_get_coalesce()
1794 	ci = rtl_coalesce_info(tp);  in rtl_get_coalesce()
1798 	scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];  in rtl_get_coalesce()
1800 	intrmit = RTL_R16(tp, IntrMitigate);  in rtl_get_coalesce()
1819 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,  in rtl_coalesce_choose_scale()  argument
1825 	ci = rtl_coalesce_info(tp);  in rtl_coalesce_choose_scale()
1844 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_coalesce()  local
1851 	if (rtl_is_8125(tp))  in rtl_set_coalesce()
1858 	scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);  in rtl_set_coalesce()
1890 	RTL_W16(tp, IntrMitigate, w);  in rtl_set_coalesce()
1893 	if (rtl_is_8168evl_up(tp)) {  in rtl_set_coalesce()
1896 			tp->cp_cmd |= PktCntrDisable;  in rtl_set_coalesce()
1898 			tp->cp_cmd &= ~PktCntrDisable;  in rtl_set_coalesce()
1901 	tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;  in rtl_set_coalesce()
1902 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_set_coalesce()
1903 	rtl_pci_commit(tp);  in rtl_set_coalesce()
1910 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_eee()  local
1912 	if (!rtl_supports_eee(tp))  in rtl8169_get_eee()
1915 	return phy_ethtool_get_eee(tp->phydev, data);  in rtl8169_get_eee()
1920 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_eee()  local
1923 	if (!rtl_supports_eee(tp))  in rtl8169_set_eee()
1926 	ret = phy_ethtool_set_eee(tp->phydev, data);  in rtl8169_set_eee()
1929 		tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,  in rtl8169_set_eee()
1948 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_pauseparam()  local
1951 	phy_get_pause(tp->phydev, &tx_pause, &rx_pause);  in rtl8169_get_pauseparam()
1953 	data->autoneg = tp->phydev->autoneg;  in rtl8169_get_pauseparam()
1961 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_set_pauseparam()  local
1966 	phy_set_asym_pause(tp->phydev, data->rx_pause, data->tx_pause);  in rtl8169_set_pauseparam()
1996 static void rtl_enable_eee(struct rtl8169_private *tp)  in rtl_enable_eee()  argument
1998 	struct phy_device *phydev = tp->phydev;  in rtl_enable_eee()
2002 	if (tp->eee_adv >= 0)  in rtl_enable_eee()
2003 		adv = tp->eee_adv;  in rtl_enable_eee()
2143 static void rtl_release_firmware(struct rtl8169_private *tp)  in rtl_release_firmware()  argument
2145 	if (tp->rtl_fw) {  in rtl_release_firmware()
2146 		rtl_fw_release_firmware(tp->rtl_fw);  in rtl_release_firmware()
2147 		kfree(tp->rtl_fw);  in rtl_release_firmware()
2148 		tp->rtl_fw = NULL;  in rtl_release_firmware()
2152 void r8169_apply_firmware(struct rtl8169_private *tp)  in r8169_apply_firmware()  argument
2157 	if (tp->rtl_fw) {  in r8169_apply_firmware()
2158 		rtl_fw_write_firmware(tp, tp->rtl_fw);  in r8169_apply_firmware()
2160 		tp->ocp_base = OCP_STD_PHY_BASE;  in r8169_apply_firmware()
2163 		phy_read_poll_timeout(tp->phydev, MII_BMCR, val,  in r8169_apply_firmware()
2169 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)  in rtl8168_config_eee_mac()  argument
2172 	if (tp->mac_version != RTL_GIGA_MAC_VER_38)  in rtl8168_config_eee_mac()
2173 		RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);  in rtl8168_config_eee_mac()
2175 	rtl_eri_set_bits(tp, 0x1b0, 0x0003);  in rtl8168_config_eee_mac()
2178 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)  in rtl8125a_config_eee_mac()  argument
2180 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125a_config_eee_mac()
2181 	r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));  in rtl8125a_config_eee_mac()
2184 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)  in rtl8125_set_eee_txidle_timer()  argument
2186 	RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);  in rtl8125_set_eee_txidle_timer()
2189 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)  in rtl8125b_config_eee_mac()  argument
2191 	rtl8125_set_eee_txidle_timer(tp);  in rtl8125b_config_eee_mac()
2192 	r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));  in rtl8125b_config_eee_mac()
2195 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, const u8 *addr)  in rtl_rar_exgmac_set()  argument
2197 	rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr));  in rtl_rar_exgmac_set()
2198 	rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4));  in rtl_rar_exgmac_set()
2199 	rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16);  in rtl_rar_exgmac_set()
2200 	rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2));  in rtl_rar_exgmac_set()
2203 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)  in rtl8168h_2_get_adc_bias_ioffset()  argument
2207 	r8168_mac_ocp_write(tp, 0xdd02, 0x807d);  in rtl8168h_2_get_adc_bias_ioffset()
2208 	data1 = r8168_mac_ocp_read(tp, 0xdd02);  in rtl8168h_2_get_adc_bias_ioffset()
2209 	data2 = r8168_mac_ocp_read(tp, 0xdd00);  in rtl8168h_2_get_adc_bias_ioffset()
2219 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)  in rtl_schedule_task()  argument
2221 	set_bit(flag, tp->wk.flags);  in rtl_schedule_task()
2222 	schedule_work(&tp->wk.work);  in rtl_schedule_task()
2225 static void rtl8169_init_phy(struct rtl8169_private *tp)  in rtl8169_init_phy()  argument
2227 	r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);  in rtl8169_init_phy()
2229 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {  in rtl8169_init_phy()
2230 		pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);  in rtl8169_init_phy()
2231 		pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);  in rtl8169_init_phy()
2233 		RTL_W8(tp, 0x82, 0x01);  in rtl8169_init_phy()
2236 	if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&  in rtl8169_init_phy()
2237 	    tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&  in rtl8169_init_phy()
2238 	    tp->pci_dev->subsystem_device == 0xe000)  in rtl8169_init_phy()
2239 		phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);  in rtl8169_init_phy()
2242 	phy_speed_up(tp->phydev);  in rtl8169_init_phy()
2244 	if (rtl_supports_eee(tp))  in rtl8169_init_phy()
2245 		rtl_enable_eee(tp);  in rtl8169_init_phy()
2247 	genphy_soft_reset(tp->phydev);  in rtl8169_init_phy()
2250 static void rtl_rar_set(struct rtl8169_private *tp, const u8 *addr)  in rtl_rar_set()  argument
2252 	rtl_unlock_config_regs(tp);  in rtl_rar_set()
2254 	RTL_W32(tp, MAC4, get_unaligned_le16(addr + 4));  in rtl_rar_set()
2255 	rtl_pci_commit(tp);  in rtl_rar_set()
2257 	RTL_W32(tp, MAC0, get_unaligned_le32(addr));  in rtl_rar_set()
2258 	rtl_pci_commit(tp);  in rtl_rar_set()
2260 	if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl_rar_set()
2261 		rtl_rar_exgmac_set(tp, addr);  in rtl_rar_set()
2263 	rtl_lock_config_regs(tp);  in rtl_rar_set()
2268 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_mac_address()  local
2275 	rtl_rar_set(tp, dev->dev_addr);  in rtl_set_mac_address()
2280 static void rtl_init_rxcfg(struct rtl8169_private *tp)  in rtl_init_rxcfg()  argument
2282 	switch (tp->mac_version) {  in rtl_init_rxcfg()
2285 		RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);  in rtl_init_rxcfg()
2290 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2293 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);  in rtl_init_rxcfg()
2296 		RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);  in rtl_init_rxcfg()
2299 		RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);  in rtl_init_rxcfg()
2304 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)  in rtl8169_init_ring_indexes()  argument
2306 	tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;  in rtl8169_init_ring_indexes()
2309 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_enable()  argument
2311 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168c_hw_jumbo_enable()
2312 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);  in r8168c_hw_jumbo_enable()
2315 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168c_hw_jumbo_disable()  argument
2317 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168c_hw_jumbo_disable()
2318 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);  in r8168c_hw_jumbo_disable()
2321 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_enable()  argument
2323 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168dp_hw_jumbo_enable()
2326 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168dp_hw_jumbo_disable()  argument
2328 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168dp_hw_jumbo_disable()
2331 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_enable()  argument
2333 	RTL_W8(tp, MaxTxPacketSize, 0x24);  in r8168e_hw_jumbo_enable()
2334 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);  in r8168e_hw_jumbo_enable()
2335 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);  in r8168e_hw_jumbo_enable()
2338 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168e_hw_jumbo_disable()  argument
2340 	RTL_W8(tp, MaxTxPacketSize, 0x3f);  in r8168e_hw_jumbo_disable()
2341 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);  in r8168e_hw_jumbo_disable()
2342 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);  in r8168e_hw_jumbo_disable()
2345 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_enable()  argument
2347 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));  in r8168b_1_hw_jumbo_enable()
2350 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)  in r8168b_1_hw_jumbo_disable()  argument
2352 	RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));  in r8168b_1_hw_jumbo_disable()
2355 static void rtl_jumbo_config(struct rtl8169_private *tp)  in rtl_jumbo_config()  argument
2357 	bool jumbo = tp->dev->mtu > ETH_DATA_LEN;  in rtl_jumbo_config()
2360 	rtl_unlock_config_regs(tp);  in rtl_jumbo_config()
2361 	switch (tp->mac_version) {  in rtl_jumbo_config()
2365 			r8168b_1_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2367 			r8168b_1_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2373 			r8168c_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2375 			r8168c_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2380 			r8168dp_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2382 			r8168dp_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2386 			r8168e_hw_jumbo_enable(tp);  in rtl_jumbo_config()
2388 			r8168e_hw_jumbo_disable(tp);  in rtl_jumbo_config()
2393 	rtl_lock_config_regs(tp);  in rtl_jumbo_config()
2395 	if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)  in rtl_jumbo_config()
2396 		pcie_set_readrq(tp->pci_dev, readrq);  in rtl_jumbo_config()
2401 				   tp->phydev->advertising);  in rtl_jumbo_config()
2403 				   tp->phydev->advertising);  in rtl_jumbo_config()
2404 		phy_start_aneg(tp->phydev);  in rtl_jumbo_config()
2410 	return RTL_R8(tp, ChipCmd) & CmdReset;  in DECLARE_RTL_COND()
2413 static void rtl_hw_reset(struct rtl8169_private *tp)  in rtl_hw_reset()  argument
2415 	RTL_W8(tp, ChipCmd, CmdReset);  in rtl_hw_reset()
2417 	rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);  in rtl_hw_reset()
2420 static void rtl_request_firmware(struct rtl8169_private *tp)  in rtl_request_firmware()  argument
2425 	if (tp->rtl_fw || !tp->fw_name)  in rtl_request_firmware()
2436 	rtl_fw->fw_name = tp->fw_name;  in rtl_request_firmware()
2437 	rtl_fw->dev = tp_to_dev(tp);  in rtl_request_firmware()
2442 		tp->rtl_fw = rtl_fw;  in rtl_request_firmware()
2445 static void rtl_rx_close(struct rtl8169_private *tp)  in rtl_rx_close()  argument
2447 	RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);  in rtl_rx_close()
2452 	return RTL_R8(tp, TxPoll) & NPQ;  in DECLARE_RTL_COND()
2457 	return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;  in DECLARE_RTL_COND()
2462 	return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;  in DECLARE_RTL_COND()
2468 	return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;  in DECLARE_RTL_COND()
2471 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)  in rtl_wait_txrx_fifo_empty()  argument
2473 	switch (tp->mac_version) {  in rtl_wait_txrx_fifo_empty()
2475 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2476 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2479 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2482 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl_wait_txrx_fifo_empty()
2483 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);  in rtl_wait_txrx_fifo_empty()
2484 		rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);  in rtl_wait_txrx_fifo_empty()
2491 static void rtl_disable_rxdvgate(struct rtl8169_private *tp)  in rtl_disable_rxdvgate()  argument
2493 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);  in rtl_disable_rxdvgate()
2496 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)  in rtl_enable_rxdvgate()  argument
2498 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);  in rtl_enable_rxdvgate()
2500 	rtl_wait_txrx_fifo_empty(tp);  in rtl_enable_rxdvgate()
2503 static void rtl_wol_enable_rx(struct rtl8169_private *tp)  in rtl_wol_enable_rx()  argument
2505 	if (tp->mac_version >= RTL_GIGA_MAC_VER_25)  in rtl_wol_enable_rx()
2506 		RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |  in rtl_wol_enable_rx()
2509 	if (tp->mac_version >= RTL_GIGA_MAC_VER_40)  in rtl_wol_enable_rx()
2510 		rtl_disable_rxdvgate(tp);  in rtl_wol_enable_rx()
2513 static void rtl_prepare_power_down(struct rtl8169_private *tp)  in rtl_prepare_power_down()  argument
2515 	if (tp->dash_type != RTL_DASH_NONE)  in rtl_prepare_power_down()
2518 	if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||  in rtl_prepare_power_down()
2519 	    tp->mac_version == RTL_GIGA_MAC_VER_33)  in rtl_prepare_power_down()
2520 		rtl_ephy_write(tp, 0x19, 0xff64);  in rtl_prepare_power_down()
2522 	if (device_may_wakeup(tp_to_dev(tp))) {  in rtl_prepare_power_down()
2523 		phy_speed_down(tp->phydev, false);  in rtl_prepare_power_down()
2524 		rtl_wol_enable_rx(tp);  in rtl_prepare_power_down()
2528 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)  in rtl_set_tx_config_registers()  argument
2533 	if (rtl_is_8168evl_up(tp))  in rtl_set_tx_config_registers()
2536 	RTL_W32(tp, TxConfig, val);  in rtl_set_tx_config_registers()
2539 static void rtl_set_rx_max_size(struct rtl8169_private *tp)  in rtl_set_rx_max_size()  argument
2542 	RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);  in rtl_set_rx_max_size()
2545 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)  in rtl_set_rx_tx_desc_registers()  argument
2552 	RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2553 	RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2554 	RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);  in rtl_set_rx_tx_desc_registers()
2555 	RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));  in rtl_set_rx_tx_desc_registers()
2558 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)  in rtl8169_set_magic_reg()  argument
2562 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl8169_set_magic_reg()
2564 	else if (tp->mac_version == RTL_GIGA_MAC_VER_06)  in rtl8169_set_magic_reg()
2569 	if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)  in rtl8169_set_magic_reg()
2572 	RTL_W32(tp, 0x7c, val);  in rtl8169_set_magic_reg()
2580 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_set_rx_mode()  local
2587 		   tp->mac_version == RTL_GIGA_MAC_VER_35) {  in rtl_set_rx_mode()
2600 		if (tp->mac_version > RTL_GIGA_MAC_VER_06) {  in rtl_set_rx_mode()
2607 	RTL_W32(tp, MAR0 + 4, mc_filter[1]);  in rtl_set_rx_mode()
2608 	RTL_W32(tp, MAR0 + 0, mc_filter[0]);  in rtl_set_rx_mode()
2610 	tmp = RTL_R32(tp, RxConfig);  in rtl_set_rx_mode()
2611 	RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);  in rtl_set_rx_mode()
2616 	return RTL_R32(tp, CSIAR) & CSIAR_FLAG;  in DECLARE_RTL_COND()
2619 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)  in rtl_csi_write()  argument
2621 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_write()
2623 	RTL_W32(tp, CSIDR, value);  in rtl_csi_write()
2624 	RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |  in rtl_csi_write()
2627 	rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);  in rtl_csi_write()
2630 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)  in rtl_csi_read()  argument
2632 	u32 func = PCI_FUNC(tp->pci_dev->devfn);  in rtl_csi_read()
2634 	RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |  in rtl_csi_read()
2637 	return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?  in rtl_csi_read()
2638 		RTL_R32(tp, CSIDR) : ~0;  in rtl_csi_read()
2641 static void rtl_set_aspm_entry_latency(struct rtl8169_private *tp, u8 val)  in rtl_set_aspm_entry_latency()  argument
2643 	struct pci_dev *pdev = tp->pci_dev;  in rtl_set_aspm_entry_latency()
2656 	netdev_notice_once(tp->dev,  in rtl_set_aspm_entry_latency()
2658 	csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;  in rtl_set_aspm_entry_latency()
2659 	rtl_csi_write(tp, 0x070c, csi | val << 24);  in rtl_set_aspm_entry_latency()
2662 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)  in rtl_set_def_aspm_entry_latency()  argument
2665 	rtl_set_aspm_entry_latency(tp, 0x27);  in rtl_set_def_aspm_entry_latency()
2674 static void __rtl_ephy_init(struct rtl8169_private *tp,  in __rtl_ephy_init()  argument
2680 		w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;  in __rtl_ephy_init()
2681 		rtl_ephy_write(tp, e->offset, w);  in __rtl_ephy_init()
2686 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))  argument
2688 static void rtl_disable_clock_request(struct rtl8169_private *tp)  in rtl_disable_clock_request()  argument
2690 	pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_disable_clock_request()
2694 static void rtl_enable_clock_request(struct rtl8169_private *tp)  in rtl_enable_clock_request()  argument
2696 	pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,  in rtl_enable_clock_request()
2700 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)  in rtl_pcie_state_l2l3_disable()  argument
2703 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);  in rtl_pcie_state_l2l3_disable()
2706 static void rtl_enable_exit_l1(struct rtl8169_private *tp)  in rtl_enable_exit_l1()  argument
2716 	switch (tp->mac_version) {  in rtl_enable_exit_l1()
2718 		rtl_eri_set_bits(tp, 0xd4, 0x1f00);  in rtl_enable_exit_l1()
2721 		rtl_eri_set_bits(tp, 0xd4, 0x0c00);  in rtl_enable_exit_l1()
2724 		r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80);  in rtl_enable_exit_l1()
2731 static void rtl_disable_exit_l1(struct rtl8169_private *tp)  in rtl_disable_exit_l1()  argument
2733 	switch (tp->mac_version) {  in rtl_disable_exit_l1()
2735 		rtl_eri_clear_bits(tp, 0xd4, 0x1f00);  in rtl_disable_exit_l1()
2738 		r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);  in rtl_disable_exit_l1()
2745 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)  in rtl_hw_aspm_clkreq_enable()  argument
2747 	if (tp->mac_version < RTL_GIGA_MAC_VER_32)  in rtl_hw_aspm_clkreq_enable()
2751 	if (enable && tp->aspm_manageable) {  in rtl_hw_aspm_clkreq_enable()
2755 		if (tp->mac_version == RTL_GIGA_MAC_VER_42 ||  in rtl_hw_aspm_clkreq_enable()
2756 		    tp->mac_version == RTL_GIGA_MAC_VER_43)  in rtl_hw_aspm_clkreq_enable()
2759 		rtl_mod_config5(tp, 0, ASPM_en);  in rtl_hw_aspm_clkreq_enable()
2760 		rtl_mod_config2(tp, 0, ClkReqEn);  in rtl_hw_aspm_clkreq_enable()
2762 		switch (tp->mac_version) {  in rtl_hw_aspm_clkreq_enable()
2766 			r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);  in rtl_hw_aspm_clkreq_enable()
2768 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));  in rtl_hw_aspm_clkreq_enable()
2774 		switch (tp->mac_version) {  in rtl_hw_aspm_clkreq_enable()
2777 			r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);  in rtl_hw_aspm_clkreq_enable()
2783 		rtl_mod_config2(tp, ClkReqEn, 0);  in rtl_hw_aspm_clkreq_enable()
2784 		rtl_mod_config5(tp, ASPM_en, 0);  in rtl_hw_aspm_clkreq_enable()
2788 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,  in rtl_set_fifo_size()  argument
2794 	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);  in rtl_set_fifo_size()
2795 	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);  in rtl_set_fifo_size()
2798 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,  in rtl8168g_set_pause_thresholds()  argument
2802 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);  in rtl8168g_set_pause_thresholds()
2803 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);  in rtl8168g_set_pause_thresholds()
2806 static void rtl_hw_start_8168b(struct rtl8169_private *tp)  in rtl_hw_start_8168b()  argument
2808 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168b()
2811 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)  in __rtl_hw_start_8168cp()  argument
2813 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);  in __rtl_hw_start_8168cp()
2815 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in __rtl_hw_start_8168cp()
2817 	rtl_disable_clock_request(tp);  in __rtl_hw_start_8168cp()
2820 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_1()  argument
2830 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_1()
2832 	rtl_ephy_init(tp, e_info_8168cp);  in rtl_hw_start_8168cp_1()
2834 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168cp_1()
2837 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_2()  argument
2839 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_2()
2841 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_2()
2844 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)  in rtl_hw_start_8168cp_3()  argument
2846 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168cp_3()
2848 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8168cp_3()
2851 	RTL_W8(tp, DBG_REG, 0x20);  in rtl_hw_start_8168cp_3()
2854 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)  in rtl_hw_start_8168c_1()  argument
2862 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_1()
2864 	RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);  in rtl_hw_start_8168c_1()
2866 	rtl_ephy_init(tp, e_info_8168c_1);  in rtl_hw_start_8168c_1()
2868 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_1()
2871 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)  in rtl_hw_start_8168c_2()  argument
2878 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_2()
2880 	rtl_ephy_init(tp, e_info_8168c_2);  in rtl_hw_start_8168c_2()
2882 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_2()
2885 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)  in rtl_hw_start_8168c_4()  argument
2887 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168c_4()
2889 	__rtl_hw_start_8168cp(tp);  in rtl_hw_start_8168c_4()
2892 static void rtl_hw_start_8168d(struct rtl8169_private *tp)  in rtl_hw_start_8168d()  argument
2894 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d()
2896 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168d()
2899 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)  in rtl_hw_start_8168d_4()  argument
2908 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168d_4()
2910 	rtl_ephy_init(tp, e_info_8168d_4);  in rtl_hw_start_8168d_4()
2912 	rtl_enable_clock_request(tp);  in rtl_hw_start_8168d_4()
2915 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)  in rtl_hw_start_8168e_1()  argument
2933 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_1()
2935 	rtl_ephy_init(tp, e_info_8168e_1);  in rtl_hw_start_8168e_1()
2937 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_1()
2940 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);  in rtl_hw_start_8168e_1()
2941 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);  in rtl_hw_start_8168e_1()
2943 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168e_1()
2946 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)  in rtl_hw_start_8168e_2()  argument
2955 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168e_2()
2957 	rtl_ephy_init(tp, e_info_8168e_2);  in rtl_hw_start_8168e_2()
2959 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168e_2()
2960 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168e_2()
2961 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168e_2()
2962 	rtl_eri_set_bits(tp, 0x1d0, BIT(1));  in rtl_hw_start_8168e_2()
2963 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168e_2()
2964 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168e_2()
2965 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168e_2()
2966 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);  in rtl_hw_start_8168e_2()
2968 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168e_2()
2970 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168e_2()
2972 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168e_2()
2974 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168e_2()
2975 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168e_2()
2976 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168e_2()
2979 static void rtl_hw_start_8168f(struct rtl8169_private *tp)  in rtl_hw_start_8168f()  argument
2981 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168f()
2983 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168f()
2984 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);  in rtl_hw_start_8168f()
2985 	rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);  in rtl_hw_start_8168f()
2986 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168f()
2987 	rtl_eri_set_bits(tp, 0x1b0, BIT(4));  in rtl_hw_start_8168f()
2988 	rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));  in rtl_hw_start_8168f()
2989 	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);  in rtl_hw_start_8168f()
2990 	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);  in rtl_hw_start_8168f()
2992 	rtl_disable_clock_request(tp);  in rtl_hw_start_8168f()
2994 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8168f()
2995 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8168f()
2996 	RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);  in rtl_hw_start_8168f()
2997 	rtl_mod_config5(tp, Spi_en, 0);  in rtl_hw_start_8168f()
2999 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168f()
3002 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)  in rtl_hw_start_8168f_1()  argument
3013 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8168f_1()
3015 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8168f_1()
3018 static void rtl_hw_start_8411(struct rtl8169_private *tp)  in rtl_hw_start_8411()  argument
3028 	rtl_hw_start_8168f(tp);  in rtl_hw_start_8411()
3029 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8411()
3031 	rtl_ephy_init(tp, e_info_8168f_1);  in rtl_hw_start_8411()
3034 static void rtl_hw_start_8168g(struct rtl8169_private *tp)  in rtl_hw_start_8168g()  argument
3036 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168g()
3037 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168g()
3039 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168g()
3041 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168g()
3042 	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);  in rtl_hw_start_8168g()
3044 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168g()
3046 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
3047 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168g()
3049 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168g()
3051 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168g()
3052 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168g()
3054 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168g()
3057 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)  in rtl_hw_start_8168g_1()  argument
3066 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_1()
3067 	rtl_ephy_init(tp, e_info_8168g_1);  in rtl_hw_start_8168g_1()
3070 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)  in rtl_hw_start_8168g_2()  argument
3084 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8168g_2()
3085 	rtl_ephy_init(tp, e_info_8168g_2);  in rtl_hw_start_8168g_2()
3088 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)  in rtl_hw_start_8411_2()  argument
3103 	rtl_hw_start_8168g(tp);  in rtl_hw_start_8411_2()
3105 	rtl_ephy_init(tp, e_info_8411_2);  in rtl_hw_start_8411_2()
3110 	r8168_mac_ocp_write(tp, 0xFC28, 0x0000);  in rtl_hw_start_8411_2()
3111 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);  in rtl_hw_start_8411_2()
3112 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);  in rtl_hw_start_8411_2()
3113 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);  in rtl_hw_start_8411_2()
3114 	r8168_mac_ocp_write(tp, 0xFC30, 0x0000);  in rtl_hw_start_8411_2()
3115 	r8168_mac_ocp_write(tp, 0xFC32, 0x0000);  in rtl_hw_start_8411_2()
3116 	r8168_mac_ocp_write(tp, 0xFC34, 0x0000);  in rtl_hw_start_8411_2()
3117 	r8168_mac_ocp_write(tp, 0xFC36, 0x0000);  in rtl_hw_start_8411_2()
3119 	r8168_mac_ocp_write(tp, 0xFC26, 0x0000);  in rtl_hw_start_8411_2()
3121 	r8168_mac_ocp_write(tp, 0xF800, 0xE008);  in rtl_hw_start_8411_2()
3122 	r8168_mac_ocp_write(tp, 0xF802, 0xE00A);  in rtl_hw_start_8411_2()
3123 	r8168_mac_ocp_write(tp, 0xF804, 0xE00C);  in rtl_hw_start_8411_2()
3124 	r8168_mac_ocp_write(tp, 0xF806, 0xE00E);  in rtl_hw_start_8411_2()
3125 	r8168_mac_ocp_write(tp, 0xF808, 0xE027);  in rtl_hw_start_8411_2()
3126 	r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);  in rtl_hw_start_8411_2()
3127 	r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);  in rtl_hw_start_8411_2()
3128 	r8168_mac_ocp_write(tp, 0xF80E, 0xE065);  in rtl_hw_start_8411_2()
3129 	r8168_mac_ocp_write(tp, 0xF810, 0xC602);  in rtl_hw_start_8411_2()
3130 	r8168_mac_ocp_write(tp, 0xF812, 0xBE00);  in rtl_hw_start_8411_2()
3131 	r8168_mac_ocp_write(tp, 0xF814, 0x0000);  in rtl_hw_start_8411_2()
3132 	r8168_mac_ocp_write(tp, 0xF816, 0xC502);  in rtl_hw_start_8411_2()
3133 	r8168_mac_ocp_write(tp, 0xF818, 0xBD00);  in rtl_hw_start_8411_2()
3134 	r8168_mac_ocp_write(tp, 0xF81A, 0x074C);  in rtl_hw_start_8411_2()
3135 	r8168_mac_ocp_write(tp, 0xF81C, 0xC302);  in rtl_hw_start_8411_2()
3136 	r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);  in rtl_hw_start_8411_2()
3137 	r8168_mac_ocp_write(tp, 0xF820, 0x080A);  in rtl_hw_start_8411_2()
3138 	r8168_mac_ocp_write(tp, 0xF822, 0x6420);  in rtl_hw_start_8411_2()
3139 	r8168_mac_ocp_write(tp, 0xF824, 0x48C2);  in rtl_hw_start_8411_2()
3140 	r8168_mac_ocp_write(tp, 0xF826, 0x8C20);  in rtl_hw_start_8411_2()
3141 	r8168_mac_ocp_write(tp, 0xF828, 0xC516);  in rtl_hw_start_8411_2()
3142 	r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);  in rtl_hw_start_8411_2()
3143 	r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);  in rtl_hw_start_8411_2()
3144 	r8168_mac_ocp_write(tp, 0xF82E, 0xF009);  in rtl_hw_start_8411_2()
3145 	r8168_mac_ocp_write(tp, 0xF830, 0x74A2);  in rtl_hw_start_8411_2()
3146 	r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);  in rtl_hw_start_8411_2()
3147 	r8168_mac_ocp_write(tp, 0xF834, 0x74A0);  in rtl_hw_start_8411_2()
3148 	r8168_mac_ocp_write(tp, 0xF836, 0xC50E);  in rtl_hw_start_8411_2()
3149 	r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);  in rtl_hw_start_8411_2()
3150 	r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);  in rtl_hw_start_8411_2()
3151 	r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);  in rtl_hw_start_8411_2()
3152 	r8168_mac_ocp_write(tp, 0xF83E, 0xE006);  in rtl_hw_start_8411_2()
3153 	r8168_mac_ocp_write(tp, 0xF840, 0x74F8);  in rtl_hw_start_8411_2()
3154 	r8168_mac_ocp_write(tp, 0xF842, 0x48C4);  in rtl_hw_start_8411_2()
3155 	r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);  in rtl_hw_start_8411_2()
3156 	r8168_mac_ocp_write(tp, 0xF846, 0xC404);  in rtl_hw_start_8411_2()
3157 	r8168_mac_ocp_write(tp, 0xF848, 0xBC00);  in rtl_hw_start_8411_2()
3158 	r8168_mac_ocp_write(tp, 0xF84A, 0xC403);  in rtl_hw_start_8411_2()
3159 	r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);  in rtl_hw_start_8411_2()
3160 	r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);  in rtl_hw_start_8411_2()
3161 	r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);  in rtl_hw_start_8411_2()
3162 	r8168_mac_ocp_write(tp, 0xF852, 0xE434);  in rtl_hw_start_8411_2()
3163 	r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);  in rtl_hw_start_8411_2()
3164 	r8168_mac_ocp_write(tp, 0xF856, 0x49D9);  in rtl_hw_start_8411_2()
3165 	r8168_mac_ocp_write(tp, 0xF858, 0xF01F);  in rtl_hw_start_8411_2()
3166 	r8168_mac_ocp_write(tp, 0xF85A, 0xC526);  in rtl_hw_start_8411_2()
3167 	r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);  in rtl_hw_start_8411_2()
3168 	r8168_mac_ocp_write(tp, 0xF85E, 0x1400);  in rtl_hw_start_8411_2()
3169 	r8168_mac_ocp_write(tp, 0xF860, 0xF007);  in rtl_hw_start_8411_2()
3170 	r8168_mac_ocp_write(tp, 0xF862, 0x0C01);  in rtl_hw_start_8411_2()
3171 	r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);  in rtl_hw_start_8411_2()
3172 	r8168_mac_ocp_write(tp, 0xF866, 0x1C15);  in rtl_hw_start_8411_2()
3173 	r8168_mac_ocp_write(tp, 0xF868, 0xC51B);  in rtl_hw_start_8411_2()
3174 	r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);  in rtl_hw_start_8411_2()
3175 	r8168_mac_ocp_write(tp, 0xF86C, 0xE013);  in rtl_hw_start_8411_2()
3176 	r8168_mac_ocp_write(tp, 0xF86E, 0xC519);  in rtl_hw_start_8411_2()
3177 	r8168_mac_ocp_write(tp, 0xF870, 0x74A0);  in rtl_hw_start_8411_2()
3178 	r8168_mac_ocp_write(tp, 0xF872, 0x48C4);  in rtl_hw_start_8411_2()
3179 	r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);  in rtl_hw_start_8411_2()
3180 	r8168_mac_ocp_write(tp, 0xF876, 0xC516);  in rtl_hw_start_8411_2()
3181 	r8168_mac_ocp_write(tp, 0xF878, 0x74A4);  in rtl_hw_start_8411_2()
3182 	r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);  in rtl_hw_start_8411_2()
3183 	r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);  in rtl_hw_start_8411_2()
3184 	r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);  in rtl_hw_start_8411_2()
3185 	r8168_mac_ocp_write(tp, 0xF880, 0xC512);  in rtl_hw_start_8411_2()
3186 	r8168_mac_ocp_write(tp, 0xF882, 0x1B00);  in rtl_hw_start_8411_2()
3187 	r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);  in rtl_hw_start_8411_2()
3188 	r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);  in rtl_hw_start_8411_2()
3189 	r8168_mac_ocp_write(tp, 0xF888, 0x483F);  in rtl_hw_start_8411_2()
3190 	r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);  in rtl_hw_start_8411_2()
3191 	r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);  in rtl_hw_start_8411_2()
3192 	r8168_mac_ocp_write(tp, 0xF88E, 0xC508);  in rtl_hw_start_8411_2()
3193 	r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);  in rtl_hw_start_8411_2()
3194 	r8168_mac_ocp_write(tp, 0xF892, 0xC505);  in rtl_hw_start_8411_2()
3195 	r8168_mac_ocp_write(tp, 0xF894, 0xBD00);  in rtl_hw_start_8411_2()
3196 	r8168_mac_ocp_write(tp, 0xF896, 0xC502);  in rtl_hw_start_8411_2()
3197 	r8168_mac_ocp_write(tp, 0xF898, 0xBD00);  in rtl_hw_start_8411_2()
3198 	r8168_mac_ocp_write(tp, 0xF89A, 0x0300);  in rtl_hw_start_8411_2()
3199 	r8168_mac_ocp_write(tp, 0xF89C, 0x051E);  in rtl_hw_start_8411_2()
3200 	r8168_mac_ocp_write(tp, 0xF89E, 0xE434);  in rtl_hw_start_8411_2()
3201 	r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);  in rtl_hw_start_8411_2()
3202 	r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);  in rtl_hw_start_8411_2()
3203 	r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);  in rtl_hw_start_8411_2()
3204 	r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);  in rtl_hw_start_8411_2()
3205 	r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);  in rtl_hw_start_8411_2()
3206 	r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);  in rtl_hw_start_8411_2()
3207 	r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);  in rtl_hw_start_8411_2()
3208 	r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);  in rtl_hw_start_8411_2()
3209 	r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);  in rtl_hw_start_8411_2()
3210 	r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);  in rtl_hw_start_8411_2()
3211 	r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);  in rtl_hw_start_8411_2()
3212 	r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);  in rtl_hw_start_8411_2()
3213 	r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);  in rtl_hw_start_8411_2()
3214 	r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);  in rtl_hw_start_8411_2()
3215 	r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);  in rtl_hw_start_8411_2()
3216 	r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);  in rtl_hw_start_8411_2()
3217 	r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);  in rtl_hw_start_8411_2()
3218 	r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);  in rtl_hw_start_8411_2()
3219 	r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);  in rtl_hw_start_8411_2()
3220 	r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);  in rtl_hw_start_8411_2()
3221 	r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);  in rtl_hw_start_8411_2()
3222 	r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);  in rtl_hw_start_8411_2()
3223 	r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);  in rtl_hw_start_8411_2()
3224 	r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);  in rtl_hw_start_8411_2()
3225 	r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);  in rtl_hw_start_8411_2()
3226 	r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);  in rtl_hw_start_8411_2()
3227 	r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);  in rtl_hw_start_8411_2()
3228 	r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);  in rtl_hw_start_8411_2()
3229 	r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);  in rtl_hw_start_8411_2()
3230 	r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);  in rtl_hw_start_8411_2()
3231 	r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);  in rtl_hw_start_8411_2()
3233 	r8168_mac_ocp_write(tp, 0xFC26, 0x8000);  in rtl_hw_start_8411_2()
3235 	r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);  in rtl_hw_start_8411_2()
3236 	r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);  in rtl_hw_start_8411_2()
3237 	r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);  in rtl_hw_start_8411_2()
3238 	r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);  in rtl_hw_start_8411_2()
3239 	r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);  in rtl_hw_start_8411_2()
3240 	r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);  in rtl_hw_start_8411_2()
3241 	r8168_mac_ocp_write(tp, 0xFC36, 0x012D);  in rtl_hw_start_8411_2()
3244 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)  in rtl_hw_start_8168h_1()  argument
3256 	rtl_ephy_init(tp, e_info_8168h_1);  in rtl_hw_start_8168h_1()
3258 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168h_1()
3259 	rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);  in rtl_hw_start_8168h_1()
3261 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168h_1()
3263 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168h_1()
3265 	rtl_eri_set_bits(tp, 0xdc, 0x001c);  in rtl_hw_start_8168h_1()
3267 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168h_1()
3269 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168h_1()
3271 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3272 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168h_1()
3274 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168h_1()
3276 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168h_1()
3277 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168h_1()
3279 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168h_1()
3281 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8168h_1()
3283 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168h_1()
3285 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8168h_1()
3291 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8168h_1()
3294 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8168h_1()
3295 	r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);  in rtl_hw_start_8168h_1()
3296 	r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);  in rtl_hw_start_8168h_1()
3297 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8168h_1()
3299 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8168h_1()
3300 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8168h_1()
3301 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8168h_1()
3302 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8168h_1()
3305 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)  in rtl_hw_start_8168ep()  argument
3307 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8168ep()
3309 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8168ep()
3310 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8168ep()
3312 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8168ep()
3314 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8168ep()
3316 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8168ep()
3318 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8168ep()
3320 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3321 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8168ep()
3323 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8168ep()
3325 	rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);  in rtl_hw_start_8168ep()
3327 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8168ep()
3329 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8168ep()
3332 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)  in rtl_hw_start_8168ep_3()  argument
3341 	rtl_ephy_init(tp, e_info_8168ep_3);  in rtl_hw_start_8168ep_3()
3343 	rtl_hw_start_8168ep(tp);  in rtl_hw_start_8168ep_3()
3345 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8168ep_3()
3346 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8168ep_3()
3348 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);  in rtl_hw_start_8168ep_3()
3349 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8168ep_3()
3350 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8168ep_3()
3353 static void rtl_hw_start_8117(struct rtl8169_private *tp)  in rtl_hw_start_8117()  argument
3361 	rtl8168ep_stop_cmac(tp);  in rtl_hw_start_8117()
3362 	rtl_ephy_init(tp, e_info_8117);  in rtl_hw_start_8117()
3364 	rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);  in rtl_hw_start_8117()
3365 	rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);  in rtl_hw_start_8117()
3367 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8117()
3369 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8117()
3371 	rtl_eri_set_bits(tp, 0xd4, 0x0010);  in rtl_hw_start_8117()
3373 	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);  in rtl_hw_start_8117()
3375 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8117()
3377 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3378 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8117()
3380 	rtl8168_config_eee_mac(tp);  in rtl_hw_start_8117()
3382 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8117()
3383 	RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);  in rtl_hw_start_8117()
3385 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);  in rtl_hw_start_8117()
3387 	rtl_eri_clear_bits(tp, 0x1b0, BIT(12));  in rtl_hw_start_8117()
3389 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8117()
3391 	rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;  in rtl_hw_start_8117()
3396 		r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);  in rtl_hw_start_8117()
3399 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);  in rtl_hw_start_8117()
3400 	r8168_mac_ocp_write(tp, 0xea80, 0x0003);  in rtl_hw_start_8117()
3401 	r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);  in rtl_hw_start_8117()
3402 	r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);  in rtl_hw_start_8117()
3404 	r8168_mac_ocp_write(tp, 0xe63e, 0x0001);  in rtl_hw_start_8117()
3405 	r8168_mac_ocp_write(tp, 0xe63e, 0x0000);  in rtl_hw_start_8117()
3406 	r8168_mac_ocp_write(tp, 0xc094, 0x0000);  in rtl_hw_start_8117()
3407 	r8168_mac_ocp_write(tp, 0xc09e, 0x0000);  in rtl_hw_start_8117()
3410 	r8169_apply_firmware(tp);  in rtl_hw_start_8117()
3413 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)  in rtl_hw_start_8102e_1()  argument
3427 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_1()
3429 	RTL_W8(tp, DBG_REG, FIX_NAK_1);  in rtl_hw_start_8102e_1()
3431 	RTL_W8(tp, Config1,  in rtl_hw_start_8102e_1()
3433 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_1()
3435 	cfg1 = RTL_R8(tp, Config1);  in rtl_hw_start_8102e_1()
3437 		RTL_W8(tp, Config1, cfg1 & ~LEDS0);  in rtl_hw_start_8102e_1()
3439 	rtl_ephy_init(tp, e_info_8102e_1);  in rtl_hw_start_8102e_1()
3442 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)  in rtl_hw_start_8102e_2()  argument
3444 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8102e_2()
3446 	RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);  in rtl_hw_start_8102e_2()
3447 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8102e_2()
3450 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)  in rtl_hw_start_8102e_3()  argument
3452 	rtl_hw_start_8102e_2(tp);  in rtl_hw_start_8102e_3()
3454 	rtl_ephy_write(tp, 0x03, 0xc2f9);  in rtl_hw_start_8102e_3()
3457 static void rtl_hw_start_8401(struct rtl8169_private *tp)  in rtl_hw_start_8401()  argument
3466 	rtl_ephy_init(tp, e_info_8401);  in rtl_hw_start_8401()
3467 	RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);  in rtl_hw_start_8401()
3470 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)  in rtl_hw_start_8105e_1()  argument
3484 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8105e_1()
3487 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);  in rtl_hw_start_8105e_1()
3489 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8105e_1()
3490 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);  in rtl_hw_start_8105e_1()
3492 	rtl_ephy_init(tp, e_info_8105e_1);  in rtl_hw_start_8105e_1()
3494 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8105e_1()
3497 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)  in rtl_hw_start_8105e_2()  argument
3499 	rtl_hw_start_8105e_1(tp);  in rtl_hw_start_8105e_2()
3500 	rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);  in rtl_hw_start_8105e_2()
3503 static void rtl_hw_start_8402(struct rtl8169_private *tp)  in rtl_hw_start_8402()  argument
3510 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8402()
3513 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8402()
3515 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_start_8402()
3517 	rtl_ephy_init(tp, e_info_8402);  in rtl_hw_start_8402()
3519 	rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);  in rtl_hw_start_8402()
3520 	rtl_reset_packet_filter(tp);  in rtl_hw_start_8402()
3521 	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3522 	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3523 	rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);  in rtl_hw_start_8402()
3526 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8402()
3528 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8402()
3531 static void rtl_hw_start_8106(struct rtl8169_private *tp)  in rtl_hw_start_8106()  argument
3534 	RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);  in rtl_hw_start_8106()
3536 	RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);  in rtl_hw_start_8106()
3537 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);  in rtl_hw_start_8106()
3538 	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);  in rtl_hw_start_8106()
3541 	rtl_set_aspm_entry_latency(tp, 0x2f);  in rtl_hw_start_8106()
3543 	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3546 	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);  in rtl_hw_start_8106()
3548 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8106()
3553 	return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);  in DECLARE_RTL_COND()
3556 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)  in rtl_hw_start_8125_common()  argument
3558 	rtl_pcie_state_l2l3_disable(tp);  in rtl_hw_start_8125_common()
3560 	RTL_W16(tp, 0x382, 0x221b);  in rtl_hw_start_8125_common()
3561 	RTL_W8(tp, 0x4500, 0);  in rtl_hw_start_8125_common()
3562 	RTL_W16(tp, 0x4800, 0);  in rtl_hw_start_8125_common()
3565 	r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);  in rtl_hw_start_8125_common()
3567 	RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);  in rtl_hw_start_8125_common()
3569 	r8168_mac_ocp_write(tp, 0xc140, 0xffff);  in rtl_hw_start_8125_common()
3570 	r8168_mac_ocp_write(tp, 0xc142, 0xffff);  in rtl_hw_start_8125_common()
3572 	r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);  in rtl_hw_start_8125_common()
3573 	r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);  in rtl_hw_start_8125_common()
3574 	r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);  in rtl_hw_start_8125_common()
3577 	r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3579 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3580 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);  in rtl_hw_start_8125_common()
3582 		r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);  in rtl_hw_start_8125_common()
3584 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3585 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);  in rtl_hw_start_8125_common()
3587 		r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);  in rtl_hw_start_8125_common()
3589 	r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);  in rtl_hw_start_8125_common()
3590 	r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);  in rtl_hw_start_8125_common()
3591 	r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);  in rtl_hw_start_8125_common()
3592 	r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);  in rtl_hw_start_8125_common()
3593 	r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);  in rtl_hw_start_8125_common()
3594 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);  in rtl_hw_start_8125_common()
3595 	r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);  in rtl_hw_start_8125_common()
3596 	r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);  in rtl_hw_start_8125_common()
3597 	r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);  in rtl_hw_start_8125_common()
3599 	r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);  in rtl_hw_start_8125_common()
3600 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);  in rtl_hw_start_8125_common()
3602 	r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);  in rtl_hw_start_8125_common()
3603 	RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);  in rtl_hw_start_8125_common()
3605 	r8168_mac_ocp_write(tp, 0xe098, 0xc302);  in rtl_hw_start_8125_common()
3607 	rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);  in rtl_hw_start_8125_common()
3609 	if (tp->mac_version == RTL_GIGA_MAC_VER_63)  in rtl_hw_start_8125_common()
3610 		rtl8125b_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3612 		rtl8125a_config_eee_mac(tp);  in rtl_hw_start_8125_common()
3614 	rtl_disable_rxdvgate(tp);  in rtl_hw_start_8125_common()
3617 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)  in rtl_hw_start_8125a_2()  argument
3635 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125a_2()
3636 	rtl_ephy_init(tp, e_info_8125a_2);  in rtl_hw_start_8125a_2()
3637 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125a_2()
3640 static void rtl_hw_start_8125b(struct rtl8169_private *tp)  in rtl_hw_start_8125b()  argument
3651 	rtl_set_def_aspm_entry_latency(tp);  in rtl_hw_start_8125b()
3652 	rtl_ephy_init(tp, e_info_8125b);  in rtl_hw_start_8125b()
3653 	rtl_hw_start_8125_common(tp);  in rtl_hw_start_8125b()
3656 static void rtl_hw_config(struct rtl8169_private *tp)  in rtl_hw_config()  argument
3700 	if (hw_configs[tp->mac_version])  in rtl_hw_config()
3701 		hw_configs[tp->mac_version](tp);  in rtl_hw_config()
3704 static void rtl_hw_start_8125(struct rtl8169_private *tp)  in rtl_hw_start_8125()  argument
3710 		RTL_W32(tp, i, 0);  in rtl_hw_start_8125()
3712 	rtl_hw_config(tp);  in rtl_hw_start_8125()
3715 static void rtl_hw_start_8168(struct rtl8169_private *tp)  in rtl_hw_start_8168()  argument
3717 	if (rtl_is_8168evl_up(tp))  in rtl_hw_start_8168()
3718 		RTL_W8(tp, MaxTxPacketSize, EarlySize);  in rtl_hw_start_8168()
3720 		RTL_W8(tp, MaxTxPacketSize, TxPacketMax);  in rtl_hw_start_8168()
3722 	rtl_hw_config(tp);  in rtl_hw_start_8168()
3725 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8168()
3728 static void rtl_hw_start_8169(struct rtl8169_private *tp)  in rtl_hw_start_8169()  argument
3730 	RTL_W8(tp, EarlyTxThres, NoEarlyTx);  in rtl_hw_start_8169()
3732 	tp->cp_cmd |= PCIMulRW;  in rtl_hw_start_8169()
3734 	if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||  in rtl_hw_start_8169()
3735 	    tp->mac_version == RTL_GIGA_MAC_VER_03)  in rtl_hw_start_8169()
3736 		tp->cp_cmd |= EnAnaPLL;  in rtl_hw_start_8169()
3738 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start_8169()
3740 	rtl8169_set_magic_reg(tp);  in rtl_hw_start_8169()
3743 	RTL_W16(tp, IntrMitigate, 0x0000);  in rtl_hw_start_8169()
3746 static void rtl_hw_start(struct  rtl8169_private *tp)  in rtl_hw_start()  argument
3748 	rtl_unlock_config_regs(tp);  in rtl_hw_start()
3750 	rtl_hw_aspm_clkreq_enable(tp, false);  in rtl_hw_start()
3751 	RTL_W16(tp, CPlusCmd, tp->cp_cmd);  in rtl_hw_start()
3753 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_hw_start()
3754 		rtl_hw_start_8169(tp);  in rtl_hw_start()
3755 	else if (rtl_is_8125(tp))  in rtl_hw_start()
3756 		rtl_hw_start_8125(tp);  in rtl_hw_start()
3758 		rtl_hw_start_8168(tp);  in rtl_hw_start()
3760 	rtl_enable_exit_l1(tp);  in rtl_hw_start()
3761 	rtl_hw_aspm_clkreq_enable(tp, true);  in rtl_hw_start()
3762 	rtl_set_rx_max_size(tp);  in rtl_hw_start()
3763 	rtl_set_rx_tx_desc_registers(tp);  in rtl_hw_start()
3764 	rtl_lock_config_regs(tp);  in rtl_hw_start()
3766 	rtl_jumbo_config(tp);  in rtl_hw_start()
3769 	rtl_pci_commit(tp);  in rtl_hw_start()
3771 	RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);  in rtl_hw_start()
3772 	rtl_init_rxcfg(tp);  in rtl_hw_start()
3773 	rtl_set_tx_config_registers(tp);  in rtl_hw_start()
3774 	rtl_set_rx_config_features(tp, tp->dev->features);  in rtl_hw_start()
3775 	rtl_set_rx_mode(tp->dev);  in rtl_hw_start()
3776 	rtl_irq_enable(tp);  in rtl_hw_start()
3781 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_change_mtu()  local
3785 	rtl_jumbo_config(tp);  in rtl8169_change_mtu()
3787 	switch (tp->mac_version) {  in rtl8169_change_mtu()
3790 		rtl8125_set_eee_txidle_timer(tp);  in rtl8169_change_mtu()
3809 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,  in rtl8169_alloc_rx_data()  argument
3812 	struct device *d = tp_to_dev(tp);  in rtl8169_alloc_rx_data()
3823 		netdev_err(tp->dev, "Failed to map RX DMA!\n");  in rtl8169_alloc_rx_data()
3834 static void rtl8169_rx_clear(struct rtl8169_private *tp)  in rtl8169_rx_clear()  argument
3838 	for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {  in rtl8169_rx_clear()
3839 		dma_unmap_page(tp_to_dev(tp),  in rtl8169_rx_clear()
3840 			       le64_to_cpu(tp->RxDescArray[i].addr),  in rtl8169_rx_clear()
3842 		__free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));  in rtl8169_rx_clear()
3843 		tp->Rx_databuff[i] = NULL;  in rtl8169_rx_clear()
3844 		tp->RxDescArray[i].addr = 0;  in rtl8169_rx_clear()
3845 		tp->RxDescArray[i].opts1 = 0;  in rtl8169_rx_clear()
3849 static int rtl8169_rx_fill(struct rtl8169_private *tp)  in rtl8169_rx_fill()  argument
3856 		data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);  in rtl8169_rx_fill()
3858 			rtl8169_rx_clear(tp);  in rtl8169_rx_fill()
3861 		tp->Rx_databuff[i] = data;  in rtl8169_rx_fill()
3865 	tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);  in rtl8169_rx_fill()
3870 static int rtl8169_init_ring(struct rtl8169_private *tp)  in rtl8169_init_ring()  argument
3872 	rtl8169_init_ring_indexes(tp);  in rtl8169_init_ring()
3874 	memset(tp->tx_skb, 0, sizeof(tp->tx_skb));  in rtl8169_init_ring()
3875 	memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));  in rtl8169_init_ring()
3877 	return rtl8169_rx_fill(tp);  in rtl8169_init_ring()
3880 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)  in rtl8169_unmap_tx_skb()  argument
3882 	struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_unmap_tx_skb()
3883 	struct TxDesc *desc = tp->TxDescArray + entry;  in rtl8169_unmap_tx_skb()
3885 	dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,  in rtl8169_unmap_tx_skb()
3891 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,  in rtl8169_tx_clear_range()  argument
3898 		struct ring_info *tx_skb = tp->tx_skb + entry;  in rtl8169_tx_clear_range()
3904 			rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_tx_clear_range()
3911 static void rtl8169_tx_clear(struct rtl8169_private *tp)  in rtl8169_tx_clear()  argument
3913 	rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);  in rtl8169_tx_clear()
3914 	netdev_reset_queue(tp->dev);  in rtl8169_tx_clear()
3917 static void rtl8169_cleanup(struct rtl8169_private *tp)  in rtl8169_cleanup()  argument
3919 	napi_disable(&tp->napi);  in rtl8169_cleanup()
3925 	rtl8169_irq_mask_and_ack(tp);  in rtl8169_cleanup()
3927 	rtl_rx_close(tp);  in rtl8169_cleanup()
3929 	switch (tp->mac_version) {  in rtl8169_cleanup()
3932 		rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);  in rtl8169_cleanup()
3935 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
3936 		rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);  in rtl8169_cleanup()
3939 		rtl_enable_rxdvgate(tp);  in rtl8169_cleanup()
3943 		RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);  in rtl8169_cleanup()
3948 	rtl_hw_reset(tp);  in rtl8169_cleanup()
3950 	rtl8169_tx_clear(tp);  in rtl8169_cleanup()
3951 	rtl8169_init_ring_indexes(tp);  in rtl8169_cleanup()
3954 static void rtl_reset_work(struct rtl8169_private *tp)  in rtl_reset_work()  argument
3958 	netif_stop_queue(tp->dev);  in rtl_reset_work()
3960 	rtl8169_cleanup(tp);  in rtl_reset_work()
3963 		rtl8169_mark_to_asic(tp->RxDescArray + i);  in rtl_reset_work()
3965 	napi_enable(&tp->napi);  in rtl_reset_work()
3966 	rtl_hw_start(tp);  in rtl_reset_work()
3971 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_tx_timeout()  local
3973 	rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);  in rtl8169_tx_timeout()
3976 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,  in rtl8169_tx_map()  argument
3979 	struct TxDesc *txd = tp->TxDescArray + entry;  in rtl8169_tx_map()
3980 	struct device *d = tp_to_dev(tp);  in rtl8169_tx_map()
3989 			netdev_err(tp->dev, "Failed to map TX data!\n");  in rtl8169_tx_map()
4003 	tp->tx_skb[entry].len = len;  in rtl8169_tx_map()
4008 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,  in rtl8169_xmit_frags()  argument
4021 		if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))  in rtl8169_xmit_frags()
4028 	rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);  in rtl8169_xmit_frags()
4053 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,  in rtl8125_quirk_udp_padto()  argument
4058 	if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&  in rtl8125_quirk_udp_padto()
4080 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,  in rtl_quirk_packet_padto()  argument
4085 	padto = rtl8125_quirk_udp_padto(tp, skb);  in rtl_quirk_packet_padto()
4087 	switch (tp->mac_version) {  in rtl_quirk_packet_padto()
4119 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,  in rtl8169_tso_csum_v2()  argument
4168 		unsigned int padto = rtl_quirk_packet_padto(tp, skb);  in rtl8169_tso_csum_v2()
4177 static unsigned int rtl_tx_slots_avail(struct rtl8169_private *tp)  in rtl_tx_slots_avail()  argument
4179 	return READ_ONCE(tp->dirty_tx) + NUM_TX_DESC - READ_ONCE(tp->cur_tx);  in rtl_tx_slots_avail()
4183 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)  in rtl_chip_supports_csum_v2()  argument
4185 	switch (tp->mac_version) {  in rtl_chip_supports_csum_v2()
4194 static void rtl8169_doorbell(struct rtl8169_private *tp)  in rtl8169_doorbell()  argument
4196 	if (rtl_is_8125(tp))  in rtl8169_doorbell()
4197 		RTL_W16(tp, TxPoll_8125, BIT(0));  in rtl8169_doorbell()
4199 		RTL_W8(tp, TxPoll, NPQ);  in rtl8169_doorbell()
4206 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_start_xmit()  local
4207 	unsigned int entry = tp->cur_tx % NUM_TX_DESC;  in rtl8169_start_xmit()
4212 	if (unlikely(!rtl_tx_slots_avail(tp))) {  in rtl8169_start_xmit()
4221 	if (!rtl_chip_supports_csum_v2(tp))  in rtl8169_start_xmit()
4223 	else if (!rtl8169_tso_csum_v2(tp, skb, opts))  in rtl8169_start_xmit()
4226 	if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,  in rtl8169_start_xmit()
4230 	txd_first = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4233 		if (rtl8169_xmit_frags(tp, skb, opts, entry))  in rtl8169_start_xmit()
4238 	txd_last = tp->TxDescArray + entry;  in rtl8169_start_xmit()
4240 	tp->tx_skb[entry].skb = skb;  in rtl8169_start_xmit()
4254 	WRITE_ONCE(tp->cur_tx, tp->cur_tx + frags + 1);  in rtl8169_start_xmit()
4256 	stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp),  in rtl8169_start_xmit()
4260 		rtl8169_doorbell(tp);  in rtl8169_start_xmit()
4265 	rtl8169_unmap_tx_skb(tp, entry);  in rtl8169_start_xmit()
4312 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_features_check()  local
4315 		if (tp->mac_version == RTL_GIGA_MAC_VER_34)  in rtl8169_features_check()
4319 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4326 		if (rtl_quirk_packet_padto(tp, skb))  in rtl8169_features_check()
4330 		    rtl_chip_supports_csum_v2(tp))  in rtl8169_features_check()
4339 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_pcierr_interrupt()  local
4340 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_pcierr_interrupt()
4352 	rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_pcierr_interrupt()
4355 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,  in rtl_tx()  argument
4361 	dirty_tx = tp->dirty_tx;  in rtl_tx()
4363 	while (READ_ONCE(tp->cur_tx) != dirty_tx) {  in rtl_tx()
4367 		status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));  in rtl_tx()
4371 		skb = tp->tx_skb[entry].skb;  in rtl_tx()
4372 		rtl8169_unmap_tx_skb(tp, entry);  in rtl_tx()
4382 	if (tp->dirty_tx != dirty_tx) {  in rtl_tx()
4384 		WRITE_ONCE(tp->dirty_tx, dirty_tx);  in rtl_tx()
4387 					      rtl_tx_slots_avail(tp),  in rtl_tx()
4397 		if (READ_ONCE(tp->cur_tx) != dirty_tx && skb)  in rtl_tx()
4398 			rtl8169_doorbell(tp);  in rtl_tx()
4417 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, int budget)  in rtl_rx()  argument
4419 	struct device *d = tp_to_dev(tp);  in rtl_rx()
4422 	for (count = 0; count < budget; count++, tp->cur_rx++) {  in rtl_rx()
4423 		unsigned int pkt_size, entry = tp->cur_rx % NUM_RX_DESC;  in rtl_rx()
4424 		struct RxDesc *desc = tp->RxDescArray + entry;  in rtl_rx()
4469 		skb = napi_alloc_skb(&tp->napi, pkt_size);  in rtl_rx()
4476 		rx_buf = page_address(tp->Rx_databuff[entry]);  in rtl_rx()
4493 		napi_gro_receive(&tp->napi, skb);  in rtl_rx()
4505 	struct rtl8169_private *tp = dev_instance;  in rtl8169_interrupt()  local
4506 	u32 status = rtl_get_events(tp);  in rtl8169_interrupt()
4508 	if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))  in rtl8169_interrupt()
4512 		rtl8169_pcierr_interrupt(tp->dev);  in rtl8169_interrupt()
4517 		phy_mac_interrupt(tp->phydev);  in rtl8169_interrupt()
4520 	    tp->mac_version == RTL_GIGA_MAC_VER_11)) {  in rtl8169_interrupt()
4521 		netif_stop_queue(tp->dev);  in rtl8169_interrupt()
4522 		rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);  in rtl8169_interrupt()
4525 	if (napi_schedule_prep(&tp->napi)) {  in rtl8169_interrupt()
4526 		rtl_irq_disable(tp);  in rtl8169_interrupt()
4527 		__napi_schedule(&tp->napi);  in rtl8169_interrupt()
4530 	rtl_ack_events(tp, status);  in rtl8169_interrupt()
4537 	struct rtl8169_private *tp =  in rtl_task()  local
4543 	if (!netif_running(tp->dev) ||  in rtl_task()
4544 	    !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))  in rtl_task()
4547 	if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {  in rtl_task()
4549 		if (RTL_R32(tp, TxConfig) == ~0) {  in rtl_task()
4550 			ret = pci_reset_bus(tp->pci_dev);  in rtl_task()
4552 				netdev_err(tp->dev, "Can't reset secondary PCI bus, detach NIC\n");  in rtl_task()
4553 				netif_device_detach(tp->dev);  in rtl_task()
4559 		ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |  in rtl_task()
4562 			netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");  in rtl_task()
4566 	if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {  in rtl_task()
4568 		rtl_reset_work(tp);  in rtl_task()
4569 		netif_wake_queue(tp->dev);  in rtl_task()
4577 	struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);  in rtl8169_poll()  local
4578 	struct net_device *dev = tp->dev;  in rtl8169_poll()
4581 	rtl_tx(dev, tp, budget);  in rtl8169_poll()
4583 	work_done = rtl_rx(dev, tp, budget);  in rtl8169_poll()
4586 		rtl_irq_enable(tp);  in rtl8169_poll()
4593 	struct rtl8169_private *tp = netdev_priv(ndev);  in r8169_phylink_handler()  local
4594 	struct device *d = tp_to_dev(tp);  in r8169_phylink_handler()
4597 		rtl_link_chg_patch(tp);  in r8169_phylink_handler()
4603 	phy_print_status(tp->phydev);  in r8169_phylink_handler()
4606 static int r8169_phy_connect(struct rtl8169_private *tp)  in r8169_phy_connect()  argument
4608 	struct phy_device *phydev = tp->phydev;  in r8169_phy_connect()
4612 	phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :  in r8169_phy_connect()
4615 	ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,  in r8169_phy_connect()
4620 	if (!tp->supports_gmii)  in r8169_phy_connect()
4628 static void rtl8169_down(struct rtl8169_private *tp)  in rtl8169_down()  argument
4631 	bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);  in rtl8169_down()
4633 	phy_stop(tp->phydev);  in rtl8169_down()
4635 	rtl8169_update_counters(tp);  in rtl8169_down()
4637 	pci_clear_master(tp->pci_dev);  in rtl8169_down()
4638 	rtl_pci_commit(tp);  in rtl8169_down()
4640 	rtl8169_cleanup(tp);  in rtl8169_down()
4641 	rtl_disable_exit_l1(tp);  in rtl8169_down()
4642 	rtl_prepare_power_down(tp);  in rtl8169_down()
4645 static void rtl8169_up(struct rtl8169_private *tp)  in rtl8169_up()  argument
4647 	pci_set_master(tp->pci_dev);  in rtl8169_up()
4648 	phy_init_hw(tp->phydev);  in rtl8169_up()
4649 	phy_resume(tp->phydev);  in rtl8169_up()
4650 	rtl8169_init_phy(tp);  in rtl8169_up()
4651 	napi_enable(&tp->napi);  in rtl8169_up()
4652 	set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);  in rtl8169_up()
4653 	rtl_reset_work(tp);  in rtl8169_up()
4655 	phy_start(tp->phydev);  in rtl8169_up()
4660 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_close()  local
4661 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_close()
4666 	rtl8169_down(tp);  in rtl8169_close()
4667 	rtl8169_rx_clear(tp);  in rtl8169_close()
4669 	cancel_work_sync(&tp->wk.work);  in rtl8169_close()
4671 	free_irq(tp->irq, tp);  in rtl8169_close()
4673 	phy_disconnect(tp->phydev);  in rtl8169_close()
4675 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl8169_close()
4676 			  tp->RxPhyAddr);  in rtl8169_close()
4677 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl8169_close()
4678 			  tp->TxPhyAddr);  in rtl8169_close()
4679 	tp->TxDescArray = NULL;  in rtl8169_close()
4680 	tp->RxDescArray = NULL;  in rtl8169_close()
4690 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_netpoll()  local
4692 	rtl8169_interrupt(tp->irq, tp);  in rtl8169_netpoll()
4698 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl_open()  local
4699 	struct pci_dev *pdev = tp->pci_dev;  in rtl_open()
4709 	tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,  in rtl_open()
4710 					     &tp->TxPhyAddr, GFP_KERNEL);  in rtl_open()
4711 	if (!tp->TxDescArray)  in rtl_open()
4714 	tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,  in rtl_open()
4715 					     &tp->RxPhyAddr, GFP_KERNEL);  in rtl_open()
4716 	if (!tp->RxDescArray)  in rtl_open()
4719 	retval = rtl8169_init_ring(tp);  in rtl_open()
4723 	rtl_request_firmware(tp);  in rtl_open()
4726 	retval = request_irq(tp->irq, rtl8169_interrupt, irqflags, dev->name, tp);  in rtl_open()
4730 	retval = r8169_phy_connect(tp);  in rtl_open()
4734 	rtl8169_up(tp);  in rtl_open()
4735 	rtl8169_init_counter_offsets(tp);  in rtl_open()
4743 	free_irq(tp->irq, tp);  in rtl_open()
4745 	rtl_release_firmware(tp);  in rtl_open()
4746 	rtl8169_rx_clear(tp);  in rtl_open()
4748 	dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,  in rtl_open()
4749 			  tp->RxPhyAddr);  in rtl_open()
4750 	tp->RxDescArray = NULL;  in rtl_open()
4752 	dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,  in rtl_open()
4753 			  tp->TxPhyAddr);  in rtl_open()
4754 	tp->TxDescArray = NULL;  in rtl_open()
4761 	struct rtl8169_private *tp = netdev_priv(dev);  in rtl8169_get_stats64()  local
4762 	struct pci_dev *pdev = tp->pci_dev;  in rtl8169_get_stats64()
4763 	struct rtl8169_counters *counters = tp->counters;  in rtl8169_get_stats64()
4775 		rtl8169_update_counters(tp);  in rtl8169_get_stats64()
4782 		le64_to_cpu(tp->tc_offset.tx_errors);  in rtl8169_get_stats64()
4784 		le32_to_cpu(tp->tc_offset.tx_multi_collision);  in rtl8169_get_stats64()
4786 		le16_to_cpu(tp->tc_offset.tx_aborted);  in rtl8169_get_stats64()
4788 		le16_to_cpu(tp->tc_offset.rx_missed);  in rtl8169_get_stats64()
4793 static void rtl8169_net_suspend(struct rtl8169_private *tp)  in rtl8169_net_suspend()  argument
4795 	netif_device_detach(tp->dev);  in rtl8169_net_suspend()
4797 	if (netif_running(tp->dev))  in rtl8169_net_suspend()
4798 		rtl8169_down(tp);  in rtl8169_net_suspend()
4803 	struct rtl8169_private *tp = dev_get_drvdata(dev);  in rtl8169_runtime_resume()  local
4805 	rtl_rar_set(tp, tp->dev->dev_addr);  in rtl8169_runtime_resume()
4806 	__rtl8169_set_wol(tp, tp->saved_wolopts);  in rtl8169_runtime_resume()
4808 	if (tp->TxDescArray)  in rtl8169_runtime_resume()
4809 		rtl8169_up(tp);  in rtl8169_runtime_resume()
4811 	netif_device_attach(tp->dev);  in rtl8169_runtime_resume()
4818 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_suspend()  local
4821 	rtl8169_net_suspend(tp);  in rtl8169_suspend()
4822 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_suspend()
4823 		clk_disable_unprepare(tp->clk);  in rtl8169_suspend()
4831 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_resume()  local
4833 	if (!device_may_wakeup(tp_to_dev(tp)))  in rtl8169_resume()
4834 		clk_prepare_enable(tp->clk);  in rtl8169_resume()
4837 	if (tp->mac_version == RTL_GIGA_MAC_VER_37)  in rtl8169_resume()
4838 		rtl_init_rxcfg(tp);  in rtl8169_resume()
4845 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_suspend()  local
4847 	if (!tp->TxDescArray) {  in rtl8169_runtime_suspend()
4848 		netif_device_detach(tp->dev);  in rtl8169_runtime_suspend()
4853 	__rtl8169_set_wol(tp, WAKE_PHY);  in rtl8169_runtime_suspend()
4854 	rtl8169_net_suspend(tp);  in rtl8169_runtime_suspend()
4862 	struct rtl8169_private *tp = dev_get_drvdata(device);  in rtl8169_runtime_idle()  local
4864 	if (tp->dash_type != RTL_DASH_NONE)  in rtl8169_runtime_idle()
4867 	if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))  in rtl8169_runtime_idle()
4881 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_shutdown()  local
4884 	rtl8169_net_suspend(tp);  in rtl_shutdown()
4888 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_shutdown()
4891 	    tp->dash_type == RTL_DASH_NONE) {  in rtl_shutdown()
4892 		pci_wake_from_d3(pdev, tp->saved_wolopts);  in rtl_shutdown()
4899 	struct rtl8169_private *tp = pci_get_drvdata(pdev);  in rtl_remove_one()  local
4904 	unregister_netdev(tp->dev);  in rtl_remove_one()
4906 	if (tp->dash_type != RTL_DASH_NONE)  in rtl_remove_one()
4907 		rtl8168_driver_stop(tp);  in rtl_remove_one()
4909 	rtl_release_firmware(tp);  in rtl_remove_one()
4912 	rtl_rar_set(tp, tp->dev->perm_addr);  in rtl_remove_one()
4935 static void rtl_set_irq_mask(struct rtl8169_private *tp)  in rtl_set_irq_mask()  argument
4937 	tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;  in rtl_set_irq_mask()
4939 	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)  in rtl_set_irq_mask()
4940 		tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;  in rtl_set_irq_mask()
4941 	else if (tp->mac_version == RTL_GIGA_MAC_VER_11)  in rtl_set_irq_mask()
4943 		tp->irq_mask |= RxFIFOOver;  in rtl_set_irq_mask()
4945 		tp->irq_mask |= RxOverflow;  in rtl_set_irq_mask()
4948 static int rtl_alloc_irq(struct rtl8169_private *tp)  in rtl_alloc_irq()  argument
4952 	switch (tp->mac_version) {  in rtl_alloc_irq()
4954 		rtl_unlock_config_regs(tp);  in rtl_alloc_irq()
4955 		RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);  in rtl_alloc_irq()
4956 		rtl_lock_config_regs(tp);  in rtl_alloc_irq()
4966 	return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);  in rtl_alloc_irq()
4969 static void rtl_read_mac_address(struct rtl8169_private *tp,  in rtl_read_mac_address()  argument
4973 	if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {  in rtl_read_mac_address()
4976 		value = rtl_eri_read(tp, 0xe0);  in rtl_read_mac_address()
4978 		value = rtl_eri_read(tp, 0xe4);  in rtl_read_mac_address()
4980 	} else if (rtl_is_8125(tp)) {  in rtl_read_mac_address()
4981 		rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);  in rtl_read_mac_address()
4987 	return RTL_R8(tp, MCU) & LINK_LIST_RDY;  in DECLARE_RTL_COND()
4990 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)  in r8168g_wait_ll_share_fifo_ready()  argument
4992 	rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);  in r8168g_wait_ll_share_fifo_ready()
4997 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_read_reg()  local
5002 	return rtl_readphy(tp, phyreg);  in r8169_mdio_read_reg()
5008 	struct rtl8169_private *tp = mii_bus->priv;  in r8169_mdio_write_reg()  local
5013 	rtl_writephy(tp, phyreg, val);  in r8169_mdio_write_reg()
5018 static int r8169_mdio_register(struct rtl8169_private *tp)  in r8169_mdio_register()  argument
5020 	struct pci_dev *pdev = tp->pci_dev;  in r8169_mdio_register()
5029 	new_bus->priv = tp;  in r8169_mdio_register()
5042 	tp->phydev = mdiobus_get_phy(new_bus, 0);  in r8169_mdio_register()
5043 	if (!tp->phydev) {  in r8169_mdio_register()
5045 	} else if (!tp->phydev->drv) {  in r8169_mdio_register()
5050 			tp->phydev->phy_id);  in r8169_mdio_register()
5054 	tp->phydev->mac_managed_pm = true;  in r8169_mdio_register()
5056 	phy_support_asym_pause(tp->phydev);  in r8169_mdio_register()
5059 	phy_suspend(tp->phydev);  in r8169_mdio_register()
5064 static void rtl_hw_init_8168g(struct rtl8169_private *tp)  in rtl_hw_init_8168g()  argument
5066 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8168g()
5068 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8168g()
5070 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8168g()
5072 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8168g()
5073 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5075 	r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));  in rtl_hw_init_8168g()
5076 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8168g()
5079 static void rtl_hw_init_8125(struct rtl8169_private *tp)  in rtl_hw_init_8125()  argument
5081 	rtl_enable_rxdvgate(tp);  in rtl_hw_init_8125()
5083 	RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));  in rtl_hw_init_8125()
5085 	RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);  in rtl_hw_init_8125()
5087 	r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);  in rtl_hw_init_8125()
5088 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5090 	r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);  in rtl_hw_init_8125()
5091 	r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);  in rtl_hw_init_8125()
5092 	r8168_mac_ocp_write(tp, 0xc01e, 0x5555);  in rtl_hw_init_8125()
5093 	r8168g_wait_ll_share_fifo_ready(tp);  in rtl_hw_init_8125()
5096 static void rtl_hw_initialize(struct rtl8169_private *tp)  in rtl_hw_initialize()  argument
5098 	switch (tp->mac_version) {  in rtl_hw_initialize()
5100 		rtl8168ep_stop_cmac(tp);  in rtl_hw_initialize()
5103 		rtl_hw_init_8168g(tp);  in rtl_hw_initialize()
5106 		rtl_hw_init_8125(tp);  in rtl_hw_initialize()
5113 static int rtl_jumbo_max(struct rtl8169_private *tp)  in rtl_jumbo_max()  argument
5116 	if (!tp->supports_gmii)  in rtl_jumbo_max()
5119 	switch (tp->mac_version) {  in rtl_jumbo_max()
5135 static void rtl_init_mac_address(struct rtl8169_private *tp)  in rtl_init_mac_address()  argument
5138 	struct net_device *dev = tp->dev;  in rtl_init_mac_address()
5141 	rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);  in rtl_init_mac_address()
5145 	rtl_read_mac_address(tp, mac_addr);  in rtl_init_mac_address()
5149 	rtl_read_mac_from_reg(tp, mac_addr, MAC0);  in rtl_init_mac_address()
5155 	dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");  in rtl_init_mac_address()
5158 	rtl_rar_set(tp, mac_addr);  in rtl_init_mac_address()
5162 static bool rtl_aspm_is_safe(struct rtl8169_private *tp)  in rtl_aspm_is_safe()  argument
5164 	if (tp->mac_version >= RTL_GIGA_MAC_VER_61 &&  in rtl_aspm_is_safe()
5165 	    r8168_mac_ocp_read(tp, 0xc0b2) & 0xf)  in rtl_aspm_is_safe()
5173 	struct rtl8169_private *tp;  in rtl_init_one()  local
5180 	dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));  in rtl_init_one()
5186 	tp = netdev_priv(dev);  in rtl_init_one()
5187 	tp->dev = dev;  in rtl_init_one()
5188 	tp->pci_dev = pdev;  in rtl_init_one()
5189 	tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;  in rtl_init_one()
5190 	tp->eee_adv = -1;  in rtl_init_one()
5191 	tp->ocp_base = OCP_STD_PHY_BASE;  in rtl_init_one()
5193 	raw_spin_lock_init(&tp->cfg9346_usage_lock);  in rtl_init_one()
5194 	raw_spin_lock_init(&tp->config25_lock);  in rtl_init_one()
5195 	raw_spin_lock_init(&tp->mac_ocp_lock);  in rtl_init_one()
5203 	tp->clk = devm_clk_get_optional_enabled(&pdev->dev, "ether_clk");  in rtl_init_one()
5204 	if (IS_ERR(tp->clk))  in rtl_init_one()
5205 		return dev_err_probe(&pdev->dev, PTR_ERR(tp->clk), "failed to get ether_clk\n");  in rtl_init_one()
5224 	tp->mmio_addr = pcim_iomap_table(pdev)[region];  in rtl_init_one()
5226 	txconfig = RTL_R32(tp, TxConfig);  in rtl_init_one()
5233 	chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);  in rtl_init_one()
5238 	tp->mac_version = chipset;  in rtl_init_one()
5243 	if (rtl_aspm_is_safe(tp))  in rtl_init_one()
5247 	tp->aspm_manageable = !rc;  in rtl_init_one()
5249 	tp->dash_type = rtl_check_dash(tp);  in rtl_init_one()
5251 	tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;  in rtl_init_one()
5253 	if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&  in rtl_init_one()
5257 	rtl_init_rxcfg(tp);  in rtl_init_one()
5259 	rtl8169_irq_mask_and_ack(tp);  in rtl_init_one()
5261 	rtl_hw_initialize(tp);  in rtl_init_one()
5263 	rtl_hw_reset(tp);  in rtl_init_one()
5265 	rc = rtl_alloc_irq(tp);  in rtl_init_one()
5269 	tp->irq = pci_irq_vector(pdev, 0);  in rtl_init_one()
5271 	INIT_WORK(&tp->wk.work, rtl_task);  in rtl_init_one()
5273 	rtl_init_mac_address(tp);  in rtl_init_one()
5277 	netif_napi_add(dev, &tp->napi, rtl8169_poll);  in rtl_init_one()
5288 	if (tp->mac_version == RTL_GIGA_MAC_VER_05)  in rtl_init_one()
5292 	if (rtl_chip_supports_csum_v2(tp))  in rtl_init_one()
5302 	if (rtl_chip_supports_csum_v2(tp)) {  in rtl_init_one()
5320 	if (tp->dash_type == RTL_DASH_NONE) {  in rtl_init_one()
5321 		rtl_set_d3_pll_down(tp, true);  in rtl_init_one()
5323 		rtl_set_d3_pll_down(tp, false);  in rtl_init_one()
5327 	jumbo_max = rtl_jumbo_max(tp);  in rtl_init_one()
5331 	rtl_set_irq_mask(tp);  in rtl_init_one()
5333 	tp->fw_name = rtl_chip_infos[chipset].fw_name;  in rtl_init_one()
5335 	tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),  in rtl_init_one()
5336 					    &tp->counters_phys_addr,  in rtl_init_one()
5338 	if (!tp->counters)  in rtl_init_one()
5341 	pci_set_drvdata(pdev, tp);  in rtl_init_one()
5343 	rc = r8169_mdio_register(tp);  in rtl_init_one()
5352 		    rtl_chip_infos[chipset].name, dev->dev_addr, xid, tp->irq);  in rtl_init_one()
5356 			    jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?  in rtl_init_one()
5359 	if (tp->dash_type != RTL_DASH_NONE) {  in rtl_init_one()
5361 		rtl8168_driver_start(tp);  in rtl_init_one()