Lines Matching refs:RTL_R8
83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg)) macro
694 RTL_R8(tp, ChipCmd); in rtl_pci_commit()
703 val = RTL_R8(tp, Config2); in rtl_mod_config2()
714 val = RTL_R8(tp, Config5); in rtl_mod_config5()
743 mac[i] = RTL_R8(tp, reg + i); in rtl_read_mac_from_reg()
1190 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1195 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1197 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1198 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1277 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1279 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | D3_NO_PLL_DOWN); in rtl_set_d3_pll_down()
1426 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask; in __rtl8169_set_wol()
1435 options = RTL_R8(tp, Config1) & ~PMEnable; in __rtl8169_set_wol()
1625 u8 val = RTL_R8(tp, ChipCmd); in rtl8169_update_counters()
2173 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2311 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168c_hw_jumbo_enable()
2312 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1); in r8168c_hw_jumbo_enable()
2317 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168c_hw_jumbo_disable()
2318 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1); in r8168c_hw_jumbo_disable()
2323 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168dp_hw_jumbo_enable()
2328 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168dp_hw_jumbo_disable()
2334 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0); in r8168e_hw_jumbo_enable()
2335 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01); in r8168e_hw_jumbo_enable()
2341 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0); in r8168e_hw_jumbo_disable()
2342 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01); in r8168e_hw_jumbo_disable()
2347 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0)); in r8168b_1_hw_jumbo_enable()
2352 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0)); in r8168b_1_hw_jumbo_disable()
2410 return RTL_R8(tp, ChipCmd) & CmdReset; in DECLARE_RTL_COND()
2452 return RTL_R8(tp, TxPoll) & NPQ; in DECLARE_RTL_COND()
2462 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY; in DECLARE_RTL_COND()
2482 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl_wait_txrx_fifo_empty()
2569 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz) in rtl8169_set_magic_reg()
2703 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); in rtl_pcie_state_l2l3_disable()
2808 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168b()
2813 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down); in __rtl_hw_start_8168cp()
2815 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in __rtl_hw_start_8168cp()
2841 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_2()
2848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8168cp_3()
2970 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168e_2()
2974 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168e_2()
2994 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8168f()
2995 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8168f()
3276 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168h_1()
3277 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168h_1()
3279 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168h_1()
3327 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8168ep()
3345 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8168ep_3()
3346 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8168ep_3()
3382 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8117()
3383 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN); in rtl_hw_start_8117()
3385 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN); in rtl_hw_start_8117()
3433 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_1()
3435 cfg1 = RTL_R8(tp, Config1); in rtl_hw_start_8102e_1()
3447 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8102e_2()
3467 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en); in rtl_hw_start_8401()
3489 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8105e_1()
3490 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN); in rtl_hw_start_8105e_1()
3515 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_start_8402()
3537 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET); in rtl_hw_start_8106()
3538 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN); in rtl_hw_start_8106()
3567 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3935 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
3943 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq); in rtl8169_cleanup()
4955 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable); in rtl_alloc_irq()
4987 return RTL_R8(tp, MCU) & LINK_LIST_RDY; in DECLARE_RTL_COND()
5068 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8168g()
5070 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8168g()
5083 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb)); in rtl_hw_init_8125()
5085 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB); in rtl_hw_init_8125()