Lines Matching +full:0 +full:x0c

14 #define MLXSW_PCI_CIR_BASE			0x71000
16 #define MLXSW_PCI_CIR_IN_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x04)
17 #define MLXSW_PCI_CIR_IN_MODIFIER (MLXSW_PCI_CIR_BASE + 0x08)
18 #define MLXSW_PCI_CIR_OUT_PARAM_HI (MLXSW_PCI_CIR_BASE + 0x0C)
19 #define MLXSW_PCI_CIR_OUT_PARAM_LO (MLXSW_PCI_CIR_BASE + 0x10)
20 #define MLXSW_PCI_CIR_TOKEN (MLXSW_PCI_CIR_BASE + 0x14)
21 #define MLXSW_PCI_CIR_CTRL (MLXSW_PCI_CIR_BASE + 0x18)
30 #define MLXSW_PCI_FW_READY 0xA1844
31 #define MLXSW_PCI_FW_READY_MASK 0xFFFF
32 #define MLXSW_PCI_FW_READY_MAGIC 0x5E
34 #define MLXSW_PCI_DOORBELL_SDQ_OFFSET 0x000
35 #define MLXSW_PCI_DOORBELL_RDQ_OFFSET 0x200
36 #define MLXSW_PCI_DOORBELL_CQ_OFFSET 0x400
37 #define MLXSW_PCI_DOORBELL_EQ_OFFSET 0x600
38 #define MLXSW_PCI_DOORBELL_ARM_CQ_OFFSET 0x800
39 #define MLXSW_PCI_DOORBELL_ARM_EQ_OFFSET 0xA00
46 #define MLXSW_PCI_EQ_ASYNC_NUM 0
50 #define MLXSW_PCI_SDQ_EMAD_INDEX 0
51 #define MLXSW_PCI_SDQ_EMAD_TC 0
65 #define MLXSW_PCI_EQE_UPDATE_COUNT 0x80
68 #define MLXSW_PCI_WQE_TYPE_ETHERNET 0xA
74 MLXSW_ITEM32(pci, wqe, c, 0x00, 31, 1);
86 MLXSW_ITEM32(pci, wqe, lp, 0x00, 30, 1);
91 MLXSW_ITEM32(pci, wqe, type, 0x00, 23, 4);
94 * Size of i-th scatter/gather entry, 0 if entry is unused.
96 MLXSW_ITEM16_INDEXED(pci, wqe, byte_count, 0x02, 0, 14, 0x02, 0x00, false);
102 MLXSW_ITEM64_INDEXED(pci, wqe, address, 0x08, 0, 64, 0x8, 0x0, false);
143 MLXSW_ITEM32(pci, cqe0, lag, 0x00, 23, 1);
144 MLXSW_ITEM32(pci, cqe12, lag, 0x00, 24, 1);
145 mlxsw_pci_cqe_item_helpers(lag, 0, 12, 12);
148 * When lag=0: System port on which the packet was received
151 * bits [3:0] sub_port on which the packet was received
153 MLXSW_ITEM32(pci, cqe, system_port, 0x00, 0, 16);
154 MLXSW_ITEM32(pci, cqe0, lag_id, 0x00, 4, 12);
155 MLXSW_ITEM32(pci, cqe12, lag_id, 0x00, 0, 16);
156 mlxsw_pci_cqe_item_helpers(lag_id, 0, 12, 12);
157 MLXSW_ITEM32(pci, cqe0, lag_subport, 0x00, 0, 4);
158 MLXSW_ITEM32(pci, cqe12, lag_subport, 0x00, 16, 8);
159 mlxsw_pci_cqe_item_helpers(lag_subport, 0, 12, 12);
164 MLXSW_ITEM32(pci, cqe, wqe_counter, 0x04, 16, 16);
171 MLXSW_ITEM32(pci, cqe, byte_count, 0x04, 0, 14);
173 #define MLXSW_PCI_CQE2_MIRROR_CONG_INVALID 0xFFFF
177 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
180 MLXSW_ITEM32(pci, cqe2, mirror_cong_high, 0x08, 16, 4);
185 MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
191 MLXSW_ITEM32(pci, cqe0, crc, 0x0C, 8, 1);
192 MLXSW_ITEM32(pci, cqe12, crc, 0x0C, 9, 1);
193 mlxsw_pci_cqe_item_helpers(crc, 0, 12, 12);
198 MLXSW_ITEM32(pci, cqe0, e, 0x0C, 7, 1);
199 MLXSW_ITEM32(pci, cqe12, e, 0x00, 27, 1);
200 mlxsw_pci_cqe_item_helpers(e, 0, 12, 12);
204 * 0 - Receive Queue
206 MLXSW_ITEM32(pci, cqe0, sr, 0x0C, 6, 1);
207 MLXSW_ITEM32(pci, cqe12, sr, 0x00, 26, 1);
208 mlxsw_pci_cqe_item_helpers(sr, 0, 12, 12);
213 MLXSW_ITEM32(pci, cqe0, dqn, 0x0C, 1, 5);
214 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
215 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
220 * 0: uSec - 1.024uSec (default for devices which do not support
221 * time_stamp_type). Only bits 15:0 are valid
224 * - time_stamp[29:0] = nSec
228 * - time_stamp[29:0] = nSec
229 * Formats 0..2 are configured by
234 MLXSW_ITEM32(pci, cqe2, time_stamp_low, 0x0C, 16, 16);
236 #define MLXSW_PCI_CQE2_MIRROR_TCLASS_INVALID 0x1F
240 * CPU. Value of 0x1F means that the traffic class is invalid.
242 MLXSW_ITEM32(pci, cqe2, mirror_tclass, 0x10, 27, 5);
247 MLXSW_ITEM32(pci, cqe2, tx_lag, 0x10, 24, 1);
251 * CPU. Reserved when tx_lag is 0.
253 MLXSW_ITEM32(pci, cqe2, tx_lag_subport, 0x10, 16, 8);
255 #define MLXSW_PCI_CQE2_TX_PORT_MULTI_PORT 0xFFFE
256 #define MLXSW_PCI_CQE2_TX_PORT_INVALID 0xFFFF
260 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx LAG ID
261 * is invalid. Reserved when tx_lag is 0.
263 MLXSW_ITEM32(pci, cqe2, tx_lag_id, 0x10, 0, 16);
267 * Value of 0xFFFE means multi-port. Value fo 0xFFFF means that the Tx port is
270 MLXSW_ITEM32(pci, cqe2, tx_system_port, 0x10, 0, 16);
274 * packet that does mirroring to the CPU. Value of 0xFFFF means that the
277 MLXSW_ITEM32(pci, cqe2, mirror_cong_low, 0x14, 20, 12);
292 MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
297 MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
308 * 0: uSec - 1.024uSec (default for devices which do not support
315 MLXSW_ITEM32(pci, cqe2, time_stamp_type, 0x18, 22, 2);
317 #define MLXSW_PCI_CQE2_MIRROR_LATENCY_INVALID 0xFFFFFF
322 * 0: uSec - 1.024uSec (default for devices which do not support
323 * time_stamp_type). Only bits 15:0 are valid
326 * - time_stamp[29:0] = nSec
330 * - time_stamp[29:0] = nSec
331 * Formats 0..2 are configured by
336 MLXSW_ITEM32(pci, cqe2, time_stamp_high, 0x18, 0, 22);
350 return full_ts >> 30 & 0xFF; in mlxsw_pci_cqe2_time_stamp_sec_get()
357 return full_ts & 0x3FFFFFFF; in mlxsw_pci_cqe2_time_stamp_nsec_get()
362 * Value of 0xFFFFFF means that the latency is invalid. Units are according to
365 MLXSW_ITEM32(pci, cqe2, mirror_latency, 0x1C, 8, 24);
370 MLXSW_ITEM32(pci, cqe01, owner, 0x0C, 0, 1);
371 MLXSW_ITEM32(pci, cqe2, owner, 0x1C, 0, 1);
377 MLXSW_ITEM32(pci, eqe, event_type, 0x0C, 24, 8);
378 #define MLXSW_PCI_EQE_EVENT_TYPE_COMP 0x00
379 #define MLXSW_PCI_EQE_EVENT_TYPE_CMD 0x0A
384 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
389 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
394 MLXSW_ITEM32(pci, eqe, owner, 0x0C, 0, 1);
399 MLXSW_ITEM32(pci, eqe, cmd_token, 0x00, 16, 16);
404 MLXSW_ITEM32(pci, eqe, cmd_status, 0x00, 0, 8);
409 MLXSW_ITEM32(pci, eqe, cmd_out_param_h, 0x04, 0, 32);
414 MLXSW_ITEM32(pci, eqe, cmd_out_param_l, 0x08, 0, 32);