766 	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);  in mtk_set_queue_speed()
894 	val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);  in mtk_tx_irq_disable()
895 	mtk_w32(eth, val & ~mask, eth->soc->reg_map->tx_irq_mask);  in mtk_tx_irq_disable()
905 	val = mtk_r32(eth, eth->soc->reg_map->tx_irq_mask);  in mtk_tx_irq_enable()
906 	mtk_w32(eth, val | mask, eth->soc->reg_map->tx_irq_mask);  in mtk_tx_irq_enable()
916 	val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_disable()
917 	mtk_w32(eth, val & ~mask, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_disable()
927 	val = mtk_r32(eth, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_enable()
928 	mtk_w32(eth, val | mask, eth->soc->reg_map->pdma.irq_mask);  in mtk_rx_irq_enable()
979 		const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_stats_update_mac()  local
983 		hw_stats->rx_bytes += mtk_r32(mac->hw, reg_map->gdm1_cnt + offs);  in mtk_stats_update_mac()
984 		stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x4 + offs);  in mtk_stats_update_mac()
988 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x8 + offs);  in mtk_stats_update_mac()
990 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x10 + offs);  in mtk_stats_update_mac()
992 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x14 + offs);  in mtk_stats_update_mac()
994 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x18 + offs);  in mtk_stats_update_mac()
996 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x1c + offs);  in mtk_stats_update_mac()
998 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);  in mtk_stats_update_mac()
1000 			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);  in mtk_stats_update_mac()
1004 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs);  in mtk_stats_update_mac()
1006 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs);  in mtk_stats_update_mac()
1008 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs);  in mtk_stats_update_mac()
1009 			stats =  mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs);  in mtk_stats_update_mac()
1013 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs);  in mtk_stats_update_mac()
1016 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs);  in mtk_stats_update_mac()
1018 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs);  in mtk_stats_update_mac()
1020 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs);  in mtk_stats_update_mac()
1021 			stats =  mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs);  in mtk_stats_update_mac()
1025 				mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs);  in mtk_stats_update_mac()
1179 	mtk_w32(eth, eth->phy_scratch_ring, soc->reg_map->qdma.fq_head);  in mtk_init_fq_dma()
1180 	mtk_w32(eth, phy_ring_tail, soc->reg_map->qdma.fq_tail);  in mtk_init_fq_dma()
1181 	mtk_w32(eth, (cnt << 16) | cnt, soc->reg_map->qdma.fq_count);  in mtk_init_fq_dma()
1182 	mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, soc->reg_map->qdma.fq_blen);  in mtk_init_fq_dma()
1509 			mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);  in mtk_tx_map()
1875 		mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);  in mtk_xdp_submit_frame()
2259 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_poll_tx_qdma()  local
2267 	dma = mtk_r32(eth, reg_map->qdma.drx_ptr);  in mtk_poll_tx_qdma()
2301 	mtk_w32(eth, cpu, reg_map->qdma.crx_ptr);  in mtk_poll_tx_qdma()
2383 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_napi_tx()  local
2388 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->tx_irq_status);  in mtk_napi_tx()
2394 			 mtk_r32(eth, reg_map->tx_irq_status),  in mtk_napi_tx()
2395 			 mtk_r32(eth, reg_map->tx_irq_mask));  in mtk_napi_tx()
2401 	if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)  in mtk_napi_tx()
2413 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_napi_rx()  local
2422 			reg_map->pdma.irq_status);  in mtk_napi_rx()
2429 				 mtk_r32(eth, reg_map->pdma.irq_status),  in mtk_napi_rx()
2430 				 mtk_r32(eth, reg_map->pdma.irq_mask));  in mtk_napi_rx()
2436 	} while (mtk_r32(eth, reg_map->pdma.irq_status) &  in mtk_napi_rx()
2520 		mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);  in mtk_tx_alloc()
2521 		mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);  in mtk_tx_alloc()
2524 			soc->reg_map->qdma.crx_ptr);  in mtk_tx_alloc()
2525 		mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);  in mtk_tx_alloc()
2529 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_cfg + ofs);  in mtk_tx_alloc()
2538 			mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);  in mtk_tx_alloc()
2542 		mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate);  in mtk_tx_alloc()
2544 			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);  in mtk_tx_alloc()
2549 		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);  in mtk_tx_alloc()
2587 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_rx_alloc()  local
2702 		ring->crx_idx_reg = reg_map->qdma.qcrx_ptr +  in mtk_rx_alloc()
2705 		ring->crx_idx_reg = reg_map->pdma.pcrx_ptr +  in mtk_rx_alloc()
2714 			reg_map->qdma.rx_ptr + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2716 			reg_map->qdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2718 			reg_map->qdma.rst_idx);  in mtk_rx_alloc()
2721 			reg_map->pdma.rx_ptr + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2723 			reg_map->pdma.rx_cnt_cfg + ring_no * MTK_QRX_OFFSET);  in mtk_rx_alloc()
2725 			reg_map->pdma.rst_idx);  in mtk_rx_alloc()
3047 		reg = eth->soc->reg_map->qdma.glo_cfg;  in mtk_dma_busy_wait()
3049 		reg = eth->soc->reg_map->pdma.glo_cfg;  in mtk_dma_busy_wait()
3107 			FC_THRES_MIN, eth->soc->reg_map->qdma.fc_th);  in mtk_dma_init()
3108 		mtk_w32(eth, 0x0, eth->soc->reg_map->qdma.hred);  in mtk_dma_init()
3197 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_handle_irq()  local
3199 	if (mtk_r32(eth, reg_map->pdma.irq_mask) &  in mtk_handle_irq()
3201 		if (mtk_r32(eth, reg_map->pdma.irq_status) &  in mtk_handle_irq()
3205 	if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {  in mtk_handle_irq()
3206 		if (mtk_r32(eth, reg_map->tx_irq_status) & MTK_TX_DONE_INT)  in mtk_handle_irq()
3230 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_start_dma()  local
3240 		val = mtk_r32(eth, reg_map->qdma.glo_cfg);  in mtk_start_dma()
3251 		mtk_w32(eth, val, reg_map->qdma.glo_cfg);  in mtk_start_dma()
3256 			reg_map->pdma.glo_cfg);  in mtk_start_dma()
3260 			reg_map->pdma.glo_cfg);  in mtk_start_dma()
3380 		gdm_config = soc->offload_version ? soc->reg_map->gdma_to_ppe  in mtk_open()
3479 		mtk_stop_dma(eth, eth->soc->reg_map->qdma.glo_cfg);  in mtk_stop()
3480 	mtk_stop_dma(eth, eth->soc->reg_map->pdma.glo_cfg);  in mtk_stop()
3576 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_dim_rx()  local
3584 	val = mtk_r32(eth, reg_map->pdma.delay_irq);  in mtk_dim_rx()
3594 	mtk_w32(eth, val, reg_map->pdma.delay_irq);  in mtk_dim_rx()
3596 		mtk_w32(eth, val, reg_map->qdma.delay_irq);  in mtk_dim_rx()
3607 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_dim_tx()  local
3615 	val = mtk_r32(eth, reg_map->pdma.delay_irq);  in mtk_dim_tx()
3625 	mtk_w32(eth, val, reg_map->pdma.delay_irq);  in mtk_dim_tx()
3627 		mtk_w32(eth, val, reg_map->qdma.delay_irq);  in mtk_dim_tx()
3751 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_hw_check_dma_hang()  local
3763 	wdidx = mtk_r32(eth, reg_map->wdma_base[0] + 0xc);  in mtk_hw_check_dma_hang()
3765 	val = mtk_r32(eth, reg_map->wdma_base[0] + 0x204);  in mtk_hw_check_dma_hang()
3768 	val = mtk_r32(eth, reg_map->wdma_base[0] + 0x230);  in mtk_hw_check_dma_hang()
3771 	oq_free  = (!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(24, 16)) &&  in mtk_hw_check_dma_hang()
3772 		    !(mtk_r32(eth, reg_map->pse_oq_sta + 0x4) & GENMASK(8, 0)) &&  in mtk_hw_check_dma_hang()
3773 		    !(mtk_r32(eth, reg_map->pse_oq_sta + 0x10) & GENMASK(24, 16)));  in mtk_hw_check_dma_hang()
3784 	qfsm_hang = !!mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x234);  in mtk_hw_check_dma_hang()
3785 	qfwd_hang = !mtk_r32(eth, reg_map->qdma.qtx_cfg + 0x308);  in mtk_hw_check_dma_hang()
3791 	gdm1_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x24);  in mtk_hw_check_dma_hang()
3792 	gdm2_fc = mtk_r32(eth, reg_map->gdm1_cnt + 0x64);  in mtk_hw_check_dma_hang()
3805 	oq_hang = !!(mtk_r32(eth, reg_map->pse_oq_sta) & GENMASK(8, 0));  in mtk_hw_check_dma_hang()
3807 	adma_busy = !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & GENMASK(4, 0)) &&  in mtk_hw_check_dma_hang()
3808 		    !(mtk_r32(eth, reg_map->pdma.adma_rx_dbg0) & BIT(6));  in mtk_hw_check_dma_hang()
3849 	const struct mtk_reg_map *reg_map = eth->soc->reg_map;  in mtk_hw_init()  local
3946 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);  in mtk_hw_init()
3947 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);  in mtk_hw_init()
3948 	mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);  in mtk_hw_init()
3949 	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);  in mtk_hw_init()
3968 			mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i);  in mtk_hw_init()
4850 			if (i >= ARRAY_SIZE(eth->soc->reg_map->wdma_base))  in mtk_probe()
4858 			wdma_base = eth->soc->reg_map->wdma_base[i];  in mtk_probe()
4948 			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;  in mtk_probe()
5032 	.reg_map = &mtk_reg_map,
5049 	.reg_map = &mtk_reg_map,
5069 	.reg_map = &mtk_reg_map,
5091 	.reg_map = &mtk_reg_map,
5112 	.reg_map = &mtk_reg_map,
5131 	.reg_map = &mt7986_reg_map,
5153 	.reg_map = &mt7986_reg_map,
5175 	.reg_map = &mt7988_reg_map,
5197 	.reg_map = &mt7628_reg_map,