Lines Matching +full:sci +full:- +full:intr
1 // SPDX-License-Identifier: GPL-2.0
32 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
35 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
38 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
41 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
44 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
47 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
50 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
53 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
56 stats->octet_encrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
59 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
62 stats->pkt_noactivesa_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
65 stats->pkt_toolong_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
68 stats->pkt_untagged_cnt = mcs_reg_read(mcs, reg); in mcs_get_tx_secy_stats()
76 stats->ctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
79 stats->ctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
82 stats->ctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
85 stats->ctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
88 stats->unctl_pkt_bcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
91 stats->unctl_pkt_mcast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
94 stats->unctl_octet_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
97 stats->unctl_pkt_ucast_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
100 stats->octet_decrypted_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
103 stats->octet_validated_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
106 stats->pkt_port_disabled_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
109 stats->pkt_badtag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
112 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
115 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
118 stats->pkt_tagged_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
121 stats->pkt_untaged_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
124 stats->pkt_ctl_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
126 if (mcs->hw->mcs_blks > 1) { in mcs_get_rx_secy_stats()
128 stats->pkt_notag_cnt = mcs_reg_read(mcs, reg); in mcs_get_rx_secy_stats()
142 stats->tcam_hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_flowid_stats()
152 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
155 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
156 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_stats()
158 stats->preempt_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
162 stats->tcam_miss_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
165 stats->parser_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
168 stats->sectag_insert_err_cnt = mcs_reg_read(mcs, reg); in mcs_get_port_stats()
178 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
181 stats->pkt_nosaerror_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
184 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
187 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
190 stats->pkt_nosa_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
193 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
196 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sa_stats()
207 stats->hit_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
210 stats->pkt_invalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
213 stats->pkt_late_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
216 stats->pkt_notvalid_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
219 stats->pkt_unchecked_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
221 if (mcs->hw->mcs_blks > 1) { in mcs_get_sc_stats()
223 stats->pkt_delay_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
226 stats->pkt_ok_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
228 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
230 stats->octet_decrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
233 stats->octet_validate_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
237 stats->pkt_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
240 stats->pkt_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
242 if (mcs->hw->mcs_blks == 1) { in mcs_get_sc_stats()
244 stats->octet_encrypt_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
247 stats->octet_protected_cnt = mcs_reg_read(mcs, reg); in mcs_get_sc_stats()
298 map = &mcs->rx; in mcs_clear_all_stats()
300 map = &mcs->tx; in mcs_clear_all_stats()
303 for (id = 0; id < map->flow_ids.max; id++) { in mcs_clear_all_stats()
304 if (map->flowid2pf_map[id] != pcifunc) in mcs_clear_all_stats()
310 for (id = 0; id < map->secy.max; id++) { in mcs_clear_all_stats()
311 if (map->secy2pf_map[id] != pcifunc) in mcs_clear_all_stats()
317 for (id = 0; id < map->secy.max; id++) { in mcs_clear_all_stats()
318 if (map->sc2pf_map[id] != pcifunc) in mcs_clear_all_stats()
324 for (id = 0; id < map->sa.max; id++) { in mcs_clear_all_stats()
325 if (map->sa2pf_map[id] != pcifunc) in mcs_clear_all_stats()
347 val = (map->sa_index0 & 0xFF) | in cn10kb_mcs_tx_sa_mem_map_write()
348 (map->sa_index1 & 0xFF) << 9 | in cn10kb_mcs_tx_sa_mem_map_write()
349 (map->rekey_ena & 0x1) << 18 | in cn10kb_mcs_tx_sa_mem_map_write()
350 (map->sa_index0_vld & 0x1) << 19 | in cn10kb_mcs_tx_sa_mem_map_write()
351 (map->sa_index1_vld & 0x1) << 20 | in cn10kb_mcs_tx_sa_mem_map_write()
352 (map->tx_sa_active & 0x1) << 21 | in cn10kb_mcs_tx_sa_mem_map_write()
353 map->sectag_sci << 22; in cn10kb_mcs_tx_sa_mem_map_write()
354 reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_0X(map->sc_id); in cn10kb_mcs_tx_sa_mem_map_write()
357 val = map->sectag_sci >> 42; in cn10kb_mcs_tx_sa_mem_map_write()
358 reg = MCSX_CPM_TX_SLAVE_SA_MAP_MEM_1X(map->sc_id); in cn10kb_mcs_tx_sa_mem_map_write()
366 val = (map->sa_index & 0xFF) | map->sa_in_use << 9; in cn10kb_mcs_rx_sa_mem_map_write()
368 reg = MCSX_CPM_RX_SLAVE_SA_MAP_MEMX((4 * map->sc_id) + map->an); in cn10kb_mcs_rx_sa_mem_map_write()
406 void mcs_rx_sc_cam_write(struct mcs *mcs, u64 sci, u64 secy, int sc_id) in mcs_rx_sc_cam_write() argument
408 mcs_reg_write(mcs, MCSX_CPM_RX_SLAVE_SC_CAMX(0, sc_id), sci); in mcs_rx_sc_cam_write()
425 if (mcs->hw->mcs_blks == 1 && dir == MCS_RX) in mcs_secy_plcy_write()
433 val = (map->secy & 0x7F) | (map->ctrl_pkt & 0x1) << 8; in cn10kb_mcs_flowid_secy_map()
435 reg = MCSX_CPM_RX_SLAVE_SECY_MAP_MEMX(map->flow_id); in cn10kb_mcs_flowid_secy_map()
437 val |= (map->sc & 0x7F) << 9; in cn10kb_mcs_flowid_secy_map()
438 reg = MCSX_CPM_TX_SLAVE_SECY_MAP_MEM_0X(map->flow_id); in cn10kb_mcs_flowid_secy_map()
500 flow_id = mcs->hw->tcam_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
501 __set_bit(flow_id, mcs->rx.flow_ids.bmap); in mcs_install_flowid_bypass_entry()
502 __set_bit(flow_id, mcs->tx.flow_ids.bmap); in mcs_install_flowid_bypass_entry()
513 secy_id = mcs->hw->secy_entries - MCS_RSRC_RSVD_CNT; in mcs_install_flowid_bypass_entry()
514 __set_bit(secy_id, mcs->rx.secy.bmap); in mcs_install_flowid_bypass_entry()
515 __set_bit(secy_id, mcs->tx.secy.bmap); in mcs_install_flowid_bypass_entry()
519 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
525 if (mcs->hw->mcs_blks > 1) in mcs_install_flowid_bypass_entry()
533 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_RX); in mcs_install_flowid_bypass_entry()
535 mcs->mcs_ops->mcs_flowid_secy_map(mcs, &map, MCS_TX); in mcs_install_flowid_bypass_entry()
550 map = &mcs->rx; in mcs_clear_secy_plcy()
552 map = &mcs->tx; in mcs_clear_secy_plcy()
558 for (flow_id = 0; flow_id < map->flow_ids.max; flow_id++) { in mcs_clear_secy_plcy()
559 if (map->flowid2secy_map[flow_id] != secy_id) in mcs_clear_secy_plcy()
569 if (!rsrc->bmap) in mcs_alloc_ctrlpktrule()
570 return -EINVAL; in mcs_alloc_ctrlpktrule()
572 rsrc_id = bitmap_find_next_zero_area(rsrc->bmap, rsrc->max, offset, 1, 0); in mcs_alloc_ctrlpktrule()
573 if (rsrc_id >= rsrc->max) in mcs_alloc_ctrlpktrule()
574 return -ENOSPC; in mcs_alloc_ctrlpktrule()
576 bitmap_set(rsrc->bmap, rsrc_id, 1); in mcs_alloc_ctrlpktrule()
584 u16 pcifunc = req->hdr.pcifunc; in mcs_free_ctrlpktrule()
589 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ENABLE : MCSX_PEX_TX_SLAVE_RULE_ENABLE; in mcs_free_ctrlpktrule()
590 map = (req->dir == MCS_RX) ? &mcs->rx : &mcs->tx; in mcs_free_ctrlpktrule()
592 if (req->all) { in mcs_free_ctrlpktrule()
593 for (id = 0; id < map->ctrlpktrule.max; id++) { in mcs_free_ctrlpktrule()
594 if (map->ctrlpktrule2pf_map[id] != pcifunc) in mcs_free_ctrlpktrule()
596 mcs_free_rsrc(&map->ctrlpktrule, map->ctrlpktrule2pf_map, id, pcifunc); in mcs_free_ctrlpktrule()
604 rc = mcs_free_rsrc(&map->ctrlpktrule, map->ctrlpktrule2pf_map, req->rule_idx, pcifunc); in mcs_free_ctrlpktrule()
606 dis &= ~BIT_ULL(req->rule_idx); in mcs_free_ctrlpktrule()
617 switch (req->rule_type) { in mcs_ctrlpktrule_write()
619 req->data0 &= GENMASK(15, 0); in mcs_ctrlpktrule_write()
620 if (req->data0 != ETH_P_PAE) in mcs_ctrlpktrule_write()
621 return -EINVAL; in mcs_ctrlpktrule_write()
623 idx = req->rule_idx - MCS_CTRLPKT_ETYPE_RULE_OFFSET; in mcs_ctrlpktrule_write()
624 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ETYPE_CFGX(idx) : in mcs_ctrlpktrule_write()
627 mcs_reg_write(mcs, reg, req->data0); in mcs_ctrlpktrule_write()
630 if (!(req->data0 & BIT_ULL(40))) in mcs_ctrlpktrule_write()
631 return -EINVAL; in mcs_ctrlpktrule_write()
633 idx = req->rule_idx - MCS_CTRLPKT_DA_RULE_OFFSET; in mcs_ctrlpktrule_write()
634 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_DAX(idx) : in mcs_ctrlpktrule_write()
637 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
640 if (!(req->data0 & BIT_ULL(40)) || !(req->data1 & BIT_ULL(40))) in mcs_ctrlpktrule_write()
641 return -EINVAL; in mcs_ctrlpktrule_write()
643 idx = req->rule_idx - MCS_CTRLPKT_DA_RANGE_RULE_OFFSET; in mcs_ctrlpktrule_write()
644 if (req->dir == MCS_RX) { in mcs_ctrlpktrule_write()
646 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
648 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
651 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
653 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
657 req->data2 &= GENMASK(15, 0); in mcs_ctrlpktrule_write()
658 if (req->data2 != ETH_P_PAE || !(req->data0 & BIT_ULL(40)) || in mcs_ctrlpktrule_write()
659 !(req->data1 & BIT_ULL(40))) in mcs_ctrlpktrule_write()
660 return -EINVAL; in mcs_ctrlpktrule_write()
662 idx = req->rule_idx - MCS_CTRLPKT_COMBO_RULE_OFFSET; in mcs_ctrlpktrule_write()
663 if (req->dir == MCS_RX) { in mcs_ctrlpktrule_write()
665 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
667 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
669 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
672 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
674 mcs_reg_write(mcs, reg, req->data1 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
676 mcs_reg_write(mcs, reg, req->data2); in mcs_ctrlpktrule_write()
680 if (!(req->data0 & BIT_ULL(40))) in mcs_ctrlpktrule_write()
681 return -EINVAL; in mcs_ctrlpktrule_write()
683 idx = req->rule_idx - MCS_CTRLPKT_MAC_EN_RULE_OFFSET; in mcs_ctrlpktrule_write()
684 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_MAC : in mcs_ctrlpktrule_write()
687 mcs_reg_write(mcs, reg, req->data0 & GENMASK_ULL(47, 0)); in mcs_ctrlpktrule_write()
691 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_RULE_ENABLE : MCSX_PEX_TX_SLAVE_RULE_ENABLE; in mcs_ctrlpktrule_write()
694 enb |= BIT_ULL(req->rule_idx); in mcs_ctrlpktrule_write()
704 return -EINVAL; in mcs_free_rsrc()
718 map = &mcs->rx; in mcs_free_all_rsrc()
720 map = &mcs->tx; in mcs_free_all_rsrc()
723 for (id = 0; id < map->flow_ids.max; id++) { in mcs_free_all_rsrc()
724 if (map->flowid2pf_map[id] != pcifunc) in mcs_free_all_rsrc()
726 mcs_free_rsrc(&map->flow_ids, map->flowid2pf_map, in mcs_free_all_rsrc()
732 for (id = 0; id < map->secy.max; id++) { in mcs_free_all_rsrc()
733 if (map->secy2pf_map[id] != pcifunc) in mcs_free_all_rsrc()
735 mcs_free_rsrc(&map->secy, map->secy2pf_map, in mcs_free_all_rsrc()
741 for (id = 0; id < map->secy.max; id++) { in mcs_free_all_rsrc()
742 if (map->sc2pf_map[id] != pcifunc) in mcs_free_all_rsrc()
744 mcs_free_rsrc(&map->sc, map->sc2pf_map, id, pcifunc); in mcs_free_all_rsrc()
752 for (id = 0; id < map->sa.max; id++) { in mcs_free_all_rsrc()
753 if (map->sa2pf_map[id] != pcifunc) in mcs_free_all_rsrc()
755 mcs_free_rsrc(&map->sa, map->sa2pf_map, id, pcifunc); in mcs_free_all_rsrc()
766 return -ENOMEM; in mcs_alloc_rsrc()
778 map = &mcs->rx; in mcs_alloc_all_rsrc()
780 map = &mcs->tx; in mcs_alloc_all_rsrc()
782 id = mcs_alloc_rsrc(&map->flow_ids, map->flowid2pf_map, pcifunc); in mcs_alloc_all_rsrc()
784 return -ENOMEM; in mcs_alloc_all_rsrc()
787 id = mcs_alloc_rsrc(&map->secy, map->secy2pf_map, pcifunc); in mcs_alloc_all_rsrc()
789 return -ENOMEM; in mcs_alloc_all_rsrc()
792 id = mcs_alloc_rsrc(&map->sc, map->sc2pf_map, pcifunc); in mcs_alloc_all_rsrc()
794 return -ENOMEM; in mcs_alloc_all_rsrc()
797 id = mcs_alloc_rsrc(&map->sa, map->sa2pf_map, pcifunc); in mcs_alloc_all_rsrc()
799 return -ENOMEM; in mcs_alloc_all_rsrc()
802 id = mcs_alloc_rsrc(&map->sa, map->sa2pf_map, pcifunc); in mcs_alloc_all_rsrc()
804 return -ENOMEM; in mcs_alloc_all_rsrc()
817 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_wrapped_handler()
819 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_wrapped_handler()
822 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_wrapped_handler()
825 if (mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_wrapped_handler()
832 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_wrapped_handler()
844 sc_bmap = &mcs->tx.sc; in cn10kb_mcs_tx_pn_thresh_reached_handler()
846 event.mcs_id = mcs->mcs_id; in cn10kb_mcs_tx_pn_thresh_reached_handler()
854 for_each_set_bit(sc, sc_bmap->bmap, mcs->hw->sc_entries) { in cn10kb_mcs_tx_pn_thresh_reached_handler()
863 if (status == mcs->tx_sa_active[sc]) in cn10kb_mcs_tx_pn_thresh_reached_handler()
871 event.pcifunc = mcs->tx.sa2pf_map[event.sa_id]; in cn10kb_mcs_tx_pn_thresh_reached_handler()
880 u64 intr; in mcs_rx_pn_thresh_reached_handler() local
883 for (reg = 0; reg < (mcs->hw->sa_entries / 64); reg++) { in mcs_rx_pn_thresh_reached_handler()
887 intr = mcs_reg_read(mcs, MCSX_CPM_RX_SLAVE_PN_THRESH_REACHEDX(reg)); in mcs_rx_pn_thresh_reached_handler()
889 if (!(intr & BIT_ULL(sa))) in mcs_rx_pn_thresh_reached_handler()
892 event.mcs_id = mcs->mcs_id; in mcs_rx_pn_thresh_reached_handler()
895 event.pcifunc = mcs->rx.sa2pf_map[event.sa_id]; in mcs_rx_pn_thresh_reached_handler()
901 static void mcs_rx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_rx_misc_intr_handler() argument
905 event.mcs_id = mcs->mcs_id; in mcs_rx_misc_intr_handler()
906 event.pcifunc = mcs->pf_map[0]; in mcs_rx_misc_intr_handler()
908 if (intr & MCS_CPM_RX_INT_SECTAG_V_EQ1) in mcs_rx_misc_intr_handler()
910 if (intr & MCS_CPM_RX_INT_SECTAG_E_EQ0_C_EQ1) in mcs_rx_misc_intr_handler()
912 if (intr & MCS_CPM_RX_INT_SL_GTE48) in mcs_rx_misc_intr_handler()
914 if (intr & MCS_CPM_RX_INT_ES_EQ1_SC_EQ1) in mcs_rx_misc_intr_handler()
916 if (intr & MCS_CPM_RX_INT_SC_EQ1_SCB_EQ1) in mcs_rx_misc_intr_handler()
918 if (intr & MCS_CPM_RX_INT_PACKET_XPN_EQ0) in mcs_rx_misc_intr_handler()
924 static void mcs_tx_misc_intr_handler(struct mcs *mcs, u64 intr) in mcs_tx_misc_intr_handler() argument
928 if (!(intr & MCS_CPM_TX_INT_SA_NOT_VALID)) in mcs_tx_misc_intr_handler()
931 event.mcs_id = mcs->mcs_id; in mcs_tx_misc_intr_handler()
932 event.pcifunc = mcs->pf_map[0]; in mcs_tx_misc_intr_handler()
939 void cn10kb_mcs_bbe_intr_handler(struct mcs *mcs, u64 intr, in cn10kb_mcs_bbe_intr_handler() argument
945 if (!(intr & 0x6ULL)) in cn10kb_mcs_bbe_intr_handler()
948 if (intr & BIT_ULL(1)) in cn10kb_mcs_bbe_intr_handler()
957 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in cn10kb_mcs_bbe_intr_handler()
960 dev_warn(mcs->dev, "BEE:Policy or data overflow occurred on lmac:%d\n", lmac); in cn10kb_mcs_bbe_intr_handler()
964 void cn10kb_mcs_pab_intr_handler(struct mcs *mcs, u64 intr, in cn10kb_mcs_pab_intr_handler() argument
969 if (!(intr & 0xFFFFFULL)) in cn10kb_mcs_pab_intr_handler()
972 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in cn10kb_mcs_pab_intr_handler()
973 if (intr & BIT_ULL(lmac)) in cn10kb_mcs_pab_intr_handler()
974 dev_warn(mcs->dev, "PAB: overflow occurred on lmac:%d\n", lmac); in cn10kb_mcs_pab_intr_handler()
981 u64 intr, cpm_intr, bbe_intr, pab_intr; in mcs_ip_intr_handler() local
987 intr = mcs_reg_read(mcs, MCSX_TOP_SLAVE_INT_SUM); in mcs_ip_intr_handler()
990 if (intr & MCS_CPM_RX_INT_ENA) { in mcs_ip_intr_handler()
1005 if (intr & MCS_CPM_TX_INT_ENA) { in mcs_ip_intr_handler()
1009 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1019 if (mcs->hw->mcs_blks > 1) in mcs_ip_intr_handler()
1029 if (intr & MCS_BBE_RX_INT_ENA) { in mcs_ip_intr_handler()
1031 mcs->mcs_ops->mcs_bbe_intr_handler(mcs, bbe_intr, MCS_RX); in mcs_ip_intr_handler()
1039 if (intr & MCS_BBE_TX_INT_ENA) { in mcs_ip_intr_handler()
1041 mcs->mcs_ops->mcs_bbe_intr_handler(mcs, bbe_intr, MCS_TX); in mcs_ip_intr_handler()
1049 if (intr & MCS_PAB_RX_INT_ENA) { in mcs_ip_intr_handler()
1051 mcs->mcs_ops->mcs_pab_intr_handler(mcs, pab_intr, MCS_RX); in mcs_ip_intr_handler()
1059 if (intr & MCS_PAB_TX_INT_ENA) { in mcs_ip_intr_handler()
1061 mcs->mcs_ops->mcs_pab_intr_handler(mcs, pab_intr, MCS_TX); in mcs_ip_intr_handler()
1077 return devm_kcalloc(mcs->dev, n, sizeof(u16), GFP_KERNEL); in alloc_mem()
1082 struct hwinfo *hw = mcs->hw; in mcs_alloc_struct_mem()
1085 res->flowid2pf_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1086 if (!res->flowid2pf_map) in mcs_alloc_struct_mem()
1087 return -ENOMEM; in mcs_alloc_struct_mem()
1089 res->secy2pf_map = alloc_mem(mcs, hw->secy_entries); in mcs_alloc_struct_mem()
1090 if (!res->secy2pf_map) in mcs_alloc_struct_mem()
1091 return -ENOMEM; in mcs_alloc_struct_mem()
1093 res->sc2pf_map = alloc_mem(mcs, hw->sc_entries); in mcs_alloc_struct_mem()
1094 if (!res->sc2pf_map) in mcs_alloc_struct_mem()
1095 return -ENOMEM; in mcs_alloc_struct_mem()
1097 res->sa2pf_map = alloc_mem(mcs, hw->sa_entries); in mcs_alloc_struct_mem()
1098 if (!res->sa2pf_map) in mcs_alloc_struct_mem()
1099 return -ENOMEM; in mcs_alloc_struct_mem()
1101 res->flowid2secy_map = alloc_mem(mcs, hw->tcam_entries); in mcs_alloc_struct_mem()
1102 if (!res->flowid2secy_map) in mcs_alloc_struct_mem()
1103 return -ENOMEM; in mcs_alloc_struct_mem()
1105 res->ctrlpktrule2pf_map = alloc_mem(mcs, MCS_MAX_CTRLPKT_RULES); in mcs_alloc_struct_mem()
1106 if (!res->ctrlpktrule2pf_map) in mcs_alloc_struct_mem()
1107 return -ENOMEM; in mcs_alloc_struct_mem()
1109 res->flow_ids.max = hw->tcam_entries - MCS_RSRC_RSVD_CNT; in mcs_alloc_struct_mem()
1110 err = rvu_alloc_bitmap(&res->flow_ids); in mcs_alloc_struct_mem()
1114 res->secy.max = hw->secy_entries - MCS_RSRC_RSVD_CNT; in mcs_alloc_struct_mem()
1115 err = rvu_alloc_bitmap(&res->secy); in mcs_alloc_struct_mem()
1119 res->sc.max = hw->sc_entries; in mcs_alloc_struct_mem()
1120 err = rvu_alloc_bitmap(&res->sc); in mcs_alloc_struct_mem()
1124 res->sa.max = hw->sa_entries; in mcs_alloc_struct_mem()
1125 err = rvu_alloc_bitmap(&res->sa); in mcs_alloc_struct_mem()
1129 res->ctrlpktrule.max = MCS_MAX_CTRLPKT_RULES; in mcs_alloc_struct_mem()
1130 err = rvu_alloc_bitmap(&res->ctrlpktrule); in mcs_alloc_struct_mem()
1141 mcs->num_vec = pci_msix_vec_count(mcs->pdev); in mcs_register_interrupts()
1143 ret = pci_alloc_irq_vectors(mcs->pdev, mcs->num_vec, in mcs_register_interrupts()
1144 mcs->num_vec, PCI_IRQ_MSIX); in mcs_register_interrupts()
1146 dev_err(mcs->dev, "MCS Request for %d msix vector failed err:%d\n", in mcs_register_interrupts()
1147 mcs->num_vec, ret); in mcs_register_interrupts()
1151 ret = request_irq(pci_irq_vector(mcs->pdev, mcs->hw->ip_vec), in mcs_register_interrupts()
1154 dev_err(mcs->dev, "MCS IP irq registration failed\n"); in mcs_register_interrupts()
1176 mcs->tx_sa_active = alloc_mem(mcs, mcs->hw->sc_entries); in mcs_register_interrupts()
1177 if (!mcs->tx_sa_active) { in mcs_register_interrupts()
1178 ret = -ENOMEM; in mcs_register_interrupts()
1185 free_irq(pci_irq_vector(mcs->pdev, mcs->hw->ip_vec), mcs); in mcs_register_interrupts()
1187 pci_free_irq_vectors(mcs->pdev); in mcs_register_interrupts()
1188 mcs->num_vec = 0; in mcs_register_interrupts()
1195 int idmax = -ENODEV; in mcs_get_blkcnt()
1202 if (mcs->mcs_id > idmax) in mcs_get_blkcnt()
1203 idmax = mcs->mcs_id; in mcs_get_blkcnt()
1216 if (mcs_dev->mcs_id == mcs_id) in mcs_get_pdata()
1226 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id), in mcs_set_port_cfg()
1227 req->port_mode & MCS_PORT_MODE_MASK); in mcs_set_port_cfg()
1229 req->cstm_tag_rel_mode_sel &= 0x3; in mcs_set_port_cfg()
1231 if (mcs->hw->mcs_blks > 1) { in mcs_set_port_cfg()
1232 req->fifo_skid &= MCS_PORT_FIFO_SKID_MASK; in mcs_set_port_cfg()
1233 val = (u32)req->fifo_skid << 0x10; in mcs_set_port_cfg()
1234 val |= req->fifo_skid; in mcs_set_port_cfg()
1235 mcs_reg_write(mcs, MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id), val); in mcs_set_port_cfg()
1236 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id), in mcs_set_port_cfg()
1237 req->cstm_tag_rel_mode_sel); in mcs_set_port_cfg()
1240 if (req->custom_hdr_enb) in mcs_set_port_cfg()
1241 val |= BIT_ULL(req->port_id); in mcs_set_port_cfg()
1243 val &= ~BIT_ULL(req->port_id); in mcs_set_port_cfg()
1247 val = mcs_reg_read(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id)); in mcs_set_port_cfg()
1248 val |= (req->cstm_tag_rel_mode_sel << 2); in mcs_set_port_cfg()
1249 mcs_reg_write(mcs, MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id), val); in mcs_set_port_cfg()
1258 rsp->port_mode = mcs_reg_read(mcs, MCSX_PAB_RX_SLAVE_PORT_CFGX(req->port_id)) & in mcs_get_port_cfg()
1261 if (mcs->hw->mcs_blks > 1) { in mcs_get_port_cfg()
1262 reg = MCSX_PAB_RX_SLAVE_FIFO_SKID_CFGX(req->port_id); in mcs_get_port_cfg()
1263 rsp->fifo_skid = mcs_reg_read(mcs, reg) & MCS_PORT_FIFO_SKID_MASK; in mcs_get_port_cfg()
1264 reg = MCSX_PEX_TX_SLAVE_CUSTOM_TAG_REL_MODE_SEL(req->port_id); in mcs_get_port_cfg()
1265 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) & 0x3; in mcs_get_port_cfg()
1266 if (mcs_reg_read(mcs, MCSX_PEX_RX_SLAVE_PEX_CONFIGURATION) & BIT_ULL(req->port_id)) in mcs_get_port_cfg()
1267 rsp->custom_hdr_enb = 1; in mcs_get_port_cfg()
1269 reg = MCSX_PEX_TX_SLAVE_PORT_CONFIG(req->port_id); in mcs_get_port_cfg()
1270 rsp->cstm_tag_rel_mode_sel = mcs_reg_read(mcs, reg) >> 2; in mcs_get_port_cfg()
1273 rsp->port_id = req->port_id; in mcs_get_port_cfg()
1274 rsp->mcs_id = req->mcs_id; in mcs_get_port_cfg()
1284 if (mcs->hw->mcs_blks > 1) in mcs_get_custom_tag_cfg()
1285 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_CUSTOM_TAGX(idx) : in mcs_get_custom_tag_cfg()
1288 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_VLAN_CFGX(idx) : in mcs_get_custom_tag_cfg()
1292 if (mcs->hw->mcs_blks > 1) { in mcs_get_custom_tag_cfg()
1293 rsp->cstm_etype[idx] = val & GENMASK(15, 0); in mcs_get_custom_tag_cfg()
1294 rsp->cstm_indx[idx] = (val >> 0x16) & 0x3; in mcs_get_custom_tag_cfg()
1295 reg = (req->dir == MCS_RX) ? MCSX_PEX_RX_SLAVE_ETYPE_ENABLE : in mcs_get_custom_tag_cfg()
1297 rsp->cstm_etype_en = mcs_reg_read(mcs, reg) & 0xFF; in mcs_get_custom_tag_cfg()
1299 rsp->cstm_etype[idx] = (val >> 0x1) & GENMASK(15, 0); in mcs_get_custom_tag_cfg()
1300 rsp->cstm_indx[idx] = (val >> 0x11) & 0x3; in mcs_get_custom_tag_cfg()
1301 rsp->cstm_etype_en |= (val & 0x1) << idx; in mcs_get_custom_tag_cfg()
1305 rsp->mcs_id = req->mcs_id; in mcs_get_custom_tag_cfg()
1306 rsp->dir = req->dir; in mcs_get_custom_tag_cfg()
1332 if (pn->dir == MCS_RX) in mcs_pn_threshold_set()
1333 reg = pn->xpn ? MCSX_CPM_RX_SLAVE_XPN_THRESHOLD : MCSX_CPM_RX_SLAVE_PN_THRESHOLD; in mcs_pn_threshold_set()
1335 reg = pn->xpn ? MCSX_CPM_TX_SLAVE_XPN_THRESHOLD : MCSX_CPM_TX_SLAVE_PN_THRESHOLD; in mcs_pn_threshold_set()
1337 mcs_reg_write(mcs, reg, pn->threshold); in mcs_pn_threshold_set()
1373 if (mcs->hw->mcs_blks > 1) { in mcs_lmac_init()
1391 return -ENODEV; in mcs_set_lmac_channels()
1392 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) { in mcs_set_lmac_channels()
1420 err = -EBUSY; in mcs_x2p_calibration()
1421 dev_err(mcs->dev, "MCS X2P calibration failed..ignoring\n"); in mcs_x2p_calibration()
1427 for (i = 0; i < mcs->hw->mcs_x2p_intf; i++) { in mcs_x2p_calibration()
1430 err = -EBUSY; in mcs_x2p_calibration()
1431 dev_err(mcs->dev, "MCS:%d didn't respond to X2P calibration\n", i); in mcs_x2p_calibration()
1462 if (mcs->hw->mcs_blks == 1) { in mcs_global_cfg()
1473 struct hwinfo *hw = mcs->hw; in cn10kb_mcs_set_hw_capabilities()
1475 hw->tcam_entries = 128; /* TCAM entries */ in cn10kb_mcs_set_hw_capabilities()
1476 hw->secy_entries = 128; /* SecY entries */ in cn10kb_mcs_set_hw_capabilities()
1477 hw->sc_entries = 128; /* SC CAM entries */ in cn10kb_mcs_set_hw_capabilities()
1478 hw->sa_entries = 256; /* SA entries */ in cn10kb_mcs_set_hw_capabilities()
1479 hw->lmac_cnt = 20; /* lmacs/ports per mcs block */ in cn10kb_mcs_set_hw_capabilities()
1480 hw->mcs_x2p_intf = 5; /* x2p clabration intf */ in cn10kb_mcs_set_hw_capabilities()
1481 hw->mcs_blks = 1; /* MCS blocks */ in cn10kb_mcs_set_hw_capabilities()
1482 hw->ip_vec = MCS_CN10KB_INT_VEC_IP; /* IP vector */ in cn10kb_mcs_set_hw_capabilities()
1497 struct device *dev = &pdev->dev; in mcs_probe()
1503 return -ENOMEM; in mcs_probe()
1505 mcs->hw = devm_kzalloc(dev, sizeof(struct hwinfo), GFP_KERNEL); in mcs_probe()
1506 if (!mcs->hw) in mcs_probe()
1507 return -ENOMEM; in mcs_probe()
1522 mcs->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); in mcs_probe()
1523 if (!mcs->reg_base) { in mcs_probe()
1525 err = -ENOMEM; in mcs_probe()
1530 mcs->pdev = pdev; in mcs_probe()
1531 mcs->dev = &pdev->dev; in mcs_probe()
1533 if (pdev->subsystem_device == PCI_SUBSYS_DEVID_CN10K_B) in mcs_probe()
1534 mcs->mcs_ops = &cn10kb_mcs_ops; in mcs_probe()
1536 mcs->mcs_ops = cnf10kb_get_mac_ops(); in mcs_probe()
1539 mcs->mcs_ops->mcs_set_hw_capabilities(mcs); in mcs_probe()
1548 mcs->mcs_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) in mcs_probe()
1552 err = mcs_alloc_struct_mem(mcs, &mcs->tx); in mcs_probe()
1557 err = mcs_alloc_struct_mem(mcs, &mcs->rx); in mcs_probe()
1562 for (lmac = 0; lmac < mcs->hw->lmac_cnt; lmac++) in mcs_probe()
1566 mcs->mcs_ops->mcs_parser_cfg(mcs); in mcs_probe()
1572 list_add(&mcs->mcs_list, &mcs_list); in mcs_probe()
1573 mutex_init(&mcs->stats_lock); in mcs_probe()
1593 free_irq(pci_irq_vector(pdev, mcs->hw->ip_vec), mcs); in mcs_remove()