Lines Matching refs:mvreg_read
768 static u32 mvreg_read(struct mvneta_port *pp, u32 offset) in mvreg_read() function
797 mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); in mvneta_mib_counters_clear()
798 mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); in mvneta_mib_counters_clear()
799 mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); in mvneta_mib_counters_clear()
880 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); in mvneta_rxq_busy_desc_num_get()
936 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); in mvneta_max_rx_size_set()
951 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); in mvneta_rxq_offset_set()
1008 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); in mvneta_rxq_buf_size_set()
1022 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); in mvneta_rxq_bm_disable()
1033 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); in mvneta_rxq_bm_enable()
1044 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); in mvneta_rxq_long_pool_set()
1057 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); in mvneta_rxq_short_pool_set()
1078 val = mvreg_read(pp, MVNETA_PORT_POOL_BUFFER_SZ_REG(pool_id)); in mvneta_bm_pool_bufsize_set()
1090 win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE); in mvneta_mbus_io_win_set()
1117 win_protect = mvreg_read(pp, MVNETA_ACCESS_PROTECT_ENABLE); in mvneta_mbus_io_win_set()
1284 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; in mvneta_port_down()
1302 val = mvreg_read(pp, MVNETA_RXQ_CMD); in mvneta_port_down()
1308 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; in mvneta_port_down()
1326 val = mvreg_read(pp, MVNETA_TXQ_CMD); in mvneta_port_down()
1341 val = mvreg_read(pp, MVNETA_PORT_STATUS); in mvneta_port_down()
1354 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); in mvneta_port_enable()
1365 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); in mvneta_port_disable()
1576 val = mvreg_read(pp, MVNETA_UNIT_CONTROL); in mvneta_defaults_set()
1604 val = mvreg_read(pp, MVNETA_TX_MTU); in mvneta_txq_max_tx_size_set()
1610 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); in mvneta_txq_max_tx_size_set()
1620 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); in mvneta_txq_max_tx_size_set()
1649 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); in mvneta_set_ucast_addr()
1713 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); in mvneta_tx_done_pkts_coal_set()
1758 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); in mvneta_txq_sent_desc_num_get()
3084 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST in mvneta_set_special_mcast_addr()
3117 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); in mvneta_set_other_mcast_addr()
3178 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); in mvneta_rx_unicast_promisc_set()
3180 val = mvreg_read(pp, MVNETA_TYPE_PRIO); in mvneta_rx_unicast_promisc_set()
3260 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); in mvneta_link_change()
3286 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); in mvneta_poll()
3288 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); in mvneta_poll()
3927 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); in mvneta_get_mac_addr()
3928 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); in mvneta_get_mac_addr()
3984 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); in mvneta_pcs_get_state()
4051 old_an = an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_pcs_config()
4064 u32 gmac_an = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_pcs_an_restart()
4102 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_mac_prepare()
4127 u32 new_ctrl0, gmac_ctrl0 = mvreg_read(pp, MVNETA_GMAC_CTRL_0); in mvneta_mac_config()
4128 u32 new_ctrl2, gmac_ctrl2 = mvreg_read(pp, MVNETA_GMAC_CTRL_2); in mvneta_mac_config()
4129 u32 new_ctrl4, gmac_ctrl4 = mvreg_read(pp, MVNETA_GMAC_CTRL_4); in mvneta_mac_config()
4172 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & in mvneta_mac_config()
4187 clk = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); in mvneta_mac_finish()
4200 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_mac_finish()
4212 lpi_ctl1 = mvreg_read(pp, MVNETA_LPI_CTRL_1); in mvneta_set_eee()
4230 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_mac_link_down()
4251 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_mac_link_up()
4276 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); in mvneta_mac_link_up()
4361 txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & in mvneta_percpu_elect()
5092 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); in mvneta_ethtool_get_eee()
5114 lpi_ctl0 = mvreg_read(pp, MVNETA_LPI_CTRL_0); in mvneta_ethtool_set_eee()
5134 u32 val = mvreg_read(pp, MVNETA_VLAN_PRIO_TO_RXQ); in mvneta_map_vlan_prio_to_rxq()
5159 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); in mvneta_enable_per_queue_rate_limit()
5171 u32 val = mvreg_read(pp, MVNETA_TXQ_CMD1_REG); in mvneta_disable_per_queue_rate_limit()