43 #define xw32(reg, val)	iowrite32(val, ioaddr + (reg))  macro
363 	xw32(CSR5, status);  in xircom_interrupt()
508 	xw32(CSR0, val);  in initialize_card()
514 	xw32(CSR0, val);  in initialize_card()
519 	xw32(CSR0, val);  in initialize_card()
539 	xw32(CSR1, 0);  in trigger_transmit()
553 	xw32(CSR2, 0);  in trigger_receive()
592 	xw32(CSR3, address);	/* Receive descr list address */  in setup_descriptors()
617 	xw32(CSR4, address);	/* xmit descr list address */  in setup_descriptors()
630 	xw32(CSR3, val);	/* Receive descriptor address */  in remove_descriptors()
631 	xw32(CSR4, val);	/* Send descriptor address */  in remove_descriptors()
652 	xw32(CSR5, val);  in link_status_changed()
711 	xw32(CSR6, val);  in activate_receiver()
727 	xw32(CSR6, val);  in activate_receiver()
758 	xw32(CSR6, val);  in deactivate_receiver()
797 	xw32(CSR6, val);  in activate_transmitter()
814 	xw32(CSR6, val);  in activate_transmitter()
845 	xw32(CSR6, val);  in deactivate_transmitter()
873 	xw32(CSR7, val);  in enable_transmit_interrupt()
889 	xw32(CSR7, val);  in enable_receive_interrupt()
904 	xw32(CSR7, val);  in enable_link_interrupt()
918 	xw32(CSR7, 0);  in disable_all_interrupts()
940 	xw32(CSR7, val);  in enable_common_interrupts()
955 	xw32(CSR6, val);  in enable_promisc()
1005 	xw32(CSR9, 1 << 12);	/* enable boot rom access */  in read_mac_address()
1009 		xw32(CSR10, i);  in read_mac_address()
1011 		xw32(CSR10, i + 1);  in read_mac_address()
1013 		xw32(CSR10, i + 2);  in read_mac_address()
1015 		xw32(CSR10, i + 3);  in read_mac_address()
1022 				xw32(CSR10, i + j + 4);  in read_mac_address()
1053 	xw32(CSR15, 0x0008);  in transceiver_voodoo()
1055 	xw32(CSR15, 0xa8050000);  in transceiver_voodoo()
1057 	xw32(CSR15, 0xa00f0000);  in transceiver_voodoo()