92 #define tg3_flag(tp, flag)				\  argument
93 	_tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 #define tg3_flag_set(tp, flag)				\  argument
95 	_tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define tg3_flag_clear(tp, flag)			\  argument
97 	_tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
130 #define TG3_MAX_MTU(tp)	\  argument
131 	(tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
137 #define TG3_RX_STD_RING_SIZE(tp) \  argument
138 	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 #define TG3_RX_JMB_RING_SIZE(tp) \  argument
142 	(tg3_flag(tp, LRG_PROD_RING_CAP) ? \
156 #define TG3_RX_STD_RING_BYTES(tp) \  argument
157 	(sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
158 #define TG3_RX_JMB_RING_BYTES(tp) \  argument
159 	(sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
160 #define TG3_RX_RCB_RING_BYTES(tp) \  argument
161 	(sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
176 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \  argument
177 	(sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \  argument
180 	(sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
195 	#define TG3_RX_COPY_THRESH(tp)	TG3_RX_COPY_THRESHOLD  argument
197 	#define TG3_RX_COPY_THRESH(tp)	((tp)->rx_copy_thresh)  argument
201 #define TG3_RX_OFFSET(tp)	((tp)->rx_offset)  argument
203 #define TG3_RX_OFFSET(tp)	(NET_SKB_PAD)  argument
213 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)  argument
214 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)  argument
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)  in tg3_write32()  argument
472 	writel(val, tp->regs + off);  in tg3_write32()
475 static u32 tg3_read32(struct tg3 *tp, u32 off)  in tg3_read32()  argument
477 	return readl(tp->regs + off);  in tg3_read32()
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)  in tg3_ape_write32()  argument
482 	writel(val, tp->aperegs + off);  in tg3_ape_write32()
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)  in tg3_ape_read32()  argument
487 	return readl(tp->aperegs + off);  in tg3_ape_read32()
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)  in tg3_write_indirect_reg32()  argument
494 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_indirect_reg32()
495 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);  in tg3_write_indirect_reg32()
496 	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);  in tg3_write_indirect_reg32()
497 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_indirect_reg32()
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)  in tg3_write_flush_reg32()  argument
502 	writel(val, tp->regs + off);  in tg3_write_flush_reg32()
503 	readl(tp->regs + off);  in tg3_write_flush_reg32()
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)  in tg3_read_indirect_reg32()  argument
511 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_indirect_reg32()
512 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);  in tg3_read_indirect_reg32()
513 	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);  in tg3_read_indirect_reg32()
514 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_indirect_reg32()
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)  in tg3_write_indirect_mbox()  argument
523 		pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +  in tg3_write_indirect_mbox()
528 		pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +  in tg3_write_indirect_mbox()
533 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_indirect_mbox()
534 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);  in tg3_write_indirect_mbox()
535 	pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);  in tg3_write_indirect_mbox()
536 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_indirect_mbox()
543 		pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,  in tg3_write_indirect_mbox()
544 				       tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);  in tg3_write_indirect_mbox()
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)  in tg3_read_indirect_mbox()  argument
553 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_indirect_mbox()
554 	pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);  in tg3_read_indirect_mbox()
555 	pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);  in tg3_read_indirect_mbox()
556 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_indirect_mbox()
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)  in _tw32_flush()  argument
567 	if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))  in _tw32_flush()
569 		tp->write32(tp, off, val);  in _tw32_flush()
572 		tg3_write32(tp, off, val);  in _tw32_flush()
575 		tp->read32(tp, off);  in _tw32_flush()
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)  in tw32_mailbox_flush()  argument
586 	tp->write32_mbox(tp, off, val);  in tw32_mailbox_flush()
587 	if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||  in tw32_mailbox_flush()
588 	    (!tg3_flag(tp, MBOX_WRITE_REORDER) &&  in tw32_mailbox_flush()
589 	     !tg3_flag(tp, ICH_WORKAROUND)))  in tw32_mailbox_flush()
590 		tp->read32_mbox(tp, off);  in tw32_mailbox_flush()
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)  in tg3_write32_tx_mbox()  argument
595 	void __iomem *mbox = tp->regs + off;  in tg3_write32_tx_mbox()
597 	if (tg3_flag(tp, TXD_MBOX_HWBUG))  in tg3_write32_tx_mbox()
599 	if (tg3_flag(tp, MBOX_WRITE_REORDER) ||  in tg3_write32_tx_mbox()
600 	    tg3_flag(tp, FLUSH_POSTED_WRITES))  in tg3_write32_tx_mbox()
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)  in tg3_read32_mbox_5906()  argument
606 	return readl(tp->regs + off + GRCMBOX_BASE);  in tg3_read32_mbox_5906()
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)  in tg3_write32_mbox_5906()  argument
611 	writel(val, tp->regs + off + GRCMBOX_BASE);  in tg3_write32_mbox_5906()
614 #define tw32_mailbox(reg, val)		tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val)	tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val)		tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val)		tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg)		tp->read32_mbox(tp, reg)
620 #define tw32(reg, val)			tp->write32(tp, reg, val)
621 #define tw32_f(reg, val)		_tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us)	_tw32_flush(tp, (reg), (val), (us))
623 #define tr32(reg)			tp->read32(tp, reg)
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)  in tg3_write_mem()  argument
629 	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&  in tg3_write_mem()
633 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_write_mem()
634 	if (tg3_flag(tp, SRAM_USE_CONFIG)) {  in tg3_write_mem()
635 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_write_mem()
636 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_write_mem()
639 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_write_mem()
647 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_write_mem()
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)  in tg3_read_mem()  argument
654 	if (tg3_asic_rev(tp) == ASIC_REV_5906 &&  in tg3_read_mem()
660 	spin_lock_irqsave(&tp->indirect_lock, flags);  in tg3_read_mem()
661 	if (tg3_flag(tp, SRAM_USE_CONFIG)) {  in tg3_read_mem()
662 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);  in tg3_read_mem()
663 		pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_read_mem()
666 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_read_mem()
674 	spin_unlock_irqrestore(&tp->indirect_lock, flags);  in tg3_read_mem()
677 static void tg3_ape_lock_init(struct tg3 *tp)  in tg3_ape_lock_init()  argument
682 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_lock_init()
697 			if (!tp->pci_fn)  in tg3_ape_lock_init()
700 				bit = 1 << tp->pci_fn;  in tg3_ape_lock_init()
702 		tg3_ape_write32(tp, regbase + 4 * i, bit);  in tg3_ape_lock_init()
707 static int tg3_ape_lock(struct tg3 *tp, int locknum)  in tg3_ape_lock()  argument
713 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_lock()
718 		if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_lock()
723 		if (!tp->pci_fn)  in tg3_ape_lock()
726 			bit = 1 << tp->pci_fn;  in tg3_ape_lock()
738 	if (tg3_asic_rev(tp) == ASIC_REV_5761) {  in tg3_ape_lock()
748 	tg3_ape_write32(tp, req + off, bit);  in tg3_ape_lock()
752 		status = tg3_ape_read32(tp, gnt + off);  in tg3_ape_lock()
755 		if (pci_channel_offline(tp->pdev))  in tg3_ape_lock()
763 		tg3_ape_write32(tp, gnt + off, bit);  in tg3_ape_lock()
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)  in tg3_ape_unlock()  argument
774 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_unlock()
779 		if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_unlock()
784 		if (!tp->pci_fn)  in tg3_ape_unlock()
787 			bit = 1 << tp->pci_fn;  in tg3_ape_unlock()
799 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_ape_unlock()
804 	tg3_ape_write32(tp, gnt + 4 * locknum, bit);  in tg3_ape_unlock()
807 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)  in tg3_ape_event_lock()  argument
812 		if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))  in tg3_ape_event_lock()
815 		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);  in tg3_ape_event_lock()
819 		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_event_lock()
829 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)  in tg3_ape_wait_for_event()  argument
834 		apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);  in tg3_ape_wait_for_event()
845 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,  in tg3_ape_scratchpad_read()  argument
851 	if (!tg3_flag(tp, APE_HAS_NCSI))  in tg3_ape_scratchpad_read()
854 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_ape_scratchpad_read()
858 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_scratchpad_read()
862 	bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +  in tg3_ape_scratchpad_read()
865 	maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);  in tg3_ape_scratchpad_read()
874 		apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_scratchpad_read()
879 		err = tg3_ape_event_lock(tp, 1000);  in tg3_ape_scratchpad_read()
886 		tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);  in tg3_ape_scratchpad_read()
888 		tg3_ape_write32(tp, bufoff, base_off);  in tg3_ape_scratchpad_read()
889 		tg3_ape_write32(tp, bufoff + sizeof(u32), length);  in tg3_ape_scratchpad_read()
891 		tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_scratchpad_read()
892 		tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);  in tg3_ape_scratchpad_read()
896 		if (tg3_ape_wait_for_event(tp, 30000))  in tg3_ape_scratchpad_read()
900 			u32 val = tg3_ape_read32(tp, msgoff + i);  in tg3_ape_scratchpad_read()
910 static int tg3_ape_send_event(struct tg3 *tp, u32 event)  in tg3_ape_send_event()  argument
915 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_ape_send_event()
919 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_ape_send_event()
924 	err = tg3_ape_event_lock(tp, 20000);  in tg3_ape_send_event()
928 	tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,  in tg3_ape_send_event()
931 	tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);  in tg3_ape_send_event()
932 	tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);  in tg3_ape_send_event()
937 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)  in tg3_ape_driver_state_change()  argument
942 	if (!tg3_flag(tp, ENABLE_APE))  in tg3_ape_driver_state_change()
947 		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);  in tg3_ape_driver_state_change()
948 		tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,  in tg3_ape_driver_state_change()
950 		tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,  in tg3_ape_driver_state_change()
952 		apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);  in tg3_ape_driver_state_change()
953 		tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);  in tg3_ape_driver_state_change()
954 		tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,  in tg3_ape_driver_state_change()
956 		tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,  in tg3_ape_driver_state_change()
958 		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,  in tg3_ape_driver_state_change()
964 		if (device_may_wakeup(&tp->pdev->dev) &&  in tg3_ape_driver_state_change()
965 		    tg3_flag(tp, WOL_ENABLE)) {  in tg3_ape_driver_state_change()
966 			tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,  in tg3_ape_driver_state_change()
972 		tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);  in tg3_ape_driver_state_change()
982 	tg3_ape_send_event(tp, event);  in tg3_ape_driver_state_change()
985 static void tg3_send_ape_heartbeat(struct tg3 *tp,  in tg3_send_ape_heartbeat()  argument
989 	if (!tg3_flag(tp, ENABLE_APE) ||  in tg3_send_ape_heartbeat()
990 	    time_before(jiffies, tp->ape_hb_jiffies + interval))  in tg3_send_ape_heartbeat()
993 	tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++);  in tg3_send_ape_heartbeat()
994 	tp->ape_hb_jiffies = jiffies;  in tg3_send_ape_heartbeat()
997 static void tg3_disable_ints(struct tg3 *tp)  in tg3_disable_ints()  argument
1002 	     (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));  in tg3_disable_ints()
1003 	for (i = 0; i < tp->irq_max; i++)  in tg3_disable_ints()
1004 		tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);  in tg3_disable_ints()
1007 static void tg3_enable_ints(struct tg3 *tp)  in tg3_enable_ints()  argument
1011 	tp->irq_sync = 0;  in tg3_enable_ints()
1015 	     (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));  in tg3_enable_ints()
1017 	tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;  in tg3_enable_ints()
1018 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_enable_ints()
1019 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_enable_ints()
1022 		if (tg3_flag(tp, 1SHOT_MSI))  in tg3_enable_ints()
1025 		tp->coal_now |= tnapi->coal_now;  in tg3_enable_ints()
1029 	if (!tg3_flag(tp, TAGGED_STATUS) &&  in tg3_enable_ints()
1030 	    (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))  in tg3_enable_ints()
1031 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);  in tg3_enable_ints()
1033 		tw32(HOSTCC_MODE, tp->coal_now);  in tg3_enable_ints()
1035 	tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);  in tg3_enable_ints()
1040 	struct tg3 *tp = tnapi->tp;  in tg3_has_work()  local
1045 	if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {  in tg3_has_work()
1069 	struct tg3 *tp = tnapi->tp;  in tg3_int_reenable()  local
1077 	if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))  in tg3_int_reenable()
1078 		tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_int_reenable()
1082 static void tg3_switch_clocks(struct tg3 *tp)  in tg3_switch_clocks()  argument
1087 	if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))  in tg3_switch_clocks()
1096 	tp->pci_clock_ctrl = clock_ctrl;  in tg3_switch_clocks()
1098 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_switch_clocks()
1117 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,  in __tg3_readphy()  argument
1124 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_readphy()
1126 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in __tg3_readphy()
1130 	tg3_ape_lock(tp, tp->phy_ape_lock);  in __tg3_readphy()
1161 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_readphy()
1162 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in __tg3_readphy()
1166 	tg3_ape_unlock(tp, tp->phy_ape_lock);  in __tg3_readphy()
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)  in tg3_readphy()  argument
1173 	return __tg3_readphy(tp, tp->phy_addr, reg, val);  in tg3_readphy()
1176 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,  in __tg3_writephy()  argument
1183 	if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in __tg3_writephy()
1187 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_writephy()
1189 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in __tg3_writephy()
1193 	tg3_ape_lock(tp, tp->phy_ape_lock);  in __tg3_writephy()
1220 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in __tg3_writephy()
1221 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in __tg3_writephy()
1225 	tg3_ape_unlock(tp, tp->phy_ape_lock);  in __tg3_writephy()
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)  in tg3_writephy()  argument
1232 	return __tg3_writephy(tp, tp->phy_addr, reg, val);  in tg3_writephy()
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)  in tg3_phy_cl45_write()  argument
1239 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);  in tg3_phy_cl45_write()
1243 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);  in tg3_phy_cl45_write()
1247 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,  in tg3_phy_cl45_write()
1252 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);  in tg3_phy_cl45_write()
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)  in tg3_phy_cl45_read()  argument
1262 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);  in tg3_phy_cl45_read()
1266 	err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);  in tg3_phy_cl45_read()
1270 	err = tg3_writephy(tp, MII_TG3_MMD_CTRL,  in tg3_phy_cl45_read()
1275 	err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);  in tg3_phy_cl45_read()
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)  in tg3_phydsp_read()  argument
1285 	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);  in tg3_phydsp_read()
1287 		err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);  in tg3_phydsp_read()
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)  in tg3_phydsp_write()  argument
1296 	err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);  in tg3_phydsp_write()
1298 		err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);  in tg3_phydsp_write()
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)  in tg3_phy_auxctl_read()  argument
1307 	err = tg3_writephy(tp, MII_TG3_AUX_CTRL,  in tg3_phy_auxctl_read()
1311 		err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);  in tg3_phy_auxctl_read()
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)  in tg3_phy_auxctl_write()  argument
1321 	return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);  in tg3_phy_auxctl_write()
1324 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)  in tg3_phy_toggle_auxctl_smdsp()  argument
1329 	err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);  in tg3_phy_toggle_auxctl_smdsp()
1339 	err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,  in tg3_phy_toggle_auxctl_smdsp()
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)  in tg3_phy_shdw_write()  argument
1347 	return tg3_writephy(tp, MII_TG3_MISC_SHDW,  in tg3_phy_shdw_write()
1351 static int tg3_bmcr_reset(struct tg3 *tp)  in tg3_bmcr_reset()  argument
1360 	err = tg3_writephy(tp, MII_BMCR, phy_control);  in tg3_bmcr_reset()
1366 		err = tg3_readphy(tp, MII_BMCR, &phy_control);  in tg3_bmcr_reset()
1384 	struct tg3 *tp = bp->priv;  in tg3_mdio_read()  local
1387 	spin_lock_bh(&tp->lock);  in tg3_mdio_read()
1389 	if (__tg3_readphy(tp, mii_id, reg, &val))  in tg3_mdio_read()
1392 	spin_unlock_bh(&tp->lock);  in tg3_mdio_read()
1399 	struct tg3 *tp = bp->priv;  in tg3_mdio_write()  local
1402 	spin_lock_bh(&tp->lock);  in tg3_mdio_write()
1404 	if (__tg3_writephy(tp, mii_id, reg, val))  in tg3_mdio_write()
1407 	spin_unlock_bh(&tp->lock);  in tg3_mdio_write()
1412 static void tg3_mdio_config_5785(struct tg3 *tp)  in tg3_mdio_config_5785()  argument
1417 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_mdio_config_5785()
1448 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE))  in tg3_mdio_config_5785()
1461 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {  in tg3_mdio_config_5785()
1462 		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))  in tg3_mdio_config_5785()
1464 		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))  in tg3_mdio_config_5785()
1479 	if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {  in tg3_mdio_config_5785()
1480 		if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))  in tg3_mdio_config_5785()
1485 		if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))  in tg3_mdio_config_5785()
1493 static void tg3_mdio_start(struct tg3 *tp)  in tg3_mdio_start()  argument
1495 	tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;  in tg3_mdio_start()
1496 	tw32_f(MAC_MI_MODE, tp->mi_mode);  in tg3_mdio_start()
1499 	if (tg3_flag(tp, MDIOBUS_INITED) &&  in tg3_mdio_start()
1500 	    tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_mdio_start()
1501 		tg3_mdio_config_5785(tp);  in tg3_mdio_start()
1504 static int tg3_mdio_init(struct tg3 *tp)  in tg3_mdio_init()  argument
1510 	if (tg3_flag(tp, 5717_PLUS)) {  in tg3_mdio_init()
1513 		tp->phy_addr = tp->pci_fn + 1;  in tg3_mdio_init()
1515 		if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)  in tg3_mdio_init()
1521 			tp->phy_addr += 7;  in tg3_mdio_init()
1522 	} else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {  in tg3_mdio_init()
1525 		addr = ssb_gige_get_phyaddr(tp->pdev);  in tg3_mdio_init()
1528 		tp->phy_addr = addr;  in tg3_mdio_init()
1530 		tp->phy_addr = TG3_PHY_MII_ADDR;  in tg3_mdio_init()
1532 	tg3_mdio_start(tp);  in tg3_mdio_init()
1534 	if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))  in tg3_mdio_init()
1537 	tp->mdio_bus = mdiobus_alloc();  in tg3_mdio_init()
1538 	if (tp->mdio_bus == NULL)  in tg3_mdio_init()
1541 	tp->mdio_bus->name     = "tg3 mdio bus";  in tg3_mdio_init()
1542 	snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev));  in tg3_mdio_init()
1543 	tp->mdio_bus->priv     = tp;  in tg3_mdio_init()
1544 	tp->mdio_bus->parent   = &tp->pdev->dev;  in tg3_mdio_init()
1545 	tp->mdio_bus->read     = &tg3_mdio_read;  in tg3_mdio_init()
1546 	tp->mdio_bus->write    = &tg3_mdio_write;  in tg3_mdio_init()
1547 	tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);  in tg3_mdio_init()
1554 	if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))  in tg3_mdio_init()
1555 		tg3_bmcr_reset(tp);  in tg3_mdio_init()
1557 	i = mdiobus_register(tp->mdio_bus);  in tg3_mdio_init()
1559 		dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);  in tg3_mdio_init()
1560 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_init()
1564 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_mdio_init()
1567 		dev_warn(&tp->pdev->dev, "No PHY devices\n");  in tg3_mdio_init()
1568 		mdiobus_unregister(tp->mdio_bus);  in tg3_mdio_init()
1569 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_init()
1592 		tp->phy_flags |= TG3_PHYFLG_IS_FET;  in tg3_mdio_init()
1596 	tg3_flag_set(tp, MDIOBUS_INITED);  in tg3_mdio_init()
1598 	if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_mdio_init()
1599 		tg3_mdio_config_5785(tp);  in tg3_mdio_init()
1604 static void tg3_mdio_fini(struct tg3 *tp)  in tg3_mdio_fini()  argument
1606 	if (tg3_flag(tp, MDIOBUS_INITED)) {  in tg3_mdio_fini()
1607 		tg3_flag_clear(tp, MDIOBUS_INITED);  in tg3_mdio_fini()
1608 		mdiobus_unregister(tp->mdio_bus);  in tg3_mdio_fini()
1609 		mdiobus_free(tp->mdio_bus);  in tg3_mdio_fini()
1614 static inline void tg3_generate_fw_event(struct tg3 *tp)  in tg3_generate_fw_event()  argument
1622 	tp->last_event_jiffies = jiffies;  in tg3_generate_fw_event()
1628 static void tg3_wait_for_event_ack(struct tg3 *tp)  in tg3_wait_for_event_ack()  argument
1635 	time_remain = (long)(tp->last_event_jiffies + 1 +  in tg3_wait_for_event_ack()
1650 		if (pci_channel_offline(tp->pdev))  in tg3_wait_for_event_ack()
1658 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)  in tg3_phy_gather_ump_data()  argument
1663 	if (!tg3_readphy(tp, MII_BMCR, &reg))  in tg3_phy_gather_ump_data()
1665 	if (!tg3_readphy(tp, MII_BMSR, &reg))  in tg3_phy_gather_ump_data()
1670 	if (!tg3_readphy(tp, MII_ADVERTISE, &reg))  in tg3_phy_gather_ump_data()
1672 	if (!tg3_readphy(tp, MII_LPA, &reg))  in tg3_phy_gather_ump_data()
1677 	if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {  in tg3_phy_gather_ump_data()
1678 		if (!tg3_readphy(tp, MII_CTRL1000, &reg))  in tg3_phy_gather_ump_data()
1680 		if (!tg3_readphy(tp, MII_STAT1000, &reg))  in tg3_phy_gather_ump_data()
1685 	if (!tg3_readphy(tp, MII_PHYADDR, &reg))  in tg3_phy_gather_ump_data()
1693 static void tg3_ump_link_report(struct tg3 *tp)  in tg3_ump_link_report()  argument
1697 	if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))  in tg3_ump_link_report()
1700 	tg3_phy_gather_ump_data(tp, data);  in tg3_ump_link_report()
1702 	tg3_wait_for_event_ack(tp);  in tg3_ump_link_report()
1704 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);  in tg3_ump_link_report()
1705 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);  in tg3_ump_link_report()
1706 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);  in tg3_ump_link_report()
1707 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);  in tg3_ump_link_report()
1708 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);  in tg3_ump_link_report()
1709 	tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);  in tg3_ump_link_report()
1711 	tg3_generate_fw_event(tp);  in tg3_ump_link_report()
1715 static void tg3_stop_fw(struct tg3 *tp)  in tg3_stop_fw()  argument
1717 	if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {  in tg3_stop_fw()
1719 		tg3_wait_for_event_ack(tp);  in tg3_stop_fw()
1721 		tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);  in tg3_stop_fw()
1723 		tg3_generate_fw_event(tp);  in tg3_stop_fw()
1726 		tg3_wait_for_event_ack(tp);  in tg3_stop_fw()
1731 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)  in tg3_write_sig_pre_reset()  argument
1733 	tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,  in tg3_write_sig_pre_reset()
1736 	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {  in tg3_write_sig_pre_reset()
1739 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1744 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1749 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_pre_reset()
1760 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)  in tg3_write_sig_post_reset()  argument
1762 	if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {  in tg3_write_sig_post_reset()
1765 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_post_reset()
1770 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_post_reset()
1781 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)  in tg3_write_sig_legacy()  argument
1783 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_write_sig_legacy()
1786 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1791 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1796 			tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,  in tg3_write_sig_legacy()
1806 static int tg3_poll_fw(struct tg3 *tp)  in tg3_poll_fw()  argument
1811 	if (tg3_flag(tp, NO_FWARE_REPORTED))  in tg3_poll_fw()
1814 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_poll_fw()
1819 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_poll_fw()
1824 			if (pci_channel_offline(tp->pdev))  in tg3_poll_fw()
1834 		tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);  in tg3_poll_fw()
1837 		if (pci_channel_offline(tp->pdev)) {  in tg3_poll_fw()
1838 			if (!tg3_flag(tp, NO_FWARE_REPORTED)) {  in tg3_poll_fw()
1839 				tg3_flag_set(tp, NO_FWARE_REPORTED);  in tg3_poll_fw()
1840 				netdev_info(tp->dev, "No firmware running\n");  in tg3_poll_fw()
1854 	if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {  in tg3_poll_fw()
1855 		tg3_flag_set(tp, NO_FWARE_REPORTED);  in tg3_poll_fw()
1857 		netdev_info(tp->dev, "No firmware running\n");  in tg3_poll_fw()
1860 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {  in tg3_poll_fw()
1870 static void tg3_link_report(struct tg3 *tp)  in tg3_link_report()  argument
1872 	if (!netif_carrier_ok(tp->dev)) {  in tg3_link_report()
1873 		netif_info(tp, link, tp->dev, "Link is down\n");  in tg3_link_report()
1874 		tg3_ump_link_report(tp);  in tg3_link_report()
1875 	} else if (netif_msg_link(tp)) {  in tg3_link_report()
1876 		netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",  in tg3_link_report()
1877 			    (tp->link_config.active_speed == SPEED_1000 ?  in tg3_link_report()
1879 			     (tp->link_config.active_speed == SPEED_100 ?  in tg3_link_report()
1881 			    (tp->link_config.active_duplex == DUPLEX_FULL ?  in tg3_link_report()
1884 		netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",  in tg3_link_report()
1885 			    (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?  in tg3_link_report()
1887 			    (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?  in tg3_link_report()
1890 		if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)  in tg3_link_report()
1891 			netdev_info(tp->dev, "EEE is %s\n",  in tg3_link_report()
1892 				    tp->setlpicnt ? "enabled" : "disabled");  in tg3_link_report()
1894 		tg3_ump_link_report(tp);  in tg3_link_report()
1897 	tp->link_up = netif_carrier_ok(tp->dev);  in tg3_link_report()
1960 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)  in tg3_setup_flow_control()  argument
1964 	u32 old_rx_mode = tp->rx_mode;  in tg3_setup_flow_control()
1965 	u32 old_tx_mode = tp->tx_mode;  in tg3_setup_flow_control()
1967 	if (tg3_flag(tp, USE_PHYLIB))  in tg3_setup_flow_control()
1968 		autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg;  in tg3_setup_flow_control()
1970 		autoneg = tp->link_config.autoneg;  in tg3_setup_flow_control()
1972 	if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {  in tg3_setup_flow_control()
1973 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_setup_flow_control()
1978 		flowctrl = tp->link_config.flowctrl;  in tg3_setup_flow_control()
1980 	tp->link_config.active_flowctrl = flowctrl;  in tg3_setup_flow_control()
1983 		tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
1985 		tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
1987 	if (old_rx_mode != tp->rx_mode)  in tg3_setup_flow_control()
1988 		tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_setup_flow_control()
1991 		tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
1993 		tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;  in tg3_setup_flow_control()
1995 	if (old_tx_mode != tp->tx_mode)  in tg3_setup_flow_control()
1996 		tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_setup_flow_control()
2003 	struct tg3 *tp = netdev_priv(dev);  in tg3_adjust_link()  local
2004 	struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_adjust_link()
2006 	spin_lock_bh(&tp->lock);  in tg3_adjust_link()
2008 	mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |  in tg3_adjust_link()
2011 	oldflowctrl = tp->link_config.active_flowctrl;  in tg3_adjust_link()
2020 			 tg3_asic_rev(tp) != ASIC_REV_5785)  in tg3_adjust_link()
2029 				  tp->link_config.flowctrl);  in tg3_adjust_link()
2037 		tg3_setup_flow_control(tp, lcl_adv, rmt_adv);  in tg3_adjust_link()
2041 	if (mac_mode != tp->mac_mode) {  in tg3_adjust_link()
2042 		tp->mac_mode = mac_mode;  in tg3_adjust_link()
2043 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_adjust_link()
2047 	if (tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_adjust_link()
2067 	if (phydev->link != tp->old_link ||  in tg3_adjust_link()
2068 	    phydev->speed != tp->link_config.active_speed ||  in tg3_adjust_link()
2069 	    phydev->duplex != tp->link_config.active_duplex ||  in tg3_adjust_link()
2070 	    oldflowctrl != tp->link_config.active_flowctrl)  in tg3_adjust_link()
2073 	tp->old_link = phydev->link;  in tg3_adjust_link()
2074 	tp->link_config.active_speed = phydev->speed;  in tg3_adjust_link()
2075 	tp->link_config.active_duplex = phydev->duplex;  in tg3_adjust_link()
2077 	spin_unlock_bh(&tp->lock);  in tg3_adjust_link()
2080 		tg3_link_report(tp);  in tg3_adjust_link()
2083 static int tg3_phy_init(struct tg3 *tp)  in tg3_phy_init()  argument
2087 	if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)  in tg3_phy_init()
2091 	tg3_bmcr_reset(tp);  in tg3_phy_init()
2093 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_phy_init()
2096 	phydev = phy_connect(tp->dev, phydev_name(phydev),  in tg3_phy_init()
2099 		dev_err(&tp->pdev->dev, "Could not attach to PHY\n");  in tg3_phy_init()
2107 		if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_init()
2118 		phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_init()
2122 	tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;  in tg3_phy_init()
2129 static void tg3_phy_start(struct tg3 *tp)  in tg3_phy_start()  argument
2133 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_phy_start()
2136 	phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_phy_start()
2138 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {  in tg3_phy_start()
2139 		tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;  in tg3_phy_start()
2140 		phydev->speed = tp->link_config.speed;  in tg3_phy_start()
2141 		phydev->duplex = tp->link_config.duplex;  in tg3_phy_start()
2142 		phydev->autoneg = tp->link_config.autoneg;  in tg3_phy_start()
2144 			phydev->advertising, tp->link_config.advertising);  in tg3_phy_start()
2152 static void tg3_phy_stop(struct tg3 *tp)  in tg3_phy_stop()  argument
2154 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_phy_stop()
2157 	phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_stop()
2160 static void tg3_phy_fini(struct tg3 *tp)  in tg3_phy_fini()  argument
2162 	if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {  in tg3_phy_fini()
2163 		phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_phy_fini()
2164 		tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;  in tg3_phy_fini()
2168 static int tg3_phy_set_extloopbk(struct tg3 *tp)  in tg3_phy_set_extloopbk()  argument
2173 	if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_phy_set_extloopbk()
2176 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_set_extloopbk()
2178 		err = tg3_phy_auxctl_write(tp,  in tg3_phy_set_extloopbk()
2185 	err = tg3_phy_auxctl_read(tp,  in tg3_phy_set_extloopbk()
2191 	err = tg3_phy_auxctl_write(tp,  in tg3_phy_set_extloopbk()
2198 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)  in tg3_phy_fet_toggle_apd()  argument
2202 	if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {  in tg3_phy_fet_toggle_apd()
2205 		tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_phy_fet_toggle_apd()
2207 		if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {  in tg3_phy_fet_toggle_apd()
2212 			tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);  in tg3_phy_fet_toggle_apd()
2214 		tg3_writephy(tp, MII_TG3_FET_TEST, phytest);  in tg3_phy_fet_toggle_apd()
2218 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)  in tg3_phy_toggle_apd()  argument
2222 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_phy_toggle_apd()
2223 	    (tg3_flag(tp, 5717_PLUS) &&  in tg3_phy_toggle_apd()
2224 	     (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))  in tg3_phy_toggle_apd()
2227 	if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_toggle_apd()
2228 		tg3_phy_fet_toggle_apd(tp, enable);  in tg3_phy_toggle_apd()
2236 	if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)  in tg3_phy_toggle_apd()
2239 	tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);  in tg3_phy_toggle_apd()
2246 	tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);  in tg3_phy_toggle_apd()
2249 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)  in tg3_phy_toggle_automdix()  argument
2253 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_phy_toggle_automdix()
2254 	    (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_phy_toggle_automdix()
2257 	if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_toggle_automdix()
2260 		if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {  in tg3_phy_toggle_automdix()
2263 			tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_phy_toggle_automdix()
2265 			if (!tg3_readphy(tp, reg, &phy)) {  in tg3_phy_toggle_automdix()
2270 				tg3_writephy(tp, reg, phy);  in tg3_phy_toggle_automdix()
2272 			tg3_writephy(tp, MII_TG3_FET_TEST, ephy);  in tg3_phy_toggle_automdix()
2277 		ret = tg3_phy_auxctl_read(tp,  in tg3_phy_toggle_automdix()
2284 			tg3_phy_auxctl_write(tp,  in tg3_phy_toggle_automdix()
2290 static void tg3_phy_set_wirespeed(struct tg3 *tp)  in tg3_phy_set_wirespeed()  argument
2295 	if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)  in tg3_phy_set_wirespeed()
2298 	ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);  in tg3_phy_set_wirespeed()
2300 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,  in tg3_phy_set_wirespeed()
2304 static void tg3_phy_apply_otp(struct tg3 *tp)  in tg3_phy_apply_otp()  argument
2308 	if (!tp->phy_otp)  in tg3_phy_apply_otp()
2311 	otp = tp->phy_otp;  in tg3_phy_apply_otp()
2313 	if (tg3_phy_toggle_auxctl_smdsp(tp, true))  in tg3_phy_apply_otp()
2318 	tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);  in tg3_phy_apply_otp()
2322 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);  in tg3_phy_apply_otp()
2326 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);  in tg3_phy_apply_otp()
2329 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);  in tg3_phy_apply_otp()
2332 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);  in tg3_phy_apply_otp()
2336 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);  in tg3_phy_apply_otp()
2338 	tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_apply_otp()
2341 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)  in tg3_eee_pull_config()  argument
2344 	struct ethtool_eee *dest = &tp->eee;  in tg3_eee_pull_config()
2346 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_eee_pull_config()
2352 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))  in tg3_eee_pull_config()
2363 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))  in tg3_eee_pull_config()
2368 	if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))  in tg3_eee_pull_config()
2381 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)  in tg3_phy_eee_adjust()  argument
2385 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_eee_adjust()
2388 	tp->setlpicnt = 0;  in tg3_phy_eee_adjust()
2390 	if (tp->link_config.autoneg == AUTONEG_ENABLE &&  in tg3_phy_eee_adjust()
2392 	    tp->link_config.active_duplex == DUPLEX_FULL &&  in tg3_phy_eee_adjust()
2393 	    (tp->link_config.active_speed == SPEED_100 ||  in tg3_phy_eee_adjust()
2394 	     tp->link_config.active_speed == SPEED_1000)) {  in tg3_phy_eee_adjust()
2397 		if (tp->link_config.active_speed == SPEED_1000)  in tg3_phy_eee_adjust()
2404 		tg3_eee_pull_config(tp, NULL);  in tg3_phy_eee_adjust()
2405 		if (tp->eee.eee_active)  in tg3_phy_eee_adjust()
2406 			tp->setlpicnt = 2;  in tg3_phy_eee_adjust()
2409 	if (!tp->setlpicnt) {  in tg3_phy_eee_adjust()
2411 		   !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_eee_adjust()
2412 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);  in tg3_phy_eee_adjust()
2413 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_eee_adjust()
2421 static void tg3_phy_eee_enable(struct tg3 *tp)  in tg3_phy_eee_enable()  argument
2425 	if (tp->link_config.active_speed == SPEED_1000 &&  in tg3_phy_eee_enable()
2426 	    (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_phy_eee_enable()
2427 	     tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_phy_eee_enable()
2428 	     tg3_flag(tp, 57765_CLASS)) &&  in tg3_phy_eee_enable()
2429 	    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_eee_enable()
2432 		tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_eee_enable()
2433 		tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_eee_enable()
2440 static int tg3_wait_macro_done(struct tg3 *tp)  in tg3_wait_macro_done()  argument
2447 		if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {  in tg3_wait_macro_done()
2458 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)  in tg3_phy_write_and_check_testpat()  argument
2471 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_write_and_check_testpat()
2473 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);  in tg3_phy_write_and_check_testpat()
2476 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT,  in tg3_phy_write_and_check_testpat()
2479 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);  in tg3_phy_write_and_check_testpat()
2480 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2485 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_write_and_check_testpat()
2487 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);  in tg3_phy_write_and_check_testpat()
2488 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2493 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);  in tg3_phy_write_and_check_testpat()
2494 		if (tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2502 			if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||  in tg3_phy_write_and_check_testpat()
2503 			    tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||  in tg3_phy_write_and_check_testpat()
2504 			    tg3_wait_macro_done(tp)) {  in tg3_phy_write_and_check_testpat()
2512 				tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);  in tg3_phy_write_and_check_testpat()
2513 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);  in tg3_phy_write_and_check_testpat()
2514 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);  in tg3_phy_write_and_check_testpat()
2524 static int tg3_phy_reset_chanpat(struct tg3 *tp)  in tg3_phy_reset_chanpat()  argument
2531 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_phy_reset_chanpat()
2533 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);  in tg3_phy_reset_chanpat()
2535 			tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);  in tg3_phy_reset_chanpat()
2536 		tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);  in tg3_phy_reset_chanpat()
2537 		if (tg3_wait_macro_done(tp))  in tg3_phy_reset_chanpat()
2544 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)  in tg3_phy_reset_5703_4_5()  argument
2553 			err = tg3_bmcr_reset(tp);  in tg3_phy_reset_5703_4_5()
2560 		if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))  in tg3_phy_reset_5703_4_5()
2564 		tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);  in tg3_phy_reset_5703_4_5()
2567 		tg3_writephy(tp, MII_BMCR,  in tg3_phy_reset_5703_4_5()
2571 		if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))  in tg3_phy_reset_5703_4_5()
2574 		tg3_writephy(tp, MII_CTRL1000,  in tg3_phy_reset_5703_4_5()
2577 		err = tg3_phy_toggle_auxctl_smdsp(tp, true);  in tg3_phy_reset_5703_4_5()
2582 		tg3_phydsp_write(tp, 0x8005, 0x0800);  in tg3_phy_reset_5703_4_5()
2584 		err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);  in tg3_phy_reset_5703_4_5()
2589 	err = tg3_phy_reset_chanpat(tp);  in tg3_phy_reset_5703_4_5()
2593 	tg3_phydsp_write(tp, 0x8005, 0x0000);  in tg3_phy_reset_5703_4_5()
2595 	tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);  in tg3_phy_reset_5703_4_5()
2596 	tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);  in tg3_phy_reset_5703_4_5()
2598 	tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset_5703_4_5()
2600 	tg3_writephy(tp, MII_CTRL1000, phy9_orig);  in tg3_phy_reset_5703_4_5()
2602 	err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);  in tg3_phy_reset_5703_4_5()
2607 	tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);  in tg3_phy_reset_5703_4_5()
2612 static void tg3_carrier_off(struct tg3 *tp)  in tg3_carrier_off()  argument
2614 	netif_carrier_off(tp->dev);  in tg3_carrier_off()
2615 	tp->link_up = false;  in tg3_carrier_off()
2618 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)  in tg3_warn_mgmt_link_flap()  argument
2620 	if (tg3_flag(tp, ENABLE_ASF))  in tg3_warn_mgmt_link_flap()
2621 		netdev_warn(tp->dev,  in tg3_warn_mgmt_link_flap()
2628 static int tg3_phy_reset(struct tg3 *tp)  in tg3_phy_reset()  argument
2633 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_phy_reset()
2638 	err  = tg3_readphy(tp, MII_BMSR, &val);  in tg3_phy_reset()
2639 	err |= tg3_readphy(tp, MII_BMSR, &val);  in tg3_phy_reset()
2643 	if (netif_running(tp->dev) && tp->link_up) {  in tg3_phy_reset()
2644 		netif_carrier_off(tp->dev);  in tg3_phy_reset()
2645 		tg3_link_report(tp);  in tg3_phy_reset()
2648 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_phy_reset()
2649 	    tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_phy_reset()
2650 	    tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_phy_reset()
2651 		err = tg3_phy_reset_5703_4_5(tp);  in tg3_phy_reset()
2658 	if (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_phy_reset()
2659 	    tg3_chip_rev(tp) != CHIPREV_5784_AX) {  in tg3_phy_reset()
2666 	err = tg3_bmcr_reset(tp);  in tg3_phy_reset()
2672 		tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);  in tg3_phy_reset()
2677 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||  in tg3_phy_reset()
2678 	    tg3_chip_rev(tp) == CHIPREV_5761_AX) {  in tg3_phy_reset()
2688 	if (tg3_flag(tp, 5717_PLUS) &&  in tg3_phy_reset()
2689 	    (tp->phy_flags & TG3_PHYFLG_MII_SERDES))  in tg3_phy_reset()
2692 	tg3_phy_apply_otp(tp);  in tg3_phy_reset()
2694 	if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)  in tg3_phy_reset()
2695 		tg3_phy_toggle_apd(tp, true);  in tg3_phy_reset()
2697 		tg3_phy_toggle_apd(tp, false);  in tg3_phy_reset()
2700 	if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&  in tg3_phy_reset()
2701 	    !tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2702 		tg3_phydsp_write(tp, 0x201f, 0x2aaa);  in tg3_phy_reset()
2703 		tg3_phydsp_write(tp, 0x000a, 0x0323);  in tg3_phy_reset()
2704 		tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2707 	if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {  in tg3_phy_reset()
2708 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_phy_reset()
2709 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_phy_reset()
2712 	if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {  in tg3_phy_reset()
2713 		if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2714 			tg3_phydsp_write(tp, 0x000a, 0x310b);  in tg3_phy_reset()
2715 			tg3_phydsp_write(tp, 0x201f, 0x9506);  in tg3_phy_reset()
2716 			tg3_phydsp_write(tp, 0x401f, 0x14e2);  in tg3_phy_reset()
2717 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2719 	} else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {  in tg3_phy_reset()
2720 		if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {  in tg3_phy_reset()
2721 			tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);  in tg3_phy_reset()
2722 			if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {  in tg3_phy_reset()
2723 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);  in tg3_phy_reset()
2724 				tg3_writephy(tp, MII_TG3_TEST1,  in tg3_phy_reset()
2727 				tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);  in tg3_phy_reset()
2729 			tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_reset()
2735 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_reset()
2737 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);  in tg3_phy_reset()
2738 	} else if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_phy_reset()
2740 		err = tg3_phy_auxctl_read(tp,  in tg3_phy_reset()
2743 			tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,  in tg3_phy_reset()
2750 	if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_phy_reset()
2751 		if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))  in tg3_phy_reset()
2752 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_phy_reset()
2756 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_phy_reset()
2758 		tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);  in tg3_phy_reset()
2761 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)  in tg3_phy_reset()
2762 		tg3_phydsp_write(tp, 0xffb, 0x4000);  in tg3_phy_reset()
2764 	tg3_phy_toggle_automdix(tp, true);  in tg3_phy_reset()
2765 	tg3_phy_set_wirespeed(tp);  in tg3_phy_reset()
2785 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)  in tg3_set_function_status()  argument
2789 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_function_status()
2790 	    tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_set_function_status()
2791 		status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);  in tg3_set_function_status()
2795 	shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;  in tg3_set_function_status()
2799 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_function_status()
2800 	    tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_set_function_status()
2801 		tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);  in tg3_set_function_status()
2808 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)  in tg3_pwrsrc_switch_to_vmain()  argument
2810 	if (!tg3_flag(tp, IS_NIC))  in tg3_pwrsrc_switch_to_vmain()
2813 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_pwrsrc_switch_to_vmain()
2814 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_pwrsrc_switch_to_vmain()
2815 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_pwrsrc_switch_to_vmain()
2816 		if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))  in tg3_pwrsrc_switch_to_vmain()
2819 		tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);  in tg3_pwrsrc_switch_to_vmain()
2821 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,  in tg3_pwrsrc_switch_to_vmain()
2824 		tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);  in tg3_pwrsrc_switch_to_vmain()
2826 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,  in tg3_pwrsrc_switch_to_vmain()
2833 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)  in tg3_pwrsrc_die_with_vmain()  argument
2837 	if (!tg3_flag(tp, IS_NIC) ||  in tg3_pwrsrc_die_with_vmain()
2838 	    tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_pwrsrc_die_with_vmain()
2839 	    tg3_asic_rev(tp) == ASIC_REV_5701)  in tg3_pwrsrc_die_with_vmain()
2842 	grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;  in tg3_pwrsrc_die_with_vmain()
2857 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)  in tg3_pwrsrc_switch_to_vaux()  argument
2859 	if (!tg3_flag(tp, IS_NIC))  in tg3_pwrsrc_switch_to_vaux()
2862 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_pwrsrc_switch_to_vaux()
2863 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_pwrsrc_switch_to_vaux()
2864 		tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |  in tg3_pwrsrc_switch_to_vaux()
2871 	} else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_pwrsrc_switch_to_vaux()
2872 		   tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {  in tg3_pwrsrc_switch_to_vaux()
2879 				     tp->grc_local_ctrl;  in tg3_pwrsrc_switch_to_vaux()
2895 		if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_pwrsrc_switch_to_vaux()
2897 			tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |  in tg3_pwrsrc_switch_to_vaux()
2903 		no_gpio2 = tp->nic_sram_data_cfg &  in tg3_pwrsrc_switch_to_vaux()
2916 			    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2922 			    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2928 				    tp->grc_local_ctrl | grc_local_ctrl,  in tg3_pwrsrc_switch_to_vaux()
2934 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)  in tg3_frob_aux_power_5717()  argument
2939 	if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))  in tg3_frob_aux_power_5717()
2942 	if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)  in tg3_frob_aux_power_5717()
2945 	msg = tg3_set_function_status(tp, msg);  in tg3_frob_aux_power_5717()
2951 		tg3_pwrsrc_switch_to_vaux(tp);  in tg3_frob_aux_power_5717()
2953 		tg3_pwrsrc_die_with_vmain(tp);  in tg3_frob_aux_power_5717()
2956 	tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);  in tg3_frob_aux_power_5717()
2959 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)  in tg3_frob_aux_power()  argument
2964 	if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))  in tg3_frob_aux_power()
2967 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_frob_aux_power()
2968 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_frob_aux_power()
2969 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_frob_aux_power()
2970 		tg3_frob_aux_power_5717(tp, include_wol ?  in tg3_frob_aux_power()
2971 					tg3_flag(tp, WOL_ENABLE) != 0 : 0);  in tg3_frob_aux_power()
2975 	if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {  in tg3_frob_aux_power()
2978 		dev_peer = pci_get_drvdata(tp->pdev_peer);  in tg3_frob_aux_power()
2993 	if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||  in tg3_frob_aux_power()
2994 	    tg3_flag(tp, ENABLE_ASF))  in tg3_frob_aux_power()
2998 		tg3_pwrsrc_switch_to_vaux(tp);  in tg3_frob_aux_power()
3000 		tg3_pwrsrc_die_with_vmain(tp);  in tg3_frob_aux_power()
3003 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)  in tg3_5700_link_polarity()  argument
3005 	if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)  in tg3_5700_link_polarity()
3007 	else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {  in tg3_5700_link_polarity()
3016 static bool tg3_phy_power_bug(struct tg3 *tp)  in tg3_phy_power_bug()  argument
3018 	switch (tg3_asic_rev(tp)) {  in tg3_phy_power_bug()
3023 		if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_phy_power_bug()
3027 		if (!tp->pci_fn)  in tg3_phy_power_bug()
3032 		if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_phy_power_bug()
3033 		    !tp->pci_fn)  in tg3_phy_power_bug()
3041 static bool tg3_phy_led_bug(struct tg3 *tp)  in tg3_phy_led_bug()  argument
3043 	switch (tg3_asic_rev(tp)) {  in tg3_phy_led_bug()
3046 		if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_phy_led_bug()
3047 		    !tp->pci_fn)  in tg3_phy_led_bug()
3055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)  in tg3_power_down_phy()  argument
3059 	if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)  in tg3_power_down_phy()
3062 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_power_down_phy()
3063 		if (tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_power_down_phy()
3075 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_phy()
3076 		tg3_bmcr_reset(tp);  in tg3_power_down_phy()
3081 	} else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_power_down_phy()
3083 		if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {  in tg3_power_down_phy()
3086 			tg3_writephy(tp, MII_ADVERTISE, 0);  in tg3_power_down_phy()
3087 			tg3_writephy(tp, MII_BMCR,  in tg3_power_down_phy()
3090 			tg3_writephy(tp, MII_TG3_FET_TEST,  in tg3_power_down_phy()
3092 			if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {  in tg3_power_down_phy()
3094 				tg3_writephy(tp,  in tg3_power_down_phy()
3098 			tg3_writephy(tp, MII_TG3_FET_TEST, phytest);  in tg3_power_down_phy()
3102 		if (!tg3_phy_led_bug(tp))  in tg3_power_down_phy()
3103 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_power_down_phy()
3109 		tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);  in tg3_power_down_phy()
3115 	if (tg3_phy_power_bug(tp))  in tg3_power_down_phy()
3118 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||  in tg3_power_down_phy()
3119 	    tg3_chip_rev(tp) == CHIPREV_5761_AX) {  in tg3_power_down_phy()
3126 	tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);  in tg3_power_down_phy()
3130 static int tg3_nvram_lock(struct tg3 *tp)  in tg3_nvram_lock()  argument
3132 	if (tg3_flag(tp, NVRAM)) {  in tg3_nvram_lock()
3135 		if (tp->nvram_lock_cnt == 0) {  in tg3_nvram_lock()
3147 		tp->nvram_lock_cnt++;  in tg3_nvram_lock()
3153 static void tg3_nvram_unlock(struct tg3 *tp)  in tg3_nvram_unlock()  argument
3155 	if (tg3_flag(tp, NVRAM)) {  in tg3_nvram_unlock()
3156 		if (tp->nvram_lock_cnt > 0)  in tg3_nvram_unlock()
3157 			tp->nvram_lock_cnt--;  in tg3_nvram_unlock()
3158 		if (tp->nvram_lock_cnt == 0)  in tg3_nvram_unlock()
3164 static void tg3_enable_nvram_access(struct tg3 *tp)  in tg3_enable_nvram_access()  argument
3166 	if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {  in tg3_enable_nvram_access()
3174 static void tg3_disable_nvram_access(struct tg3 *tp)  in tg3_disable_nvram_access()  argument
3176 	if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {  in tg3_disable_nvram_access()
3183 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,  in tg3_nvram_read_using_eeprom()  argument
3225 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)  in tg3_nvram_exec_cmd()  argument
3244 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)  in tg3_nvram_phys_addr()  argument
3246 	if (tg3_flag(tp, NVRAM) &&  in tg3_nvram_phys_addr()
3247 	    tg3_flag(tp, NVRAM_BUFFERED) &&  in tg3_nvram_phys_addr()
3248 	    tg3_flag(tp, FLASH) &&  in tg3_nvram_phys_addr()
3249 	    !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&  in tg3_nvram_phys_addr()
3250 	    (tp->nvram_jedecnum == JEDEC_ATMEL))  in tg3_nvram_phys_addr()
3252 		addr = ((addr / tp->nvram_pagesize) <<  in tg3_nvram_phys_addr()
3254 		       (addr % tp->nvram_pagesize);  in tg3_nvram_phys_addr()
3259 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)  in tg3_nvram_logical_addr()  argument
3261 	if (tg3_flag(tp, NVRAM) &&  in tg3_nvram_logical_addr()
3262 	    tg3_flag(tp, NVRAM_BUFFERED) &&  in tg3_nvram_logical_addr()
3263 	    tg3_flag(tp, FLASH) &&  in tg3_nvram_logical_addr()
3264 	    !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&  in tg3_nvram_logical_addr()
3265 	    (tp->nvram_jedecnum == JEDEC_ATMEL))  in tg3_nvram_logical_addr()
3268 			tp->nvram_pagesize) +  in tg3_nvram_logical_addr()
3280 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)  in tg3_nvram_read()  argument
3284 	if (!tg3_flag(tp, NVRAM))  in tg3_nvram_read()
3285 		return tg3_nvram_read_using_eeprom(tp, offset, val);  in tg3_nvram_read()
3287 	offset = tg3_nvram_phys_addr(tp, offset);  in tg3_nvram_read()
3292 	ret = tg3_nvram_lock(tp);  in tg3_nvram_read()
3296 	tg3_enable_nvram_access(tp);  in tg3_nvram_read()
3299 	ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |  in tg3_nvram_read()
3305 	tg3_disable_nvram_access(tp);  in tg3_nvram_read()
3307 	tg3_nvram_unlock(tp);  in tg3_nvram_read()
3313 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)  in tg3_nvram_read_be32()  argument
3316 	int res = tg3_nvram_read(tp, offset, &v);  in tg3_nvram_read_be32()
3322 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,  in tg3_nvram_write_block_using_eeprom()  argument
3372 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,  in tg3_nvram_write_block_unbuffered()  argument
3376 	u32 pagesize = tp->nvram_pagesize;  in tg3_nvram_write_block_unbuffered()
3392 			ret = tg3_nvram_read_be32(tp, phy_addr + j,  in tg3_nvram_write_block_unbuffered()
3411 		tg3_enable_nvram_access(tp);  in tg3_nvram_write_block_unbuffered()
3419 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3428 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3434 		if (tg3_nvram_exec_cmd(tp, nvram_cmd))  in tg3_nvram_write_block_unbuffered()
3454 			ret = tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_unbuffered()
3463 	tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_unbuffered()
3471 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,  in tg3_nvram_write_block_buffered()  argument
3483 		page_off = offset % tp->nvram_pagesize;  in tg3_nvram_write_block_buffered()
3485 		phy_addr = tg3_nvram_phys_addr(tp, offset);  in tg3_nvram_write_block_buffered()
3491 		if (page_off == (tp->nvram_pagesize - 4))  in tg3_nvram_write_block_buffered()
3498 		    !tg3_flag(tp, FLASH) ||  in tg3_nvram_write_block_buffered()
3499 		    !tg3_flag(tp, 57765_PLUS))  in tg3_nvram_write_block_buffered()
3502 		if (tg3_asic_rev(tp) != ASIC_REV_5752 &&  in tg3_nvram_write_block_buffered()
3503 		    !tg3_flag(tp, 5755_PLUS) &&  in tg3_nvram_write_block_buffered()
3504 		    (tp->nvram_jedecnum == JEDEC_ST) &&  in tg3_nvram_write_block_buffered()
3509 			ret = tg3_nvram_exec_cmd(tp, cmd);  in tg3_nvram_write_block_buffered()
3513 		if (!tg3_flag(tp, FLASH)) {  in tg3_nvram_write_block_buffered()
3518 		ret = tg3_nvram_exec_cmd(tp, nvram_cmd);  in tg3_nvram_write_block_buffered()
3526 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)  in tg3_nvram_write_block()  argument
3530 	if (tg3_flag(tp, EEPROM_WRITE_PROT)) {  in tg3_nvram_write_block()
3531 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &  in tg3_nvram_write_block()
3536 	if (!tg3_flag(tp, NVRAM)) {  in tg3_nvram_write_block()
3537 		ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);  in tg3_nvram_write_block()
3541 		ret = tg3_nvram_lock(tp);  in tg3_nvram_write_block()
3545 		tg3_enable_nvram_access(tp);  in tg3_nvram_write_block()
3546 		if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))  in tg3_nvram_write_block()
3552 		if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {  in tg3_nvram_write_block()
3553 			ret = tg3_nvram_write_block_buffered(tp, offset, len,  in tg3_nvram_write_block()
3556 			ret = tg3_nvram_write_block_unbuffered(tp, offset, len,  in tg3_nvram_write_block()
3563 		tg3_disable_nvram_access(tp);  in tg3_nvram_write_block()
3564 		tg3_nvram_unlock(tp);  in tg3_nvram_write_block()
3567 	if (tg3_flag(tp, EEPROM_WRITE_PROT)) {  in tg3_nvram_write_block()
3568 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_nvram_write_block()
3581 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_pause_cpu()  argument
3591 		if (pci_channel_offline(tp->pdev))  in tg3_pause_cpu()
3599 static int tg3_rxcpu_pause(struct tg3 *tp)  in tg3_rxcpu_pause()  argument
3601 	int rc = tg3_pause_cpu(tp, RX_CPU_BASE);  in tg3_rxcpu_pause()
3611 static int tg3_txcpu_pause(struct tg3 *tp)  in tg3_txcpu_pause()  argument
3613 	return tg3_pause_cpu(tp, TX_CPU_BASE);  in tg3_txcpu_pause()
3617 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_resume_cpu()  argument
3624 static void tg3_rxcpu_resume(struct tg3 *tp)  in tg3_rxcpu_resume()  argument
3626 	tg3_resume_cpu(tp, RX_CPU_BASE);  in tg3_rxcpu_resume()
3630 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)  in tg3_halt_cpu()  argument
3634 	BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));  in tg3_halt_cpu()
3636 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_halt_cpu()
3643 		rc = tg3_rxcpu_pause(tp);  in tg3_halt_cpu()
3649 		if (tg3_flag(tp, IS_SSB_CORE))  in tg3_halt_cpu()
3652 		rc = tg3_txcpu_pause(tp);  in tg3_halt_cpu()
3656 		netdev_err(tp->dev, "%s timed out, %s CPU\n",  in tg3_halt_cpu()
3662 	if (tg3_flag(tp, NVRAM))  in tg3_halt_cpu()
3667 static int tg3_fw_data_len(struct tg3 *tp,  in tg3_fw_data_len()  argument
3686 	if (tp->fw_len == 0xffffffff)  in tg3_fw_data_len()
3689 		fw_len = tp->fw->size;  in tg3_fw_data_len()
3695 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,  in tg3_load_firmware_cpu()  argument
3701 	int total_len = tp->fw->size;  in tg3_load_firmware_cpu()
3703 	if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {  in tg3_load_firmware_cpu()
3704 		netdev_err(tp->dev,  in tg3_load_firmware_cpu()
3710 	if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)  in tg3_load_firmware_cpu()
3715 	if (tg3_asic_rev(tp) != ASIC_REV_57766) {  in tg3_load_firmware_cpu()
3719 		int lock_err = tg3_nvram_lock(tp);  in tg3_load_firmware_cpu()
3720 		err = tg3_halt_cpu(tp, cpu_base);  in tg3_load_firmware_cpu()
3722 			tg3_nvram_unlock(tp);  in tg3_load_firmware_cpu()
3727 			write_op(tp, cpu_scratch_base + i, 0);  in tg3_load_firmware_cpu()
3741 		for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)  in tg3_load_firmware_cpu()
3742 			write_op(tp, cpu_scratch_base +  in tg3_load_firmware_cpu()
3761 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)  in tg3_pause_cpu_and_set_pc()  argument
3782 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)  in tg3_load_5701_a0_firmware_fix()  argument
3787 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_5701_a0_firmware_fix()
3795 	err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3801 	err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3808 	err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,  in tg3_load_5701_a0_firmware_fix()
3811 		netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "  in tg3_load_5701_a0_firmware_fix()
3818 	tg3_rxcpu_resume(tp);  in tg3_load_5701_a0_firmware_fix()
3823 static int tg3_validate_rxcpu_state(struct tg3 *tp)  in tg3_validate_rxcpu_state()  argument
3840 		netdev_err(tp->dev, "Boot code not ready for service patches\n");  in tg3_validate_rxcpu_state()
3844 	val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);  in tg3_validate_rxcpu_state()
3846 		netdev_warn(tp->dev,  in tg3_validate_rxcpu_state()
3855 static void tg3_load_57766_firmware(struct tg3 *tp)  in tg3_load_57766_firmware()  argument
3859 	if (!tg3_flag(tp, NO_NVRAM))  in tg3_load_57766_firmware()
3862 	if (tg3_validate_rxcpu_state(tp))  in tg3_load_57766_firmware()
3865 	if (!tp->fw)  in tg3_load_57766_firmware()
3882 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_57766_firmware()
3886 	if (tg3_rxcpu_pause(tp))  in tg3_load_57766_firmware()
3890 	tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);  in tg3_load_57766_firmware()
3892 	tg3_rxcpu_resume(tp);  in tg3_load_57766_firmware()
3896 static int tg3_load_tso_firmware(struct tg3 *tp)  in tg3_load_tso_firmware()  argument
3902 	if (!tg3_flag(tp, FW_TSO))  in tg3_load_tso_firmware()
3905 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_load_tso_firmware()
3913 	cpu_scratch_size = tp->fw_len;  in tg3_load_tso_firmware()
3915 	if (tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_load_tso_firmware()
3924 	err = tg3_load_firmware_cpu(tp, cpu_base,  in tg3_load_tso_firmware()
3931 	err = tg3_pause_cpu_and_set_pc(tp, cpu_base,  in tg3_load_tso_firmware()
3934 		netdev_err(tp->dev,  in tg3_load_tso_firmware()
3941 	tg3_resume_cpu(tp, cpu_base);  in tg3_load_tso_firmware()
3946 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr,  in __tg3_set_one_mac_addr()  argument
3966 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)  in __tg3_set_mac_addr()  argument
3974 		__tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);  in __tg3_set_mac_addr()
3977 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in __tg3_set_mac_addr()
3978 	    tg3_asic_rev(tp) == ASIC_REV_5704) {  in __tg3_set_mac_addr()
3980 			__tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);  in __tg3_set_mac_addr()
3983 	addr_high = (tp->dev->dev_addr[0] +  in __tg3_set_mac_addr()
3984 		     tp->dev->dev_addr[1] +  in __tg3_set_mac_addr()
3985 		     tp->dev->dev_addr[2] +  in __tg3_set_mac_addr()
3986 		     tp->dev->dev_addr[3] +  in __tg3_set_mac_addr()
3987 		     tp->dev->dev_addr[4] +  in __tg3_set_mac_addr()
3988 		     tp->dev->dev_addr[5]) &  in __tg3_set_mac_addr()
3993 static void tg3_enable_register_access(struct tg3 *tp)  in tg3_enable_register_access()  argument
3999 	pci_write_config_dword(tp->pdev,  in tg3_enable_register_access()
4000 			       TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);  in tg3_enable_register_access()
4003 static int tg3_power_up(struct tg3 *tp)  in tg3_power_up()  argument
4007 	tg3_enable_register_access(tp);  in tg3_power_up()
4009 	err = pci_set_power_state(tp->pdev, PCI_D0);  in tg3_power_up()
4012 		tg3_pwrsrc_switch_to_vmain(tp);  in tg3_power_up()
4014 		netdev_err(tp->dev, "Transition to D0 failed\n");  in tg3_power_up()
4022 static int tg3_power_down_prepare(struct tg3 *tp)  in tg3_power_down_prepare()  argument
4027 	tg3_enable_register_access(tp);  in tg3_power_down_prepare()
4030 	if (tg3_flag(tp, CLKREQ_BUG))  in tg3_power_down_prepare()
4031 		pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_power_down_prepare()
4038 	device_should_wake = device_may_wakeup(&tp->pdev->dev) &&  in tg3_power_down_prepare()
4039 			     tg3_flag(tp, WOL_ENABLE);  in tg3_power_down_prepare()
4041 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_power_down_prepare()
4043 		if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&  in tg3_power_down_prepare()
4044 		    !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_power_down_prepare()
4049 			phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_power_down_prepare()
4051 			tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;  in tg3_power_down_prepare()
4053 			tp->link_config.speed = phydev->speed;  in tg3_power_down_prepare()
4054 			tp->link_config.duplex = phydev->duplex;  in tg3_power_down_prepare()
4055 			tp->link_config.autoneg = phydev->autoneg;  in tg3_power_down_prepare()
4057 				&tp->link_config.advertising,  in tg3_power_down_prepare()
4068 			if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {  in tg3_power_down_prepare()
4069 				if (tg3_flag(tp, WOL_SPEED_100MB)) {  in tg3_power_down_prepare()
4097 		if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))  in tg3_power_down_prepare()
4098 			tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;  in tg3_power_down_prepare()
4100 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_power_down_prepare()
4101 			tg3_setup_phy(tp, false);  in tg3_power_down_prepare()
4104 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_prepare()
4109 	} else if (!tg3_flag(tp, ENABLE_ASF)) {  in tg3_power_down_prepare()
4114 			tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);  in tg3_power_down_prepare()
4120 	if (tg3_flag(tp, WOL_CAP))  in tg3_power_down_prepare()
4121 		tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |  in tg3_power_down_prepare()
4129 		if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_power_down_prepare()
4131 			    !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_power_down_prepare()
4132 				tg3_phy_auxctl_write(tp,  in tg3_power_down_prepare()
4140 			if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_power_down_prepare()
4142 			else if (tp->phy_flags &  in tg3_power_down_prepare()
4144 				if (tp->link_config.active_speed == SPEED_1000)  in tg3_power_down_prepare()
4151 			mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;  in tg3_power_down_prepare()
4152 			if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_power_down_prepare()
4153 				u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?  in tg3_power_down_prepare()
4155 				if (tg3_5700_link_polarity(tp, speed))  in tg3_power_down_prepare()
4164 		if (!tg3_flag(tp, 5750_PLUS))  in tg3_power_down_prepare()
4165 			tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_power_down_prepare()
4168 		if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&  in tg3_power_down_prepare()
4169 		    (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))  in tg3_power_down_prepare()
4172 		if (tg3_flag(tp, ENABLE_APE))  in tg3_power_down_prepare()
4184 	if (!tg3_flag(tp, WOL_SPEED_100MB) &&  in tg3_power_down_prepare()
4185 	    (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4186 	     tg3_asic_rev(tp) == ASIC_REV_5701)) {  in tg3_power_down_prepare()
4189 		base_val = tp->pci_clock_ctrl;  in tg3_power_down_prepare()
4195 	} else if (tg3_flag(tp, 5780_CLASS) ||  in tg3_power_down_prepare()
4196 		   tg3_flag(tp, CPMU_PRESENT) ||  in tg3_power_down_prepare()
4197 		   tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_power_down_prepare()
4199 	} else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {  in tg3_power_down_prepare()
4202 		if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4203 		    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_power_down_prepare()
4208 		} else if (tg3_flag(tp, 5705_PLUS)) {  in tg3_power_down_prepare()
4216 		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,  in tg3_power_down_prepare()
4219 		tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,  in tg3_power_down_prepare()
4222 		if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_power_down_prepare()
4225 			if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_power_down_prepare()
4226 			    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_power_down_prepare()
4235 				    tp->pci_clock_ctrl | newbits3, 40);  in tg3_power_down_prepare()
4239 	if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))  in tg3_power_down_prepare()
4240 		tg3_power_down_phy(tp, do_low_power);  in tg3_power_down_prepare()
4242 	tg3_frob_aux_power(tp, true);  in tg3_power_down_prepare()
4245 	if ((!tg3_flag(tp, IS_SSB_CORE)) &&  in tg3_power_down_prepare()
4246 	    ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||  in tg3_power_down_prepare()
4247 	     (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {  in tg3_power_down_prepare()
4252 		if (!tg3_flag(tp, ENABLE_ASF)) {  in tg3_power_down_prepare()
4255 			err = tg3_nvram_lock(tp);  in tg3_power_down_prepare()
4256 			tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_power_down_prepare()
4258 				tg3_nvram_unlock(tp);  in tg3_power_down_prepare()
4262 	tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);  in tg3_power_down_prepare()
4264 	tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);  in tg3_power_down_prepare()
4269 static void tg3_power_down(struct tg3 *tp)  in tg3_power_down()  argument
4271 	pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));  in tg3_power_down()
4272 	pci_set_power_state(tp->pdev, PCI_D3hot);  in tg3_power_down()
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)  in tg3_aux_stat_to_speed_duplex()  argument
4309 		if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_aux_stat_to_speed_duplex()
4322 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)  in tg3_phy_autoneg_cfg()  argument
4331 	err = tg3_writephy(tp, MII_ADVERTISE, new_adv);  in tg3_phy_autoneg_cfg()
4335 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_autoneg_cfg()
4338 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_phy_autoneg_cfg()
4339 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)  in tg3_phy_autoneg_cfg()
4342 		err = tg3_writephy(tp, MII_CTRL1000, new_adv);  in tg3_phy_autoneg_cfg()
4347 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_autoneg_cfg()
4353 	err = tg3_phy_toggle_auxctl_smdsp(tp, true);  in tg3_phy_autoneg_cfg()
4365 		if (!tp->eee.eee_enabled) {  in tg3_phy_autoneg_cfg()
4367 			tp->eee.advertised = 0;  in tg3_phy_autoneg_cfg()
4369 			tp->eee.advertised = advertise &  in tg3_phy_autoneg_cfg()
4374 		err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);  in tg3_phy_autoneg_cfg()
4378 		switch (tg3_asic_rev(tp)) {  in tg3_phy_autoneg_cfg()
4388 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_autoneg_cfg()
4392 			if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))  in tg3_phy_autoneg_cfg()
4393 				tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |  in tg3_phy_autoneg_cfg()
4397 		err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);  in tg3_phy_autoneg_cfg()
4406 static void tg3_phy_copper_begin(struct tg3 *tp)  in tg3_phy_copper_begin()  argument
4408 	if (tp->link_config.autoneg == AUTONEG_ENABLE ||  in tg3_phy_copper_begin()
4409 	    (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_phy_copper_begin()
4412 		if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&  in tg3_phy_copper_begin()
4413 		    !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {  in tg3_phy_copper_begin()
4416 			if (tg3_flag(tp, WOL_SPEED_100MB))  in tg3_phy_copper_begin()
4419 			if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {  in tg3_phy_copper_begin()
4420 				if (!(tp->phy_flags &  in tg3_phy_copper_begin()
4428 			adv = tp->link_config.advertising;  in tg3_phy_copper_begin()
4429 			if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_phy_copper_begin()
4433 			fc = tp->link_config.flowctrl;  in tg3_phy_copper_begin()
4436 		tg3_phy_autoneg_cfg(tp, adv, fc);  in tg3_phy_copper_begin()
4438 		if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&  in tg3_phy_copper_begin()
4439 		    (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {  in tg3_phy_copper_begin()
4447 		tg3_writephy(tp, MII_BMCR,  in tg3_phy_copper_begin()
4453 		tp->link_config.active_speed = tp->link_config.speed;  in tg3_phy_copper_begin()
4454 		tp->link_config.active_duplex = tp->link_config.duplex;  in tg3_phy_copper_begin()
4456 		if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_phy_copper_begin()
4461 			tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);  in tg3_phy_copper_begin()
4465 		switch (tp->link_config.speed) {  in tg3_phy_copper_begin()
4479 		if (tp->link_config.duplex == DUPLEX_FULL)  in tg3_phy_copper_begin()
4482 		if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&  in tg3_phy_copper_begin()
4484 			tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);  in tg3_phy_copper_begin()
4489 				if (tg3_readphy(tp, MII_BMSR, &tmp) ||  in tg3_phy_copper_begin()
4490 				    tg3_readphy(tp, MII_BMSR, &tmp))  in tg3_phy_copper_begin()
4497 			tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_phy_copper_begin()
4503 static int tg3_phy_pull_config(struct tg3 *tp)  in tg3_phy_pull_config()  argument
4508 	err = tg3_readphy(tp, MII_BMCR, &val);  in tg3_phy_pull_config()
4513 		tp->link_config.autoneg = AUTONEG_DISABLE;  in tg3_phy_pull_config()
4514 		tp->link_config.advertising = 0;  in tg3_phy_pull_config()
4515 		tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_phy_pull_config()
4521 			if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_phy_pull_config()
4524 			tp->link_config.speed = SPEED_10;  in tg3_phy_pull_config()
4527 			if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_phy_pull_config()
4530 			tp->link_config.speed = SPEED_100;  in tg3_phy_pull_config()
4533 			if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_pull_config()
4534 				tp->link_config.speed = SPEED_1000;  in tg3_phy_pull_config()
4543 			tp->link_config.duplex = DUPLEX_FULL;  in tg3_phy_pull_config()
4545 			tp->link_config.duplex = DUPLEX_HALF;  in tg3_phy_pull_config()
4547 		tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;  in tg3_phy_pull_config()
4553 	tp->link_config.autoneg = AUTONEG_ENABLE;  in tg3_phy_pull_config()
4554 	tp->link_config.advertising = ADVERTISED_Autoneg;  in tg3_phy_pull_config()
4555 	tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_phy_pull_config()
4557 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_phy_pull_config()
4560 		err = tg3_readphy(tp, MII_ADVERTISE, &val);  in tg3_phy_pull_config()
4565 		tp->link_config.advertising |= adv | ADVERTISED_TP;  in tg3_phy_pull_config()
4567 		tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);  in tg3_phy_pull_config()
4569 		tp->link_config.advertising |= ADVERTISED_FIBRE;  in tg3_phy_pull_config()
4572 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_pull_config()
4575 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_phy_pull_config()
4576 			err = tg3_readphy(tp, MII_CTRL1000, &val);  in tg3_phy_pull_config()
4582 			err = tg3_readphy(tp, MII_ADVERTISE, &val);  in tg3_phy_pull_config()
4587 			tp->link_config.flowctrl = adv;  in tg3_phy_pull_config()
4593 		tp->link_config.advertising |= adv;  in tg3_phy_pull_config()
4600 static int tg3_init_5401phy_dsp(struct tg3 *tp)  in tg3_init_5401phy_dsp()  argument
4606 	err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);  in tg3_init_5401phy_dsp()
4608 	err |= tg3_phydsp_write(tp, 0x0012, 0x1804);  in tg3_init_5401phy_dsp()
4609 	err |= tg3_phydsp_write(tp, 0x0013, 0x1204);  in tg3_init_5401phy_dsp()
4610 	err |= tg3_phydsp_write(tp, 0x8006, 0x0132);  in tg3_init_5401phy_dsp()
4611 	err |= tg3_phydsp_write(tp, 0x8006, 0x0232);  in tg3_init_5401phy_dsp()
4612 	err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);  in tg3_init_5401phy_dsp()
4619 static bool tg3_phy_eee_config_ok(struct tg3 *tp)  in tg3_phy_eee_config_ok()  argument
4623 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))  in tg3_phy_eee_config_ok()
4626 	tg3_eee_pull_config(tp, &eee);  in tg3_phy_eee_config_ok()
4628 	if (tp->eee.eee_enabled) {  in tg3_phy_eee_config_ok()
4629 		if (tp->eee.advertised != eee.advertised ||  in tg3_phy_eee_config_ok()
4630 		    tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||  in tg3_phy_eee_config_ok()
4631 		    tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)  in tg3_phy_eee_config_ok()
4642 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)  in tg3_phy_copper_an_config_ok()  argument
4646 	advertising = tp->link_config.advertising;  in tg3_phy_copper_an_config_ok()
4650 	if (tp->link_config.active_duplex == DUPLEX_FULL) {  in tg3_phy_copper_an_config_ok()
4651 		tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);  in tg3_phy_copper_an_config_ok()
4655 	if (tg3_readphy(tp, MII_ADVERTISE, lcladv))  in tg3_phy_copper_an_config_ok()
4661 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_copper_an_config_ok()
4666 		if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))  in tg3_phy_copper_an_config_ok()
4670 		    (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_phy_copper_an_config_ok()
4671 		     tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {  in tg3_phy_copper_an_config_ok()
4686 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)  in tg3_phy_copper_fetch_rmtadv()  argument
4690 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_copper_fetch_rmtadv()
4693 		if (tg3_readphy(tp, MII_STAT1000, &val))  in tg3_phy_copper_fetch_rmtadv()
4699 	if (tg3_readphy(tp, MII_LPA, rmtadv))  in tg3_phy_copper_fetch_rmtadv()
4703 	tp->link_config.rmt_adv = lpeth;  in tg3_phy_copper_fetch_rmtadv()
4708 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)  in tg3_test_and_report_link_chg()  argument
4710 	if (curr_link_up != tp->link_up) {  in tg3_test_and_report_link_chg()
4712 			netif_carrier_on(tp->dev);  in tg3_test_and_report_link_chg()
4714 			netif_carrier_off(tp->dev);  in tg3_test_and_report_link_chg()
4715 			if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_test_and_report_link_chg()
4716 				tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_test_and_report_link_chg()
4719 		tg3_link_report(tp);  in tg3_test_and_report_link_chg()
4726 static void tg3_clear_mac_status(struct tg3 *tp)  in tg3_clear_mac_status()  argument
4738 static void tg3_setup_eee(struct tg3 *tp)  in tg3_setup_eee()  argument
4744 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)  in tg3_setup_eee()
4753 	      (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |  in tg3_setup_eee()
4757 	if (tg3_asic_rev(tp) != ASIC_REV_5717)  in tg3_setup_eee()
4760 	if (tg3_flag(tp, ENABLE_APE))  in tg3_setup_eee()
4763 	tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);  in tg3_setup_eee()
4767 	       (tp->eee.tx_lpi_timer & 0xffff));  in tg3_setup_eee()
4774 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_copper_phy()  argument
4783 	tg3_clear_mac_status(tp);  in tg3_setup_copper_phy()
4785 	if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {  in tg3_setup_copper_phy()
4787 		     (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));  in tg3_setup_copper_phy()
4791 	tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);  in tg3_setup_copper_phy()
4796 	if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_setup_copper_phy()
4797 	     tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_setup_copper_phy()
4798 	     tg3_asic_rev(tp) == ASIC_REV_5705) &&  in tg3_setup_copper_phy()
4799 	    tp->link_up) {  in tg3_setup_copper_phy()
4800 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4801 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4806 		tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4808 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_setup_copper_phy()
4809 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4810 		if (tg3_readphy(tp, MII_BMSR, &bmsr) ||  in tg3_setup_copper_phy()
4811 		    !tg3_flag(tp, INIT_COMPLETE))  in tg3_setup_copper_phy()
4815 			err = tg3_init_5401phy_dsp(tp);  in tg3_setup_copper_phy()
4819 			tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4822 				if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4829 			if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==  in tg3_setup_copper_phy()
4832 			    tp->link_config.active_speed == SPEED_1000) {  in tg3_setup_copper_phy()
4833 				err = tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4835 					err = tg3_init_5401phy_dsp(tp);  in tg3_setup_copper_phy()
4840 	} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_setup_copper_phy()
4841 		   tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {  in tg3_setup_copper_phy()
4843 		tg3_writephy(tp, 0x15, 0x0a75);  in tg3_setup_copper_phy()
4844 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);  in tg3_setup_copper_phy()
4845 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);  in tg3_setup_copper_phy()
4846 		tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);  in tg3_setup_copper_phy()
4850 	tg3_readphy(tp, MII_TG3_ISTAT, &val);  in tg3_setup_copper_phy()
4851 	tg3_readphy(tp, MII_TG3_ISTAT, &val);  in tg3_setup_copper_phy()
4853 	if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)  in tg3_setup_copper_phy()
4854 		tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);  in tg3_setup_copper_phy()
4855 	else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))  in tg3_setup_copper_phy()
4856 		tg3_writephy(tp, MII_TG3_IMASK, ~0);  in tg3_setup_copper_phy()
4858 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_setup_copper_phy()
4859 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_setup_copper_phy()
4860 		if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)  in tg3_setup_copper_phy()
4861 			tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_setup_copper_phy()
4864 			tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);  in tg3_setup_copper_phy()
4870 	tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;  in tg3_setup_copper_phy()
4871 	tp->link_config.rmt_adv = 0;  in tg3_setup_copper_phy()
4873 	if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {  in tg3_setup_copper_phy()
4874 		err = tg3_phy_auxctl_read(tp,  in tg3_setup_copper_phy()
4878 			tg3_phy_auxctl_write(tp,  in tg3_setup_copper_phy()
4887 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4888 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_setup_copper_phy()
4897 		tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);  in tg3_setup_copper_phy()
4900 			if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&  in tg3_setup_copper_phy()
4905 		tg3_aux_stat_to_speed_duplex(tp, aux_stat,  in tg3_setup_copper_phy()
4911 			tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_setup_copper_phy()
4912 			if (tg3_readphy(tp, MII_BMCR, &bmcr))  in tg3_setup_copper_phy()
4922 		tp->link_config.active_speed = current_speed;  in tg3_setup_copper_phy()
4923 		tp->link_config.active_duplex = current_duplex;  in tg3_setup_copper_phy()
4925 		if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_copper_phy()
4926 			bool eee_config_ok = tg3_phy_eee_config_ok(tp);  in tg3_setup_copper_phy()
4930 			    tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&  in tg3_setup_copper_phy()
4931 			    tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))  in tg3_setup_copper_phy()
4939 			    (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_setup_copper_phy()
4941 				tg3_setup_eee(tp);  in tg3_setup_copper_phy()
4942 				tg3_phy_reset(tp);  in tg3_setup_copper_phy()
4946 			    tp->link_config.speed == current_speed &&  in tg3_setup_copper_phy()
4947 			    tp->link_config.duplex == current_duplex) {  in tg3_setup_copper_phy()
4953 		    tp->link_config.active_duplex == DUPLEX_FULL) {  in tg3_setup_copper_phy()
4956 			if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_setup_copper_phy()
4964 			if (!tg3_readphy(tp, reg, &val) && (val & bit))  in tg3_setup_copper_phy()
4965 				tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;  in tg3_setup_copper_phy()
4967 			tg3_setup_flow_control(tp, lcl_adv, rmt_adv);  in tg3_setup_copper_phy()
4972 	if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {  in tg3_setup_copper_phy()
4973 		tg3_phy_copper_begin(tp);  in tg3_setup_copper_phy()
4975 		if (tg3_flag(tp, ROBOSWITCH)) {  in tg3_setup_copper_phy()
4980 			tp->link_config.active_speed = current_speed;  in tg3_setup_copper_phy()
4981 			tp->link_config.active_duplex = current_duplex;  in tg3_setup_copper_phy()
4984 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_copper_phy()
4985 		if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||  in tg3_setup_copper_phy()
4986 		    (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))  in tg3_setup_copper_phy()
4990 	tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;  in tg3_setup_copper_phy()
4992 		if (tp->link_config.active_speed == SPEED_100 ||  in tg3_setup_copper_phy()
4993 		    tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
4994 			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_copper_phy()
4996 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_copper_phy()
4997 	} else if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_setup_copper_phy()
4998 		tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_copper_phy()
5000 		tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_copper_phy()
5005 	if (tg3_flag(tp, RGMII_MODE)) {  in tg3_setup_copper_phy()
5009 		if (tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
5011 		else if (tp->link_config.active_speed == SPEED_100)  in tg3_setup_copper_phy()
5014 		else if (tp->link_config.active_speed == SPEED_1000)  in tg3_setup_copper_phy()
5022 	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;  in tg3_setup_copper_phy()
5023 	if (tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_copper_phy()
5024 		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;  in tg3_setup_copper_phy()
5026 	if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_setup_copper_phy()
5028 		    tg3_5700_link_polarity(tp, tp->link_config.active_speed))  in tg3_setup_copper_phy()
5029 			tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_setup_copper_phy()
5031 			tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;  in tg3_setup_copper_phy()
5037 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&  in tg3_setup_copper_phy()
5038 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {  in tg3_setup_copper_phy()
5039 		tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;  in tg3_setup_copper_phy()
5040 		tw32_f(MAC_MI_MODE, tp->mi_mode);  in tg3_setup_copper_phy()
5044 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_copper_phy()
5047 	tg3_phy_eee_adjust(tp, current_link_up);  in tg3_setup_copper_phy()
5049 	if (tg3_flag(tp, USE_LINKCHG_REG)) {  in tg3_setup_copper_phy()
5057 	if (tg3_asic_rev(tp) == ASIC_REV_5700 &&  in tg3_setup_copper_phy()
5059 	    tp->link_config.active_speed == SPEED_1000 &&  in tg3_setup_copper_phy()
5060 	    (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {  in tg3_setup_copper_phy()
5066 		tg3_write_mem(tp,  in tg3_setup_copper_phy()
5072 	if (tg3_flag(tp, CLKREQ_BUG)) {  in tg3_setup_copper_phy()
5073 		if (tp->link_config.active_speed == SPEED_100 ||  in tg3_setup_copper_phy()
5074 		    tp->link_config.active_speed == SPEED_10)  in tg3_setup_copper_phy()
5075 			pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_setup_copper_phy()
5078 			pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,  in tg3_setup_copper_phy()
5082 	tg3_test_and_report_link_chg(tp, current_link_up);  in tg3_setup_copper_phy()
5151 static int tg3_fiber_aneg_smachine(struct tg3 *tp,  in tg3_fiber_aneg_smachine()  argument
5231 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5232 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5254 		flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_fiber_aneg_smachine()
5260 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5261 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5275 		tp->mac_mode |= MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5276 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5361 		tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;  in tg3_fiber_aneg_smachine()
5362 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_fiber_aneg_smachine()
5403 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)  in fiber_autoneg()  argument
5413 	tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;  in fiber_autoneg()
5417 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);  in fiber_autoneg()
5426 		status = tg3_fiber_aneg_smachine(tp, &aninfo);  in fiber_autoneg()
5433 	tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;  in fiber_autoneg()
5434 	tw32_f(MAC_MODE, tp->mac_mode);  in fiber_autoneg()
5448 static void tg3_init_bcm8002(struct tg3 *tp)  in tg3_init_bcm8002()  argument
5454 	if (tg3_flag(tp, INIT_COMPLETE) &&  in tg3_init_bcm8002()
5459 	tg3_writephy(tp, 0x16, 0x8007);  in tg3_init_bcm8002()
5462 	tg3_writephy(tp, MII_BMCR, BMCR_RESET);  in tg3_init_bcm8002()
5470 	tg3_writephy(tp, 0x10, 0x8411);  in tg3_init_bcm8002()
5473 	tg3_writephy(tp, 0x11, 0x0a10);  in tg3_init_bcm8002()
5475 	tg3_writephy(tp, 0x18, 0x00a0);  in tg3_init_bcm8002()
5476 	tg3_writephy(tp, 0x16, 0x41ff);  in tg3_init_bcm8002()
5479 	tg3_writephy(tp, 0x13, 0x0400);  in tg3_init_bcm8002()
5481 	tg3_writephy(tp, 0x13, 0x0000);  in tg3_init_bcm8002()
5483 	tg3_writephy(tp, 0x11, 0x0a50);  in tg3_init_bcm8002()
5485 	tg3_writephy(tp, 0x11, 0x0a10);  in tg3_init_bcm8002()
5495 	tg3_writephy(tp, 0x10, 0x8011);  in tg3_init_bcm8002()
5498 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)  in tg3_setup_fiber_hw_autoneg()  argument
5511 	if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&  in tg3_setup_fiber_hw_autoneg()
5512 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {  in tg3_setup_fiber_hw_autoneg()
5524 	if (tp->link_config.autoneg != AUTONEG_ENABLE) {  in tg3_setup_fiber_hw_autoneg()
5539 			tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_hw_autoneg()
5548 	flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_setup_fiber_hw_autoneg()
5555 		if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&  in tg3_setup_fiber_hw_autoneg()
5556 		    tp->serdes_counter &&  in tg3_setup_fiber_hw_autoneg()
5560 			tp->serdes_counter--;  in tg3_setup_fiber_hw_autoneg()
5571 		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;  in tg3_setup_fiber_hw_autoneg()
5572 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5592 			tp->link_config.rmt_adv =  in tg3_setup_fiber_hw_autoneg()
5595 			tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_hw_autoneg()
5597 			tp->serdes_counter = 0;  in tg3_setup_fiber_hw_autoneg()
5598 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5600 			if (tp->serdes_counter)  in tg3_setup_fiber_hw_autoneg()
5601 				tp->serdes_counter--;  in tg3_setup_fiber_hw_autoneg()
5623 					tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_hw_autoneg()
5625 					tp->phy_flags |=  in tg3_setup_fiber_hw_autoneg()
5627 					tp->serdes_counter =  in tg3_setup_fiber_hw_autoneg()
5634 		tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;  in tg3_setup_fiber_hw_autoneg()
5635 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_hw_autoneg()
5642 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)  in tg3_setup_fiber_by_hand()  argument
5649 	if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_fiber_by_hand()
5653 		if (fiber_autoneg(tp, &txflags, &rxflags)) {  in tg3_setup_fiber_by_hand()
5666 			tp->link_config.rmt_adv =  in tg3_setup_fiber_by_hand()
5669 			tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_by_hand()
5691 		tg3_setup_flow_control(tp, 0, 0);  in tg3_setup_fiber_by_hand()
5696 		tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));  in tg3_setup_fiber_by_hand()
5699 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_by_hand()
5707 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_fiber_phy()  argument
5716 	orig_pause_cfg = tp->link_config.active_flowctrl;  in tg3_setup_fiber_phy()
5717 	orig_active_speed = tp->link_config.active_speed;  in tg3_setup_fiber_phy()
5718 	orig_active_duplex = tp->link_config.active_duplex;  in tg3_setup_fiber_phy()
5720 	if (!tg3_flag(tp, HW_AUTONEG) &&  in tg3_setup_fiber_phy()
5721 	    tp->link_up &&  in tg3_setup_fiber_phy()
5722 	    tg3_flag(tp, INIT_COMPLETE)) {  in tg3_setup_fiber_phy()
5738 	tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);  in tg3_setup_fiber_phy()
5739 	tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;  in tg3_setup_fiber_phy()
5740 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_phy()
5743 	if (tp->phy_id == TG3_PHY_ID_BCM8002)  in tg3_setup_fiber_phy()
5744 		tg3_init_bcm8002(tp);  in tg3_setup_fiber_phy()
5750 	tp->link_config.rmt_adv = 0;  in tg3_setup_fiber_phy()
5753 	if (tg3_flag(tp, HW_AUTONEG))  in tg3_setup_fiber_phy()
5754 		current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);  in tg3_setup_fiber_phy()
5756 		current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);  in tg3_setup_fiber_phy()
5758 	tp->napi[0].hw_status->status =  in tg3_setup_fiber_phy()
5760 		 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));  in tg3_setup_fiber_phy()
5775 		if (tp->link_config.autoneg == AUTONEG_ENABLE &&  in tg3_setup_fiber_phy()
5776 		    tp->serdes_counter == 0) {  in tg3_setup_fiber_phy()
5777 			tw32_f(MAC_MODE, (tp->mac_mode |  in tg3_setup_fiber_phy()
5780 			tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_phy()
5785 		tp->link_config.active_speed = SPEED_1000;  in tg3_setup_fiber_phy()
5786 		tp->link_config.active_duplex = DUPLEX_FULL;  in tg3_setup_fiber_phy()
5787 		tw32(MAC_LED_CTRL, (tp->led_ctrl |  in tg3_setup_fiber_phy()
5791 		tp->link_config.active_speed = SPEED_UNKNOWN;  in tg3_setup_fiber_phy()
5792 		tp->link_config.active_duplex = DUPLEX_UNKNOWN;  in tg3_setup_fiber_phy()
5793 		tw32(MAC_LED_CTRL, (tp->led_ctrl |  in tg3_setup_fiber_phy()
5798 	if (!tg3_test_and_report_link_chg(tp, current_link_up)) {  in tg3_setup_fiber_phy()
5799 		u32 now_pause_cfg = tp->link_config.active_flowctrl;  in tg3_setup_fiber_phy()
5801 		    orig_active_speed != tp->link_config.active_speed ||  in tg3_setup_fiber_phy()
5802 		    orig_active_duplex != tp->link_config.active_duplex)  in tg3_setup_fiber_phy()
5803 			tg3_link_report(tp);  in tg3_setup_fiber_phy()
5809 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_fiber_mii_phy()  argument
5818 	if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_setup_fiber_mii_phy()
5819 	     tg3_asic_rev(tp) == ASIC_REV_5720) &&  in tg3_setup_fiber_mii_phy()
5820 	     !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&  in tg3_setup_fiber_mii_phy()
5824 			tg3_phy_reset(tp);  in tg3_setup_fiber_mii_phy()
5826 		tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;  in tg3_setup_fiber_mii_phy()
5829 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5834 				tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5837 				tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_fiber_mii_phy()
5840 				tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_setup_fiber_mii_phy()
5849 		tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
5852 		tg3_clear_mac_status(tp);  in tg3_setup_fiber_mii_phy()
5857 	tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_setup_fiber_mii_phy()
5858 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
5861 	tg3_clear_mac_status(tp);  in tg3_setup_fiber_mii_phy()
5864 		tg3_phy_reset(tp);  in tg3_setup_fiber_mii_phy()
5866 	tp->link_config.rmt_adv = 0;  in tg3_setup_fiber_mii_phy()
5868 	err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5869 	err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5870 	if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_setup_fiber_mii_phy()
5877 	err |= tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_setup_fiber_mii_phy()
5879 	if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&  in tg3_setup_fiber_mii_phy()
5880 	    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {  in tg3_setup_fiber_mii_phy()
5882 	} else if (tp->link_config.autoneg == AUTONEG_ENABLE) {  in tg3_setup_fiber_mii_phy()
5885 		err |= tg3_readphy(tp, MII_ADVERTISE, &adv);  in tg3_setup_fiber_mii_phy()
5891 		newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);  in tg3_setup_fiber_mii_phy()
5892 		newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);  in tg3_setup_fiber_mii_phy()
5895 			tg3_writephy(tp, MII_ADVERTISE, newadv);  in tg3_setup_fiber_mii_phy()
5897 			tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_setup_fiber_mii_phy()
5900 			tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;  in tg3_setup_fiber_mii_phy()
5901 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_mii_phy()
5911 		if (tp->link_config.duplex == DUPLEX_FULL)  in tg3_setup_fiber_mii_phy()
5921 			if (tp->link_up) {  in tg3_setup_fiber_mii_phy()
5924 				err |= tg3_readphy(tp, MII_ADVERTISE, &adv);  in tg3_setup_fiber_mii_phy()
5928 				tg3_writephy(tp, MII_ADVERTISE, adv);  in tg3_setup_fiber_mii_phy()
5929 				tg3_writephy(tp, MII_BMCR, bmcr |  in tg3_setup_fiber_mii_phy()
5933 				tg3_carrier_off(tp);  in tg3_setup_fiber_mii_phy()
5935 			tg3_writephy(tp, MII_BMCR, new_bmcr);  in tg3_setup_fiber_mii_phy()
5937 			err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5938 			err |= tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_setup_fiber_mii_phy()
5939 			if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_setup_fiber_mii_phy()
5945 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_setup_fiber_mii_phy()
5963 			err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);  in tg3_setup_fiber_mii_phy()
5964 			err |= tg3_readphy(tp, MII_LPA, &remote_adv);  in tg3_setup_fiber_mii_phy()
5973 				tp->link_config.rmt_adv =  in tg3_setup_fiber_mii_phy()
5975 			} else if (!tg3_flag(tp, 5780_CLASS)) {  in tg3_setup_fiber_mii_phy()
5985 		tg3_setup_flow_control(tp, local_adv, remote_adv);  in tg3_setup_fiber_mii_phy()
5987 	tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;  in tg3_setup_fiber_mii_phy()
5988 	if (tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_fiber_mii_phy()
5989 		tp->mac_mode |= MAC_MODE_HALF_DUPLEX;  in tg3_setup_fiber_mii_phy()
5991 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_setup_fiber_mii_phy()
5996 	tp->link_config.active_speed = current_speed;  in tg3_setup_fiber_mii_phy()
5997 	tp->link_config.active_duplex = current_duplex;  in tg3_setup_fiber_mii_phy()
5999 	tg3_test_and_report_link_chg(tp, current_link_up);  in tg3_setup_fiber_mii_phy()
6003 static void tg3_serdes_parallel_detect(struct tg3 *tp)  in tg3_serdes_parallel_detect()  argument
6005 	if (tp->serdes_counter) {  in tg3_serdes_parallel_detect()
6007 		tp->serdes_counter--;  in tg3_serdes_parallel_detect()
6011 	if (!tp->link_up &&  in tg3_serdes_parallel_detect()
6012 	    (tp->link_config.autoneg == AUTONEG_ENABLE)) {  in tg3_serdes_parallel_detect()
6015 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_serdes_parallel_detect()
6020 			tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);  in tg3_serdes_parallel_detect()
6021 			tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);  in tg3_serdes_parallel_detect()
6024 			tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_serdes_parallel_detect()
6026 			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6027 			tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6037 				tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_serdes_parallel_detect()
6038 				tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;  in tg3_serdes_parallel_detect()
6041 	} else if (tp->link_up &&  in tg3_serdes_parallel_detect()
6042 		   (tp->link_config.autoneg == AUTONEG_ENABLE) &&  in tg3_serdes_parallel_detect()
6043 		   (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {  in tg3_serdes_parallel_detect()
6047 		tg3_writephy(tp, MII_TG3_DSP_ADDRESS,  in tg3_serdes_parallel_detect()
6049 		tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);  in tg3_serdes_parallel_detect()
6054 			tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_serdes_parallel_detect()
6055 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);  in tg3_serdes_parallel_detect()
6057 			tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_serdes_parallel_detect()
6063 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)  in tg3_setup_phy()  argument
6068 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_setup_phy()
6069 		err = tg3_setup_fiber_phy(tp, force_reset);  in tg3_setup_phy()
6070 	else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_setup_phy()
6071 		err = tg3_setup_fiber_mii_phy(tp, force_reset);  in tg3_setup_phy()
6073 		err = tg3_setup_copper_phy(tp, force_reset);  in tg3_setup_phy()
6075 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {  in tg3_setup_phy()
6093 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_setup_phy()
6094 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_setup_phy()
6099 	if (tp->link_config.active_speed == SPEED_1000 &&  in tg3_setup_phy()
6100 	    tp->link_config.active_duplex == DUPLEX_HALF)  in tg3_setup_phy()
6107 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_setup_phy()
6108 		if (tp->link_up) {  in tg3_setup_phy()
6110 			     tp->coal.stats_block_coalesce_usecs);  in tg3_setup_phy()
6116 	if (tg3_flag(tp, ASPM_WORKAROUND)) {  in tg3_setup_phy()
6118 		if (!tp->link_up)  in tg3_setup_phy()
6120 			      tp->pwrmgmt_thresh;  in tg3_setup_phy()
6130 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts)  in tg3_refclk_read()  argument
6143 static void tg3_refclk_write(struct tg3 *tp, u64 newval)  in tg3_refclk_write()  argument
6153 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6154 static inline void tg3_full_unlock(struct tg3 *tp);
6157 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ts_info()  local
6163 	if (tg3_flag(tp, PTP_CAPABLE)) {  in tg3_get_ts_info()
6169 	if (tp->ptp_clock)  in tg3_get_ts_info()
6170 		info->phc_index = ptp_clock_index(tp->ptp_clock);  in tg3_get_ts_info()
6185 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_adjfine()  local
6196 	tg3_full_lock(tp, 0);  in tg3_ptp_adjfine()
6206 	tg3_full_unlock(tp);  in tg3_ptp_adjfine()
6213 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_adjtime()  local
6215 	tg3_full_lock(tp, 0);  in tg3_ptp_adjtime()
6216 	tp->ptp_adjust += delta;  in tg3_ptp_adjtime()
6217 	tg3_full_unlock(tp);  in tg3_ptp_adjtime()
6226 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_gettimex()  local
6228 	tg3_full_lock(tp, 0);  in tg3_ptp_gettimex()
6229 	ns = tg3_refclk_read(tp, sts);  in tg3_ptp_gettimex()
6230 	ns += tp->ptp_adjust;  in tg3_ptp_gettimex()
6231 	tg3_full_unlock(tp);  in tg3_ptp_gettimex()
6242 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_settime()  local
6246 	tg3_full_lock(tp, 0);  in tg3_ptp_settime()
6247 	tg3_refclk_write(tp, ns);  in tg3_ptp_settime()
6248 	tp->ptp_adjust = 0;  in tg3_ptp_settime()
6249 	tg3_full_unlock(tp);  in tg3_ptp_settime()
6257 	struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);  in tg3_ptp_enable()  local
6270 		tg3_full_lock(tp, 0);  in tg3_ptp_enable()
6281 				netdev_warn(tp->dev,  in tg3_ptp_enable()
6288 				netdev_warn(tp->dev,  in tg3_ptp_enable()
6307 		tg3_full_unlock(tp);  in tg3_ptp_enable()
6333 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,  in tg3_hwclock_to_timestamp()  argument
6338 					   tp->ptp_adjust);  in tg3_hwclock_to_timestamp()
6342 static void tg3_ptp_init(struct tg3 *tp)  in tg3_ptp_init()  argument
6344 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_ptp_init()
6348 	tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));  in tg3_ptp_init()
6349 	tp->ptp_adjust = 0;  in tg3_ptp_init()
6350 	tp->ptp_info = tg3_ptp_caps;  in tg3_ptp_init()
6354 static void tg3_ptp_resume(struct tg3 *tp)  in tg3_ptp_resume()  argument
6356 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_ptp_resume()
6359 	tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);  in tg3_ptp_resume()
6360 	tp->ptp_adjust = 0;  in tg3_ptp_resume()
6363 static void tg3_ptp_fini(struct tg3 *tp)  in tg3_ptp_fini()  argument
6365 	if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)  in tg3_ptp_fini()
6368 	ptp_clock_unregister(tp->ptp_clock);  in tg3_ptp_fini()
6369 	tp->ptp_clock = NULL;  in tg3_ptp_fini()
6370 	tp->ptp_adjust = 0;  in tg3_ptp_fini()
6373 static inline int tg3_irq_sync(struct tg3 *tp)  in tg3_irq_sync()  argument
6375 	return tp->irq_sync;  in tg3_irq_sync()
6378 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)  in tg3_rd32_loop()  argument
6387 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)  in tg3_dump_legacy_regs()  argument
6389 	tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);  in tg3_dump_legacy_regs()
6390 	tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);  in tg3_dump_legacy_regs()
6391 	tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);  in tg3_dump_legacy_regs()
6392 	tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);  in tg3_dump_legacy_regs()
6393 	tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);  in tg3_dump_legacy_regs()
6394 	tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);  in tg3_dump_legacy_regs()
6395 	tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);  in tg3_dump_legacy_regs()
6396 	tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);  in tg3_dump_legacy_regs()
6397 	tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);  in tg3_dump_legacy_regs()
6398 	tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);  in tg3_dump_legacy_regs()
6399 	tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);  in tg3_dump_legacy_regs()
6400 	tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);  in tg3_dump_legacy_regs()
6401 	tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);  in tg3_dump_legacy_regs()
6402 	tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);  in tg3_dump_legacy_regs()
6403 	tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);  in tg3_dump_legacy_regs()
6404 	tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);  in tg3_dump_legacy_regs()
6405 	tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);  in tg3_dump_legacy_regs()
6406 	tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);  in tg3_dump_legacy_regs()
6407 	tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);  in tg3_dump_legacy_regs()
6409 	if (tg3_flag(tp, SUPPORT_MSIX))  in tg3_dump_legacy_regs()
6410 		tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);  in tg3_dump_legacy_regs()
6412 	tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);  in tg3_dump_legacy_regs()
6413 	tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);  in tg3_dump_legacy_regs()
6414 	tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);  in tg3_dump_legacy_regs()
6415 	tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);  in tg3_dump_legacy_regs()
6416 	tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);  in tg3_dump_legacy_regs()
6417 	tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);  in tg3_dump_legacy_regs()
6418 	tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);  in tg3_dump_legacy_regs()
6419 	tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);  in tg3_dump_legacy_regs()
6421 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_dump_legacy_regs()
6422 		tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);  in tg3_dump_legacy_regs()
6423 		tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);  in tg3_dump_legacy_regs()
6424 		tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);  in tg3_dump_legacy_regs()
6427 	tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);  in tg3_dump_legacy_regs()
6428 	tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);  in tg3_dump_legacy_regs()
6429 	tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);  in tg3_dump_legacy_regs()
6430 	tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);  in tg3_dump_legacy_regs()
6431 	tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);  in tg3_dump_legacy_regs()
6433 	if (tg3_flag(tp, NVRAM))  in tg3_dump_legacy_regs()
6434 		tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);  in tg3_dump_legacy_regs()
6437 static void tg3_dump_state(struct tg3 *tp)  in tg3_dump_state()  argument
6446 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_dump_state()
6451 		tg3_dump_legacy_regs(tp, regs);  in tg3_dump_state()
6458 		netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",  in tg3_dump_state()
6465 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_dump_state()
6466 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_dump_state()
6469 		netdev_err(tp->dev,  in tg3_dump_state()
6480 		netdev_err(tp->dev,  in tg3_dump_state()
6499 static void tg3_tx_recover(struct tg3 *tp)  in tg3_tx_recover()  argument
6501 	BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||  in tg3_tx_recover()
6502 	       tp->write32_tx_mbox == tg3_write_indirect_mbox);  in tg3_tx_recover()
6504 	netdev_warn(tp->dev,  in tg3_tx_recover()
6510 	tg3_flag_set(tp, TX_RECOVERY_PENDING);  in tg3_tx_recover()
6527 	struct tg3 *tp = tnapi->tp;  in tg3_tx()  local
6531 	int index = tnapi - tp->napi;  in tg3_tx()
6534 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_tx()
6537 	txq = netdev_get_tx_queue(tp->dev, index);  in tg3_tx()
6545 			tg3_tx_recover(tp);  in tg3_tx()
6554 			tg3_hwclock_to_timestamp(tp, hwclock, &timestamp);  in tg3_tx()
6559 		dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping),  in tg3_tx()
6577 			dma_unmap_page(&tp->pdev->dev,  in tg3_tx()
6597 			tg3_tx_recover(tp);  in tg3_tx()
6631 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)  in tg3_rx_data_free()  argument
6633 	unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +  in tg3_rx_data_free()
6639 	dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz,  in tg3_rx_data_free()
6657 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,  in tg3_alloc_rx_data()  argument
6669 		dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;  in tg3_alloc_rx_data()
6672 		data_size = tp->rx_pkt_map_sz;  in tg3_alloc_rx_data()
6676 		dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;  in tg3_alloc_rx_data()
6692 	skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +  in tg3_alloc_rx_data()
6704 	mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp),  in tg3_alloc_rx_data()
6706 	if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) {  in tg3_alloc_rx_data()
6729 	struct tg3 *tp = tnapi->tp;  in tg3_recycle_rx()  local
6732 	struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;  in tg3_recycle_rx()
6737 		dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;  in tg3_recycle_rx()
6745 		dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;  in tg3_recycle_rx()
6796 	struct tg3 *tp = tnapi->tp;  in tg3_rx()  local
6827 			ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];  in tg3_rx()
6833 			ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];  in tg3_rx()
6848 			tp->rx_dropped++;  in tg3_rx()
6852 		prefetch(data + TG3_RX_OFFSET(tp));  in tg3_rx()
6864 		if (len > TG3_RX_COPY_THRESH(tp)) {  in tg3_rx()
6868 			skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,  in tg3_rx()
6873 			dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size,  in tg3_rx()
6891 			skb_reserve(skb, TG3_RX_OFFSET(tp));  in tg3_rx()
6896 			skb = netdev_alloc_skb(tp->dev,  in tg3_rx()
6902 			dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len,  in tg3_rx()
6905 			       data + TG3_RX_OFFSET(tp),  in tg3_rx()
6907 			dma_sync_single_for_device(&tp->pdev->dev, dma_addr,  in tg3_rx()
6913 			tg3_hwclock_to_timestamp(tp, tstamp,  in tg3_rx()
6916 		if ((tp->dev->features & NETIF_F_RXCSUM) &&  in tg3_rx()
6924 		skb->protocol = eth_type_trans(skb, tp->dev);  in tg3_rx()
6926 		if (len > (tp->dev->mtu + ETH_HLEN) &&  in tg3_rx()
6934 		    !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))  in tg3_rx()
6946 		if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {  in tg3_rx()
6948 					       tp->rx_std_ring_mask;  in tg3_rx()
6956 		sw_idx &= tp->rx_ret_ring_mask;  in tg3_rx()
6970 	if (!tg3_flag(tp, ENABLE_RSS)) {  in tg3_rx()
6976 					       tp->rx_std_ring_mask;  in tg3_rx()
6982 					       tp->rx_jmb_ring_mask;  in tg3_rx()
6992 		tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;  in tg3_rx()
6993 		tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;  in tg3_rx()
6995 		if (tnapi != &tp->napi[1]) {  in tg3_rx()
6996 			tp->rx_refill = true;  in tg3_rx()
6997 			napi_schedule(&tp->napi[1].napi);  in tg3_rx()
7004 static void tg3_poll_link(struct tg3 *tp)  in tg3_poll_link()  argument
7007 	if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {  in tg3_poll_link()
7008 		struct tg3_hw_status *sblk = tp->napi[0].hw_status;  in tg3_poll_link()
7013 			spin_lock(&tp->lock);  in tg3_poll_link()
7014 			if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_poll_link()
7022 				tg3_setup_phy(tp, false);  in tg3_poll_link()
7023 			spin_unlock(&tp->lock);  in tg3_poll_link()
7028 static int tg3_rx_prodring_xfer(struct tg3 *tp,  in tg3_rx_prodring_xfer()  argument
7049 			cpycnt = tp->rx_std_ring_mask + 1 -  in tg3_rx_prodring_xfer()
7053 			     tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);  in tg3_rx_prodring_xfer()
7088 				       tp->rx_std_ring_mask;  in tg3_rx_prodring_xfer()
7090 				       tp->rx_std_ring_mask;  in tg3_rx_prodring_xfer()
7107 			cpycnt = tp->rx_jmb_ring_mask + 1 -  in tg3_rx_prodring_xfer()
7111 			     tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);  in tg3_rx_prodring_xfer()
7146 				       tp->rx_jmb_ring_mask;  in tg3_rx_prodring_xfer()
7148 				       tp->rx_jmb_ring_mask;  in tg3_rx_prodring_xfer()
7156 	struct tg3 *tp = tnapi->tp;  in tg3_poll_work()  local
7161 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll_work()
7175 	if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {  in tg3_poll_work()
7176 		struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;  in tg3_poll_work()
7181 		tp->rx_refill = false;  in tg3_poll_work()
7182 		for (i = 1; i <= tp->rxq_cnt; i++)  in tg3_poll_work()
7183 			err |= tg3_rx_prodring_xfer(tp, dpr,  in tg3_poll_work()
7184 						    &tp->napi[i].prodring);  in tg3_poll_work()
7197 			tw32_f(HOSTCC_MODE, tp->coal_now);  in tg3_poll_work()
7203 static inline void tg3_reset_task_schedule(struct tg3 *tp)  in tg3_reset_task_schedule()  argument
7205 	if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))  in tg3_reset_task_schedule()
7206 		schedule_work(&tp->reset_task);  in tg3_reset_task_schedule()
7209 static inline void tg3_reset_task_cancel(struct tg3 *tp)  in tg3_reset_task_cancel()  argument
7211 	if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))  in tg3_reset_task_cancel()
7212 		cancel_work_sync(&tp->reset_task);  in tg3_reset_task_cancel()
7213 	tg3_flag_clear(tp, TX_RECOVERY_PENDING);  in tg3_reset_task_cancel()
7219 	struct tg3 *tp = tnapi->tp;  in tg3_poll_msix()  local
7226 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll_msix()
7247 			if (tnapi == &tp->napi[1] && tp->rx_refill)  in tg3_poll_msix()
7257 			if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {  in tg3_poll_msix()
7258 				tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_poll_msix()
7266 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);  in tg3_poll_msix()
7272 	tg3_reset_task_schedule(tp);  in tg3_poll_msix()
7276 static void tg3_process_error(struct tg3 *tp)  in tg3_process_error()  argument
7281 	if (tg3_flag(tp, ERROR_PROCESSED))  in tg3_process_error()
7287 		netdev_err(tp->dev, "FLOW Attention error.  Resetting chip.\n");  in tg3_process_error()
7292 		netdev_err(tp->dev, "MSI Status error.  Resetting chip.\n");  in tg3_process_error()
7297 		netdev_err(tp->dev, "DMA Status error.  Resetting chip.\n");  in tg3_process_error()
7304 	tg3_dump_state(tp);  in tg3_process_error()
7306 	tg3_flag_set(tp, ERROR_PROCESSED);  in tg3_process_error()
7307 	tg3_reset_task_schedule(tp);  in tg3_process_error()
7313 	struct tg3 *tp = tnapi->tp;  in tg3_poll()  local
7319 			tg3_process_error(tp);  in tg3_poll()
7321 		tg3_poll_link(tp);  in tg3_poll()
7325 		if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))  in tg3_poll()
7331 		if (tg3_flag(tp, TAGGED_STATUS)) {  in tg3_poll()
7349 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1);  in tg3_poll()
7355 	tg3_reset_task_schedule(tp);  in tg3_poll()
7359 static void tg3_napi_disable(struct tg3 *tp)  in tg3_napi_disable()  argument
7363 	for (i = tp->irq_cnt - 1; i >= 0; i--)  in tg3_napi_disable()
7364 		napi_disable(&tp->napi[i].napi);  in tg3_napi_disable()
7367 static void tg3_napi_enable(struct tg3 *tp)  in tg3_napi_enable()  argument
7371 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_napi_enable()
7372 		napi_enable(&tp->napi[i].napi);  in tg3_napi_enable()
7375 static void tg3_napi_init(struct tg3 *tp)  in tg3_napi_init()  argument
7379 	netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll);  in tg3_napi_init()
7380 	for (i = 1; i < tp->irq_cnt; i++)  in tg3_napi_init()
7381 		netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix);  in tg3_napi_init()
7384 static void tg3_napi_fini(struct tg3 *tp)  in tg3_napi_fini()  argument
7388 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_napi_fini()
7389 		netif_napi_del(&tp->napi[i].napi);  in tg3_napi_fini()
7392 static inline void tg3_netif_stop(struct tg3 *tp)  in tg3_netif_stop()  argument
7394 	netif_trans_update(tp->dev);	/* prevent tx timeout */  in tg3_netif_stop()
7395 	tg3_napi_disable(tp);  in tg3_netif_stop()
7396 	netif_carrier_off(tp->dev);  in tg3_netif_stop()
7397 	netif_tx_disable(tp->dev);  in tg3_netif_stop()
7401 static inline void tg3_netif_start(struct tg3 *tp)  in tg3_netif_start()  argument
7403 	tg3_ptp_resume(tp);  in tg3_netif_start()
7409 	netif_tx_wake_all_queues(tp->dev);  in tg3_netif_start()
7411 	if (tp->link_up)  in tg3_netif_start()
7412 		netif_carrier_on(tp->dev);  in tg3_netif_start()
7414 	tg3_napi_enable(tp);  in tg3_netif_start()
7415 	tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;  in tg3_netif_start()
7416 	tg3_enable_ints(tp);  in tg3_netif_start()
7419 static void tg3_irq_quiesce(struct tg3 *tp)  in tg3_irq_quiesce()  argument
7420 	__releases(tp->lock)  in tg3_irq_quiesce()
7421 	__acquires(tp->lock)  in tg3_irq_quiesce()
7425 	BUG_ON(tp->irq_sync);  in tg3_irq_quiesce()
7427 	tp->irq_sync = 1;  in tg3_irq_quiesce()
7430 	spin_unlock_bh(&tp->lock);  in tg3_irq_quiesce()
7432 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_irq_quiesce()
7433 		synchronize_irq(tp->napi[i].irq_vec);  in tg3_irq_quiesce()
7435 	spin_lock_bh(&tp->lock);  in tg3_irq_quiesce()
7443 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)  in tg3_full_lock()  argument
7445 	spin_lock_bh(&tp->lock);  in tg3_full_lock()
7447 		tg3_irq_quiesce(tp);  in tg3_full_lock()
7450 static inline void tg3_full_unlock(struct tg3 *tp)  in tg3_full_unlock()  argument
7452 	spin_unlock_bh(&tp->lock);  in tg3_full_unlock()
7461 	struct tg3 *tp = tnapi->tp;  in tg3_msi_1shot()  local
7467 	if (likely(!tg3_irq_sync(tp)))  in tg3_msi_1shot()
7480 	struct tg3 *tp = tnapi->tp;  in tg3_msi()  local
7493 	if (likely(!tg3_irq_sync(tp)))  in tg3_msi()
7502 	struct tg3 *tp = tnapi->tp;  in tg3_interrupt()  local
7512 		if (tg3_flag(tp, CHIP_RESETTING) ||  in tg3_interrupt()
7531 	if (tg3_irq_sync(tp))  in tg3_interrupt()
7551 	struct tg3 *tp = tnapi->tp;  in tg3_interrupt_tagged()  local
7561 		if (tg3_flag(tp, CHIP_RESETTING) ||  in tg3_interrupt_tagged()
7589 	if (tg3_irq_sync(tp))  in tg3_interrupt_tagged()
7604 	struct tg3 *tp = tnapi->tp;  in tg3_test_isr()  local
7609 		tg3_disable_ints(tp);  in tg3_test_isr()
7619 	struct tg3 *tp = netdev_priv(dev);  in tg3_poll_controller()  local
7621 	if (tg3_irq_sync(tp))  in tg3_poll_controller()
7624 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_poll_controller()
7625 		tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);  in tg3_poll_controller()
7631 	struct tg3 *tp = netdev_priv(dev);  in tg3_tx_timeout()  local
7633 	if (netif_msg_tx_err(tp)) {  in tg3_tx_timeout()
7635 		tg3_dump_state(tp);  in tg3_tx_timeout()
7638 	tg3_reset_task_schedule(tp);  in tg3_tx_timeout()
7652 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,  in tg3_4g_tso_overflow_test()  argument
7655 	if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {  in tg3_4g_tso_overflow_test()
7664 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,  in tg3_40bit_overflow_test()  argument
7668 	if (tg3_flag(tp, 40BIT_DMA_BUG))  in tg3_40bit_overflow_test()
7690 	struct tg3 *tp = tnapi->tp;  in tg3_tx_frag_set()  local
7693 	if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)  in tg3_tx_frag_set()
7699 	if (tg3_4g_tso_overflow_test(tp, map, len, mss))  in tg3_tx_frag_set()
7702 	if (tg3_40bit_overflow_test(tp, map, len))  in tg3_tx_frag_set()
7705 	if (tp->dma_limit) {  in tg3_tx_frag_set()
7708 		while (len > tp->dma_limit && *budget) {  in tg3_tx_frag_set()
7709 			u32 frag_len = tp->dma_limit;  in tg3_tx_frag_set()
7710 			len -= tp->dma_limit;  in tg3_tx_frag_set()
7714 				len += tp->dma_limit / 2;  in tg3_tx_frag_set()
7715 				frag_len = tp->dma_limit / 2;  in tg3_tx_frag_set()
7758 	dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping),  in tg3_tx_skb_unmap()
7773 		dma_unmap_page(&tnapi->tp->pdev->dev,  in tg3_tx_skb_unmap()
7791 	struct tg3 *tp = tnapi->tp;  in tigon3_dma_hwbug_workaround()  local
7796 	if (tg3_asic_rev(tp) != ASIC_REV_5701)  in tigon3_dma_hwbug_workaround()
7810 		new_addr = dma_map_single(&tp->pdev->dev, new_skb->data,  in tigon3_dma_hwbug_workaround()
7813 		if (dma_mapping_error(&tp->pdev->dev, new_addr)) {  in tigon3_dma_hwbug_workaround()
7853 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,  in tg3_tso_bug()  argument
7875 	segs = skb_gso_segment(skb, tp->dev->features &  in tg3_tso_bug()
7882 		tg3_start_xmit(seg, tp->dev);  in tg3_tso_bug()
7894 	struct tg3 *tp = netdev_priv(dev);  in tg3_start_xmit()  local
7908 	tnapi = &tp->napi[skb_get_queue_mapping(skb)];  in tg3_start_xmit()
7909 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_start_xmit()
7951 				return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
7957 			    tg3_flag(tp, TSO_BUG)) {  in tg3_start_xmit()
7959 					return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
7974 		if (tg3_flag(tp, HW_TSO_1) ||  in tg3_start_xmit()
7975 		    tg3_flag(tp, HW_TSO_2) ||  in tg3_start_xmit()
7976 		    tg3_flag(tp, HW_TSO_3)) {  in tg3_start_xmit()
7984 		if (tg3_flag(tp, HW_TSO_3)) {  in tg3_start_xmit()
7989 		} else if (tg3_flag(tp, HW_TSO_2))  in tg3_start_xmit()
7991 		else if (tg3_flag(tp, HW_TSO_1) ||  in tg3_start_xmit()
7992 			 tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_start_xmit()
8020 	if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&  in tg3_start_xmit()
8030 	    tg3_flag(tp, TX_TSTAMP_EN)) {  in tg3_start_xmit()
8037 	mapping = dma_map_single(&tp->pdev->dev, skb->data, len,  in tg3_start_xmit()
8039 	if (dma_mapping_error(&tp->pdev->dev, mapping))  in tg3_start_xmit()
8048 	if (tg3_flag(tp, 5701_DMA_BUG))  in tg3_start_xmit()
8058 		if (!tg3_flag(tp, HW_TSO_1) &&  in tg3_start_xmit()
8059 		    !tg3_flag(tp, HW_TSO_2) &&  in tg3_start_xmit()
8060 		    !tg3_flag(tp, HW_TSO_3))  in tg3_start_xmit()
8071 			mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,  in tg3_start_xmit()
8077 			if (dma_mapping_error(&tp->pdev->dev, mapping))  in tg3_start_xmit()
8103 			return tg3_tso_bug(tp, tnapi, txq, skb);  in tg3_start_xmit()
8149 	tp->tx_dropped++;  in tg3_start_xmit()
8153 static void tg3_mac_loopback(struct tg3 *tp, bool enable)  in tg3_mac_loopback()  argument
8156 		tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |  in tg3_mac_loopback()
8159 		tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;  in tg3_mac_loopback()
8161 		if (!tg3_flag(tp, 5705_PLUS))  in tg3_mac_loopback()
8162 			tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_mac_loopback()
8164 		if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_mac_loopback()
8165 			tp->mac_mode |= MAC_MODE_PORT_MODE_MII;  in tg3_mac_loopback()
8167 			tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;  in tg3_mac_loopback()
8169 		tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;  in tg3_mac_loopback()
8171 		if (tg3_flag(tp, 5705_PLUS) ||  in tg3_mac_loopback()
8172 		    (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||  in tg3_mac_loopback()
8173 		    tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_mac_loopback()
8174 			tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;  in tg3_mac_loopback()
8177 	tw32(MAC_MODE, tp->mac_mode);  in tg3_mac_loopback()
8181 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)  in tg3_phy_lpbk_set()  argument
8185 	tg3_phy_toggle_apd(tp, false);  in tg3_phy_lpbk_set()
8186 	tg3_phy_toggle_automdix(tp, false);  in tg3_phy_lpbk_set()
8188 	if (extlpbk && tg3_phy_set_extloopbk(tp))  in tg3_phy_lpbk_set()
8200 		if (tp->phy_flags & TG3_PHYFLG_IS_FET) {  in tg3_phy_lpbk_set()
8210 		if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_phy_lpbk_set()
8211 			tg3_readphy(tp, MII_CTRL1000, &val);  in tg3_phy_lpbk_set()
8214 			tg3_writephy(tp, MII_CTRL1000, val);  in tg3_phy_lpbk_set()
8218 			tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);  in tg3_phy_lpbk_set()
8223 	tg3_writephy(tp, MII_BMCR, bmcr);  in tg3_phy_lpbk_set()
8226 	if (tp->phy_flags & TG3_PHYFLG_IS_FET)  in tg3_phy_lpbk_set()
8227 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_phy_lpbk_set()
8231 	if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in tg3_phy_lpbk_set()
8232 	    tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_phy_lpbk_set()
8233 		tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |  in tg3_phy_lpbk_set()
8238 		tg3_readphy(tp, MII_TG3_FET_PTEST, &val);  in tg3_phy_lpbk_set()
8242 	if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_phy_lpbk_set()
8243 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_phy_lpbk_set()
8246 		tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_phy_lpbk_set()
8249 	mac_mode = tp->mac_mode &  in tg3_phy_lpbk_set()
8256 	if (tg3_asic_rev(tp) == ASIC_REV_5700) {  in tg3_phy_lpbk_set()
8257 		u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;  in tg3_phy_lpbk_set()
8264 		tg3_writephy(tp, MII_TG3_EXT_CTRL,  in tg3_phy_lpbk_set()
8276 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_loopback()  local
8279 		if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)  in tg3_set_loopback()
8282 		spin_lock_bh(&tp->lock);  in tg3_set_loopback()
8283 		tg3_mac_loopback(tp, true);  in tg3_set_loopback()
8284 		netif_carrier_on(tp->dev);  in tg3_set_loopback()
8285 		spin_unlock_bh(&tp->lock);  in tg3_set_loopback()
8288 		if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))  in tg3_set_loopback()
8291 		spin_lock_bh(&tp->lock);  in tg3_set_loopback()
8292 		tg3_mac_loopback(tp, false);  in tg3_set_loopback()
8294 		tg3_setup_phy(tp, true);  in tg3_set_loopback()
8295 		spin_unlock_bh(&tp->lock);  in tg3_set_loopback()
8303 	struct tg3 *tp = netdev_priv(dev);  in tg3_fix_features()  local
8305 	if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))  in tg3_fix_features()
8321 static void tg3_rx_prodring_free(struct tg3 *tp,  in tg3_rx_prodring_free()  argument
8326 	if (tpr != &tp->napi[0].prodring) {  in tg3_rx_prodring_free()
8328 		     i = (i + 1) & tp->rx_std_ring_mask)  in tg3_rx_prodring_free()
8329 			tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],  in tg3_rx_prodring_free()
8330 					tp->rx_pkt_map_sz);  in tg3_rx_prodring_free()
8332 		if (tg3_flag(tp, JUMBO_CAPABLE)) {  in tg3_rx_prodring_free()
8335 			     i = (i + 1) & tp->rx_jmb_ring_mask) {  in tg3_rx_prodring_free()
8336 				tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],  in tg3_rx_prodring_free()
8344 	for (i = 0; i <= tp->rx_std_ring_mask; i++)  in tg3_rx_prodring_free()
8345 		tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],  in tg3_rx_prodring_free()
8346 				tp->rx_pkt_map_sz);  in tg3_rx_prodring_free()
8348 	if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {  in tg3_rx_prodring_free()
8349 		for (i = 0; i <= tp->rx_jmb_ring_mask; i++)  in tg3_rx_prodring_free()
8350 			tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],  in tg3_rx_prodring_free()
8362 static int tg3_rx_prodring_alloc(struct tg3 *tp,  in tg3_rx_prodring_alloc()  argument
8372 	if (tpr != &tp->napi[0].prodring) {  in tg3_rx_prodring_alloc()
8374 		       TG3_RX_STD_BUFF_RING_SIZE(tp));  in tg3_rx_prodring_alloc()
8377 			       TG3_RX_JMB_BUFF_RING_SIZE(tp));  in tg3_rx_prodring_alloc()
8382 	memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));  in tg3_rx_prodring_alloc()
8385 	if (tg3_flag(tp, 5780_CLASS) &&  in tg3_rx_prodring_alloc()
8386 	    tp->dev->mtu > ETH_DATA_LEN)  in tg3_rx_prodring_alloc()
8388 	tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);  in tg3_rx_prodring_alloc()
8394 	for (i = 0; i <= tp->rx_std_ring_mask; i++) {  in tg3_rx_prodring_alloc()
8405 	for (i = 0; i < tp->rx_pending; i++) {  in tg3_rx_prodring_alloc()
8408 		if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,  in tg3_rx_prodring_alloc()
8410 			netdev_warn(tp->dev,  in tg3_rx_prodring_alloc()
8413 				    "successfully\n", i, tp->rx_pending);  in tg3_rx_prodring_alloc()
8416 			tp->rx_pending = i;  in tg3_rx_prodring_alloc()
8421 	if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))  in tg3_rx_prodring_alloc()
8424 	memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));  in tg3_rx_prodring_alloc()
8426 	if (!tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_rx_prodring_alloc()
8429 	for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {  in tg3_rx_prodring_alloc()
8440 	for (i = 0; i < tp->rx_jumbo_pending; i++) {  in tg3_rx_prodring_alloc()
8443 		if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,  in tg3_rx_prodring_alloc()
8445 			netdev_warn(tp->dev,  in tg3_rx_prodring_alloc()
8448 				    "successfully\n", i, tp->rx_jumbo_pending);  in tg3_rx_prodring_alloc()
8451 			tp->rx_jumbo_pending = i;  in tg3_rx_prodring_alloc()
8460 	tg3_rx_prodring_free(tp, tpr);  in tg3_rx_prodring_alloc()
8464 static void tg3_rx_prodring_fini(struct tg3 *tp,  in tg3_rx_prodring_fini()  argument
8472 		dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),  in tg3_rx_prodring_fini()
8477 		dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),  in tg3_rx_prodring_fini()
8483 static int tg3_rx_prodring_init(struct tg3 *tp,  in tg3_rx_prodring_init()  argument
8486 	tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),  in tg3_rx_prodring_init()
8491 	tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,  in tg3_rx_prodring_init()
8492 					 TG3_RX_STD_RING_BYTES(tp),  in tg3_rx_prodring_init()
8498 	if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {  in tg3_rx_prodring_init()
8499 		tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),  in tg3_rx_prodring_init()
8504 		tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,  in tg3_rx_prodring_init()
8505 						 TG3_RX_JMB_RING_BYTES(tp),  in tg3_rx_prodring_init()
8515 	tg3_rx_prodring_fini(tp, tpr);  in tg3_rx_prodring_init()
8526 static void tg3_free_rings(struct tg3 *tp)  in tg3_free_rings()  argument
8530 	for (j = 0; j < tp->irq_cnt; j++) {  in tg3_free_rings()
8531 		struct tg3_napi *tnapi = &tp->napi[j];  in tg3_free_rings()
8533 		tg3_rx_prodring_free(tp, &tnapi->prodring);  in tg3_free_rings()
8549 		netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));  in tg3_free_rings()
8560 static int tg3_init_rings(struct tg3 *tp)  in tg3_init_rings()  argument
8565 	tg3_free_rings(tp);  in tg3_init_rings()
8567 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_init_rings()
8568 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_init_rings()
8583 			memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));  in tg3_init_rings()
8586 		    tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {  in tg3_init_rings()
8587 			tg3_free_rings(tp);  in tg3_init_rings()
8595 static void tg3_mem_tx_release(struct tg3 *tp)  in tg3_mem_tx_release()  argument
8599 	for (i = 0; i < tp->irq_max; i++) {  in tg3_mem_tx_release()
8600 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_tx_release()
8603 			dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,  in tg3_mem_tx_release()
8613 static int tg3_mem_tx_acquire(struct tg3 *tp)  in tg3_mem_tx_acquire()  argument
8616 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_mem_tx_acquire()
8621 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_mem_tx_acquire()
8624 	for (i = 0; i < tp->txq_cnt; i++, tnapi++) {  in tg3_mem_tx_acquire()
8631 		tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,  in tg3_mem_tx_acquire()
8642 	tg3_mem_tx_release(tp);  in tg3_mem_tx_acquire()
8646 static void tg3_mem_rx_release(struct tg3 *tp)  in tg3_mem_rx_release()  argument
8650 	for (i = 0; i < tp->irq_max; i++) {  in tg3_mem_rx_release()
8651 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_rx_release()
8653 		tg3_rx_prodring_fini(tp, &tnapi->prodring);  in tg3_mem_rx_release()
8658 		dma_free_coherent(&tp->pdev->dev,  in tg3_mem_rx_release()
8659 				  TG3_RX_RCB_RING_BYTES(tp),  in tg3_mem_rx_release()
8666 static int tg3_mem_rx_acquire(struct tg3 *tp)  in tg3_mem_rx_acquire()  argument
8670 	limit = tp->rxq_cnt;  in tg3_mem_rx_acquire()
8675 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_mem_rx_acquire()
8679 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_mem_rx_acquire()
8681 		if (tg3_rx_prodring_init(tp, &tnapi->prodring))  in tg3_mem_rx_acquire()
8688 		if (!i && tg3_flag(tp, ENABLE_RSS))  in tg3_mem_rx_acquire()
8691 		tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,  in tg3_mem_rx_acquire()
8692 						   TG3_RX_RCB_RING_BYTES(tp),  in tg3_mem_rx_acquire()
8702 	tg3_mem_rx_release(tp);  in tg3_mem_rx_acquire()
8710 static void tg3_free_consistent(struct tg3 *tp)  in tg3_free_consistent()  argument
8714 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_free_consistent()
8715 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_free_consistent()
8718 			dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,  in tg3_free_consistent()
8725 	tg3_mem_rx_release(tp);  in tg3_free_consistent()
8726 	tg3_mem_tx_release(tp);  in tg3_free_consistent()
8732 	if (tp->hw_stats) {  in tg3_free_consistent()
8733 		dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),  in tg3_free_consistent()
8734 				  tp->hw_stats, tp->stats_mapping);  in tg3_free_consistent()
8735 		tp->hw_stats = NULL;  in tg3_free_consistent()
8743 static int tg3_alloc_consistent(struct tg3 *tp)  in tg3_alloc_consistent()  argument
8747 	tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,  in tg3_alloc_consistent()
8749 					  &tp->stats_mapping, GFP_KERNEL);  in tg3_alloc_consistent()
8750 	if (!tp->hw_stats)  in tg3_alloc_consistent()
8753 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_alloc_consistent()
8754 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_alloc_consistent()
8757 		tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,  in tg3_alloc_consistent()
8766 		if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_alloc_consistent()
8795 	if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))  in tg3_alloc_consistent()
8801 	tg3_free_consistent(tp);  in tg3_alloc_consistent()
8810 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)  in tg3_stop_block()  argument
8815 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_stop_block()
8837 		if (pci_channel_offline(tp->pdev)) {  in tg3_stop_block()
8838 			dev_err(&tp->pdev->dev,  in tg3_stop_block()
8852 		dev_err(&tp->pdev->dev,  in tg3_stop_block()
8862 static int tg3_abort_hw(struct tg3 *tp, bool silent)  in tg3_abort_hw()  argument
8866 	tg3_disable_ints(tp);  in tg3_abort_hw()
8868 	if (pci_channel_offline(tp->pdev)) {  in tg3_abort_hw()
8869 		tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);  in tg3_abort_hw()
8870 		tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;  in tg3_abort_hw()
8875 	tp->rx_mode &= ~RX_MODE_ENABLE;  in tg3_abort_hw()
8876 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_abort_hw()
8879 	err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8880 	err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);  in tg3_abort_hw()
8881 	err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);  in tg3_abort_hw()
8882 	err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8883 	err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8884 	err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8886 	err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);  in tg3_abort_hw()
8887 	err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);  in tg3_abort_hw()
8888 	err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);  in tg3_abort_hw()
8889 	err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8890 	err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8891 	err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8892 	err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);  in tg3_abort_hw()
8894 	tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;  in tg3_abort_hw()
8895 	tw32_f(MAC_MODE, tp->mac_mode);  in tg3_abort_hw()
8898 	tp->tx_mode &= ~TX_MODE_ENABLE;  in tg3_abort_hw()
8899 	tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_abort_hw()
8907 		dev_err(&tp->pdev->dev,  in tg3_abort_hw()
8913 	err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);  in tg3_abort_hw()
8914 	err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);  in tg3_abort_hw()
8915 	err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);  in tg3_abort_hw()
8920 	err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);  in tg3_abort_hw()
8921 	err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);  in tg3_abort_hw()
8924 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_abort_hw()
8925 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_abort_hw()
8934 static void tg3_save_pci_state(struct tg3 *tp)  in tg3_save_pci_state()  argument
8936 	pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);  in tg3_save_pci_state()
8940 static void tg3_restore_pci_state(struct tg3 *tp)  in tg3_restore_pci_state()  argument
8945 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_restore_pci_state()
8946 			       tp->misc_host_ctrl);  in tg3_restore_pci_state()
8950 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&  in tg3_restore_pci_state()
8951 	    tg3_flag(tp, PCIX_MODE))  in tg3_restore_pci_state()
8954 	if (tg3_flag(tp, ENABLE_APE))  in tg3_restore_pci_state()
8958 	pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);  in tg3_restore_pci_state()
8960 	pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);  in tg3_restore_pci_state()
8962 	if (!tg3_flag(tp, PCI_EXPRESS)) {  in tg3_restore_pci_state()
8963 		pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,  in tg3_restore_pci_state()
8964 				      tp->pci_cacheline_sz);  in tg3_restore_pci_state()
8965 		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_restore_pci_state()
8966 				      tp->pci_lat_timer);  in tg3_restore_pci_state()
8970 	if (tg3_flag(tp, PCIX_MODE)) {  in tg3_restore_pci_state()
8973 		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_restore_pci_state()
8976 		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_restore_pci_state()
8980 	if (tg3_flag(tp, 5780_CLASS)) {  in tg3_restore_pci_state()
8985 		if (tg3_flag(tp, USING_MSI)) {  in tg3_restore_pci_state()
8988 			pci_read_config_word(tp->pdev,  in tg3_restore_pci_state()
8989 					     tp->msi_cap + PCI_MSI_FLAGS,  in tg3_restore_pci_state()
8991 			pci_write_config_word(tp->pdev,  in tg3_restore_pci_state()
8992 					      tp->msi_cap + PCI_MSI_FLAGS,  in tg3_restore_pci_state()
9000 static void tg3_override_clk(struct tg3 *tp)  in tg3_override_clk()  argument
9004 	switch (tg3_asic_rev(tp)) {  in tg3_override_clk()
9021 static void tg3_restore_clk(struct tg3 *tp)  in tg3_restore_clk()  argument
9025 	switch (tg3_asic_rev(tp)) {  in tg3_restore_clk()
9044 static int tg3_chip_reset(struct tg3 *tp)  in tg3_chip_reset()  argument
9045 	__releases(tp->lock)  in tg3_chip_reset()
9046 	__acquires(tp->lock)  in tg3_chip_reset()
9052 	if (!pci_device_is_present(tp->pdev))  in tg3_chip_reset()
9055 	tg3_nvram_lock(tp);  in tg3_chip_reset()
9057 	tg3_ape_lock(tp, TG3_APE_LOCK_GRC);  in tg3_chip_reset()
9062 	tp->nvram_lock_cnt = 0;  in tg3_chip_reset()
9068 	tg3_save_pci_state(tp);  in tg3_chip_reset()
9070 	if (tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_chip_reset()
9071 	    tg3_flag(tp, 5755_PLUS))  in tg3_chip_reset()
9080 	write_op = tp->write32;  in tg3_chip_reset()
9082 		tp->write32 = tg3_write32;  in tg3_chip_reset()
9090 	tg3_flag_set(tp, CHIP_RESETTING);  in tg3_chip_reset()
9091 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_chip_reset()
9092 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_chip_reset()
9102 	tg3_full_unlock(tp);  in tg3_chip_reset()
9104 	for (i = 0; i < tp->irq_cnt; i++)  in tg3_chip_reset()
9105 		synchronize_irq(tp->napi[i].irq_vec);  in tg3_chip_reset()
9107 	tg3_full_lock(tp, 0);  in tg3_chip_reset()
9109 	if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_chip_reset()
9117 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_chip_reset()
9119 		if (tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_chip_reset()
9120 		    !tg3_flag(tp, 57765_PLUS) &&  in tg3_chip_reset()
9125 		if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {  in tg3_chip_reset()
9131 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_chip_reset()
9142 	tg3_override_clk(tp);  in tg3_chip_reset()
9145 	if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))  in tg3_chip_reset()
9151 	tp->write32 = write_op;  in tg3_chip_reset()
9174 	pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);  in tg3_chip_reset()
9178 	if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {  in tg3_chip_reset()
9181 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {  in tg3_chip_reset()
9189 			pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);  in tg3_chip_reset()
9190 			pci_write_config_dword(tp->pdev, 0xc4,  in tg3_chip_reset()
9200 		if (!tg3_flag(tp, CPMU_PRESENT))  in tg3_chip_reset()
9202 		pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);  in tg3_chip_reset()
9205 		pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,  in tg3_chip_reset()
9212 	tg3_restore_pci_state(tp);  in tg3_chip_reset()
9214 	tg3_flag_clear(tp, CHIP_RESETTING);  in tg3_chip_reset()
9215 	tg3_flag_clear(tp, ERROR_PROCESSED);  in tg3_chip_reset()
9218 	if (tg3_flag(tp, 5780_CLASS))  in tg3_chip_reset()
9222 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {  in tg3_chip_reset()
9223 		tg3_stop_fw(tp);  in tg3_chip_reset()
9227 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_chip_reset()
9233 		tg3_stop_fw(tp);  in tg3_chip_reset()
9234 		tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_chip_reset()
9237 	err = tg3_poll_fw(tp);  in tg3_chip_reset()
9241 	tw32(GRC_MODE, tp->grc_mode);  in tg3_chip_reset()
9243 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {  in tg3_chip_reset()
9249 	if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&  in tg3_chip_reset()
9250 	    tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_chip_reset()
9251 		tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;  in tg3_chip_reset()
9252 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)  in tg3_chip_reset()
9253 			tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;  in tg3_chip_reset()
9254 		tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);  in tg3_chip_reset()
9257 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_chip_reset()
9258 		tp->mac_mode = MAC_MODE_PORT_MODE_TBI;  in tg3_chip_reset()
9259 		val = tp->mac_mode;  in tg3_chip_reset()
9260 	} else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {  in tg3_chip_reset()
9261 		tp->mac_mode = MAC_MODE_PORT_MODE_GMII;  in tg3_chip_reset()
9262 		val = tp->mac_mode;  in tg3_chip_reset()
9269 	tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);  in tg3_chip_reset()
9271 	tg3_mdio_start(tp);  in tg3_chip_reset()
9273 	if (tg3_flag(tp, PCI_EXPRESS) &&  in tg3_chip_reset()
9274 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&  in tg3_chip_reset()
9275 	    tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_chip_reset()
9276 	    !tg3_flag(tp, 57765_PLUS)) {  in tg3_chip_reset()
9282 	tg3_restore_clk(tp);  in tg3_chip_reset()
9287 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_chip_reset()
9294 	tg3_flag_clear(tp, ENABLE_ASF);  in tg3_chip_reset()
9295 	tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |  in tg3_chip_reset()
9298 	tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);  in tg3_chip_reset()
9299 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);  in tg3_chip_reset()
9303 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);  in tg3_chip_reset()
9305 			tg3_flag_set(tp, ENABLE_ASF);  in tg3_chip_reset()
9306 			tp->last_event_jiffies = jiffies;  in tg3_chip_reset()
9307 			if (tg3_flag(tp, 5750_PLUS))  in tg3_chip_reset()
9308 				tg3_flag_set(tp, ASF_NEW_HANDSHAKE);  in tg3_chip_reset()
9310 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);  in tg3_chip_reset()
9312 				tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;  in tg3_chip_reset()
9314 				tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;  in tg3_chip_reset()
9326 static int tg3_halt(struct tg3 *tp, int kind, bool silent)  in tg3_halt()  argument
9330 	tg3_stop_fw(tp);  in tg3_halt()
9332 	tg3_write_sig_pre_reset(tp, kind);  in tg3_halt()
9334 	tg3_abort_hw(tp, silent);  in tg3_halt()
9335 	err = tg3_chip_reset(tp);  in tg3_halt()
9337 	__tg3_set_mac_addr(tp, false);  in tg3_halt()
9339 	tg3_write_sig_legacy(tp, kind);  in tg3_halt()
9340 	tg3_write_sig_post_reset(tp, kind);  in tg3_halt()
9342 	if (tp->hw_stats) {  in tg3_halt()
9344 		tg3_get_nstats(tp, &tp->net_stats_prev);  in tg3_halt()
9345 		tg3_get_estats(tp, &tp->estats_prev);  in tg3_halt()
9348 		memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));  in tg3_halt()
9356 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_mac_addr()  local
9369 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_set_mac_addr()
9382 	spin_lock_bh(&tp->lock);  in tg3_set_mac_addr()
9383 	__tg3_set_mac_addr(tp, skip_mac_1);  in tg3_set_mac_addr()
9385 	spin_unlock_bh(&tp->lock);  in tg3_set_mac_addr()
9391 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,  in tg3_set_bdinfo()  argument
9395 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9398 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9401 	tg3_write_mem(tp,  in tg3_set_bdinfo()
9405 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_set_bdinfo()
9406 		tg3_write_mem(tp,  in tg3_set_bdinfo()
9412 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)  in tg3_coal_tx_init()  argument
9416 	if (!tg3_flag(tp, ENABLE_TSS)) {  in tg3_coal_tx_init()
9425 		for (; i < tp->txq_cnt; i++) {  in tg3_coal_tx_init()
9437 	for (; i < tp->irq_max - 1; i++) {  in tg3_coal_tx_init()
9444 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)  in tg3_coal_rx_init()  argument
9447 	u32 limit = tp->rxq_cnt;  in tg3_coal_rx_init()
9449 	if (!tg3_flag(tp, ENABLE_RSS)) {  in tg3_coal_rx_init()
9471 	for (; i < tp->irq_max - 1; i++) {  in tg3_coal_rx_init()
9478 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)  in __tg3_set_coalesce()  argument
9480 	tg3_coal_tx_init(tp, ec);  in __tg3_set_coalesce()
9481 	tg3_coal_rx_init(tp, ec);  in __tg3_set_coalesce()
9483 	if (!tg3_flag(tp, 5705_PLUS)) {  in __tg3_set_coalesce()
9489 		if (!tp->link_up)  in __tg3_set_coalesce()
9497 static void tg3_tx_rcbs_disable(struct tg3 *tp)  in tg3_tx_rcbs_disable()  argument
9502 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_tx_rcbs_disable()
9504 	else if (tg3_flag(tp, 5717_PLUS))  in tg3_tx_rcbs_disable()
9506 	else if (tg3_flag(tp, 57765_CLASS) ||  in tg3_tx_rcbs_disable()
9507 		 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_tx_rcbs_disable()
9514 		tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,  in tg3_tx_rcbs_disable()
9519 static void tg3_tx_rcbs_init(struct tg3 *tp)  in tg3_tx_rcbs_init()  argument
9524 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_tx_rcbs_init()
9527 	for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {  in tg3_tx_rcbs_init()
9528 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_tx_rcbs_init()
9533 		tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,  in tg3_tx_rcbs_init()
9540 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)  in tg3_rx_ret_rcbs_disable()  argument
9545 	if (tg3_flag(tp, 5717_PLUS))  in tg3_rx_ret_rcbs_disable()
9547 	else if (!tg3_flag(tp, 5705_PLUS))  in tg3_rx_ret_rcbs_disable()
9549 	else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_rx_ret_rcbs_disable()
9550 		 tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_rx_ret_rcbs_disable()
9551 		 tg3_flag(tp, 57765_CLASS))  in tg3_rx_ret_rcbs_disable()
9558 		tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,  in tg3_rx_ret_rcbs_disable()
9563 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)  in tg3_rx_ret_rcbs_init()  argument
9568 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_rx_ret_rcbs_init()
9571 	for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {  in tg3_rx_ret_rcbs_init()
9572 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_rx_ret_rcbs_init()
9577 		tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,  in tg3_rx_ret_rcbs_init()
9578 			       (tp->rx_ret_ring_mask + 1) <<  in tg3_rx_ret_rcbs_init()
9584 static void tg3_rings_reset(struct tg3 *tp)  in tg3_rings_reset()  argument
9588 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_rings_reset()
9590 	tg3_tx_rcbs_disable(tp);  in tg3_rings_reset()
9592 	tg3_rx_ret_rcbs_disable(tp);  in tg3_rings_reset()
9595 	tw32_mailbox_f(tp->napi[0].int_mbox, 1);  in tg3_rings_reset()
9596 	tp->napi[0].chk_msi_cnt = 0;  in tg3_rings_reset()
9597 	tp->napi[0].last_rx_cons = 0;  in tg3_rings_reset()
9598 	tp->napi[0].last_tx_cons = 0;  in tg3_rings_reset()
9601 	if (tg3_flag(tp, SUPPORT_MSIX)) {  in tg3_rings_reset()
9602 		for (i = 1; i < tp->irq_max; i++) {  in tg3_rings_reset()
9603 			tp->napi[i].tx_prod = 0;  in tg3_rings_reset()
9604 			tp->napi[i].tx_cons = 0;  in tg3_rings_reset()
9605 			if (tg3_flag(tp, ENABLE_TSS))  in tg3_rings_reset()
9606 				tw32_mailbox(tp->napi[i].prodmbox, 0);  in tg3_rings_reset()
9607 			tw32_rx_mbox(tp->napi[i].consmbox, 0);  in tg3_rings_reset()
9608 			tw32_mailbox_f(tp->napi[i].int_mbox, 1);  in tg3_rings_reset()
9609 			tp->napi[i].chk_msi_cnt = 0;  in tg3_rings_reset()
9610 			tp->napi[i].last_rx_cons = 0;  in tg3_rings_reset()
9611 			tp->napi[i].last_tx_cons = 0;  in tg3_rings_reset()
9613 		if (!tg3_flag(tp, ENABLE_TSS))  in tg3_rings_reset()
9614 			tw32_mailbox(tp->napi[0].prodmbox, 0);  in tg3_rings_reset()
9616 		tp->napi[0].tx_prod = 0;  in tg3_rings_reset()
9617 		tp->napi[0].tx_cons = 0;  in tg3_rings_reset()
9618 		tw32_mailbox(tp->napi[0].prodmbox, 0);  in tg3_rings_reset()
9619 		tw32_rx_mbox(tp->napi[0].consmbox, 0);  in tg3_rings_reset()
9623 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_rings_reset()
9640 	for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {  in tg3_rings_reset()
9650 	tg3_tx_rcbs_init(tp);  in tg3_rings_reset()
9651 	tg3_rx_ret_rcbs_init(tp);  in tg3_rings_reset()
9654 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)  in tg3_setup_rxbd_thresholds()  argument
9658 	if (!tg3_flag(tp, 5750_PLUS) ||  in tg3_setup_rxbd_thresholds()
9659 	    tg3_flag(tp, 5780_CLASS) ||  in tg3_setup_rxbd_thresholds()
9660 	    tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_setup_rxbd_thresholds()
9661 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_setup_rxbd_thresholds()
9662 	    tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9664 	else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_setup_rxbd_thresholds()
9665 		 tg3_asic_rev(tp) == ASIC_REV_5787)  in tg3_setup_rxbd_thresholds()
9670 	nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);  in tg3_setup_rxbd_thresholds()
9671 	host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);  in tg3_setup_rxbd_thresholds()
9676 	if (tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9679 	if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))  in tg3_setup_rxbd_thresholds()
9684 	host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);  in tg3_setup_rxbd_thresholds()
9689 	if (tg3_flag(tp, 57765_PLUS))  in tg3_setup_rxbd_thresholds()
9717 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)  in tg3_set_multi()  argument
9728 	struct tg3 *tp = netdev_priv(dev);  in __tg3_set_rx_mode()  local
9731 	rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |  in __tg3_set_rx_mode()
9738 	if (!tg3_flag(tp, ENABLE_ASF))  in __tg3_set_rx_mode()
9747 		tg3_set_multi(tp, 1);  in __tg3_set_rx_mode()
9750 		tg3_set_multi(tp, 0);  in __tg3_set_rx_mode()
9773 	if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {  in __tg3_set_rx_mode()
9781 			__tg3_set_one_mac_addr(tp, ha->addr,  in __tg3_set_rx_mode()
9782 					       i + TG3_UCAST_ADDR_IDX(tp));  in __tg3_set_rx_mode()
9787 	if (rx_mode != tp->rx_mode) {  in __tg3_set_rx_mode()
9788 		tp->rx_mode = rx_mode;  in __tg3_set_rx_mode()
9794 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)  in tg3_rss_init_dflt_indir_tbl()  argument
9799 		tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);  in tg3_rss_init_dflt_indir_tbl()
9802 static void tg3_rss_check_indir_tbl(struct tg3 *tp)  in tg3_rss_check_indir_tbl()  argument
9806 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_rss_check_indir_tbl()
9809 	if (tp->rxq_cnt == 1) {  in tg3_rss_check_indir_tbl()
9810 		memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));  in tg3_rss_check_indir_tbl()
9816 		if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)  in tg3_rss_check_indir_tbl()
9821 		tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);  in tg3_rss_check_indir_tbl()
9824 static void tg3_rss_write_indir_tbl(struct tg3 *tp)  in tg3_rss_write_indir_tbl()  argument
9830 		u32 val = tp->rss_ind_tbl[i];  in tg3_rss_write_indir_tbl()
9834 			val |= tp->rss_ind_tbl[i];  in tg3_rss_write_indir_tbl()
9841 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)  in tg3_lso_rd_dma_workaround_bit()  argument
9843 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_lso_rd_dma_workaround_bit()
9850 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)  in tg3_reset_hw()  argument
9854 	struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;  in tg3_reset_hw()
9856 	tg3_disable_ints(tp);  in tg3_reset_hw()
9858 	tg3_stop_fw(tp);  in tg3_reset_hw()
9860 	tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);  in tg3_reset_hw()
9862 	if (tg3_flag(tp, INIT_COMPLETE))  in tg3_reset_hw()
9863 		tg3_abort_hw(tp, 1);  in tg3_reset_hw()
9865 	if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_reset_hw()
9866 	    !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {  in tg3_reset_hw()
9867 		tg3_phy_pull_config(tp);  in tg3_reset_hw()
9868 		tg3_eee_pull_config(tp, NULL);  in tg3_reset_hw()
9869 		tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_reset_hw()
9873 	if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)  in tg3_reset_hw()
9874 		tg3_setup_eee(tp);  in tg3_reset_hw()
9877 		tg3_phy_reset(tp);  in tg3_reset_hw()
9879 	err = tg3_chip_reset(tp);  in tg3_reset_hw()
9883 	tg3_write_sig_legacy(tp, RESET_KIND_INIT);  in tg3_reset_hw()
9885 	if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {  in tg3_reset_hw()
9906 	if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_reset_hw()
9921 	if (tg3_flag(tp, L1PLLPD_EN)) {  in tg3_reset_hw()
9935 	if (tg3_flag(tp, 57765_CLASS)) {  in tg3_reset_hw()
9936 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {  in tg3_reset_hw()
9951 		if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {  in tg3_reset_hw()
9985 	if (!tg3_flag(tp, CPMU_PRESENT)) {  in tg3_reset_hw()
9986 		if (!tg3_flag(tp, PCI_EXPRESS))  in tg3_reset_hw()
9987 			tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;  in tg3_reset_hw()
9988 		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);  in tg3_reset_hw()
9991 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&  in tg3_reset_hw()
9992 	    tg3_flag(tp, PCIX_MODE)) {  in tg3_reset_hw()
9998 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_reset_hw()
10009 	if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {  in tg3_reset_hw()
10021 	err = tg3_init_rings(tp);  in tg3_reset_hw()
10025 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10028 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)  in tg3_reset_hw()
10030 		if (!tg3_flag(tp, 57765_CLASS) &&  in tg3_reset_hw()
10031 		    tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_reset_hw()
10032 		    tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_reset_hw()
10034 		tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);  in tg3_reset_hw()
10035 	} else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&  in tg3_reset_hw()
10036 		   tg3_asic_rev(tp) != ASIC_REV_5761) {  in tg3_reset_hw()
10040 		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_reset_hw()
10043 	tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |  in tg3_reset_hw()
10047 	tp->grc_mode |= GRC_MODE_HOST_SENDBDS;  in tg3_reset_hw()
10055 	tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;  in tg3_reset_hw()
10058 	if (tp->rxptpctl)  in tg3_reset_hw()
10060 		     tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);  in tg3_reset_hw()
10062 	if (tg3_flag(tp, PTP_CAPABLE))  in tg3_reset_hw()
10065 	tw32(GRC_MODE, tp->grc_mode | val);  in tg3_reset_hw()
10071 	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&  in tg3_reset_hw()
10072 	    tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) {  in tg3_reset_hw()
10084 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_reset_hw()
10086 	} else if (tg3_asic_rev(tp) != ASIC_REV_5705) {  in tg3_reset_hw()
10088 		if (tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_reset_hw()
10094 	} else if (tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10097 		fw_len = tp->fw_len;  in tg3_reset_hw()
10105 	if (tp->dev->mtu <= ETH_DATA_LEN) {  in tg3_reset_hw()
10107 		     tp->bufmgr_config.mbuf_read_dma_low_water);  in tg3_reset_hw()
10109 		     tp->bufmgr_config.mbuf_mac_rx_low_water);  in tg3_reset_hw()
10111 		     tp->bufmgr_config.mbuf_high_water);  in tg3_reset_hw()
10114 		     tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);  in tg3_reset_hw()
10116 		     tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);  in tg3_reset_hw()
10118 		     tp->bufmgr_config.mbuf_high_water_jumbo);  in tg3_reset_hw()
10121 	     tp->bufmgr_config.dma_low_water);  in tg3_reset_hw()
10123 	     tp->bufmgr_config.dma_high_water);  in tg3_reset_hw()
10126 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_reset_hw()
10128 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_reset_hw()
10129 	    tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_reset_hw()
10130 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10131 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)  in tg3_reset_hw()
10140 		netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);  in tg3_reset_hw()
10144 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)  in tg3_reset_hw()
10147 	tg3_setup_rxbd_thresholds(tp);  in tg3_reset_hw()
10170 	if (!tg3_flag(tp, 5717_PLUS))  in tg3_reset_hw()
10175 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10182 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10183 	    (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {  in tg3_reset_hw()
10185 		if (tg3_flag(tp, JUMBO_RING_ENABLE)) {  in tg3_reset_hw()
10190 			val = TG3_RX_JMB_RING_SIZE(tp) <<  in tg3_reset_hw()
10194 			if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||  in tg3_reset_hw()
10195 			    tg3_flag(tp, 57765_CLASS) ||  in tg3_reset_hw()
10196 			    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10204 		if (tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10205 			val = TG3_RX_STD_RING_SIZE(tp);  in tg3_reset_hw()
10215 	tpr->rx_std_prod_idx = tp->rx_pending;  in tg3_reset_hw()
10219 		tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;  in tg3_reset_hw()
10222 	tg3_rings_reset(tp);  in tg3_reset_hw()
10225 	__tg3_set_mac_addr(tp, false);  in tg3_reset_hw()
10229 	     tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);  in tg3_reset_hw()
10238 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10239 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10259 	if (tg3_asic_rev(tp) == ASIC_REV_5717)  in tg3_reset_hw()
10262 	if (tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_reset_hw()
10263 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10264 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_reset_hw()
10269 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_reset_hw()
10270 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_reset_hw()
10271 		if (tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10274 			   !tg3_flag(tp, IS_5788)) {  in tg3_reset_hw()
10279 	if (tg3_flag(tp, PCI_EXPRESS))  in tg3_reset_hw()
10282 	if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_reset_hw()
10283 		tp->dma_limit = 0;  in tg3_reset_hw()
10284 		if (tp->dev->mtu <= ETH_DATA_LEN) {  in tg3_reset_hw()
10286 			tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;  in tg3_reset_hw()
10290 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_reset_hw()
10291 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_reset_hw()
10292 	    tg3_flag(tp, HW_TSO_3))  in tg3_reset_hw()
10295 	if (tg3_flag(tp, 57765_PLUS) ||  in tg3_reset_hw()
10296 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10297 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_reset_hw()
10300 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10301 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10304 	if (tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_reset_hw()
10305 	    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_reset_hw()
10306 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_reset_hw()
10307 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_reset_hw()
10308 	    tg3_flag(tp, 57765_PLUS)) {  in tg3_reset_hw()
10311 		if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10317 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_reset_hw()
10318 		    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10329 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_reset_hw()
10330 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10331 	    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10334 		if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10346 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_reset_hw()
10351 		   tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10372 	__tg3_set_coalesce(tp, &tp->coal);  in tg3_reset_hw()
10374 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_reset_hw()
10380 		     ((u64) tp->stats_mapping >> 32));  in tg3_reset_hw()
10382 		     ((u64) tp->stats_mapping & 0xffffffff));  in tg3_reset_hw()
10391 			tg3_write_mem(tp, i, 0);  in tg3_reset_hw()
10396 	tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);  in tg3_reset_hw()
10400 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10403 	if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {  in tg3_reset_hw()
10404 		tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;  in tg3_reset_hw()
10410 	tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |  in tg3_reset_hw()
10413 	if (tg3_flag(tp, ENABLE_APE))  in tg3_reset_hw()
10414 		tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;  in tg3_reset_hw()
10415 	if (!tg3_flag(tp, 5705_PLUS) &&  in tg3_reset_hw()
10416 	    !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_reset_hw()
10417 	    tg3_asic_rev(tp) != ASIC_REV_5700)  in tg3_reset_hw()
10418 		tp->mac_mode |= MAC_MODE_LINK_POLARITY;  in tg3_reset_hw()
10419 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);  in tg3_reset_hw()
10428 	if (!tg3_flag(tp, IS_NIC)) {  in tg3_reset_hw()
10435 		if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_reset_hw()
10439 		if (tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_reset_hw()
10442 		tp->grc_local_ctrl &= ~gpio_mask;  in tg3_reset_hw()
10443 		tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;  in tg3_reset_hw()
10446 		if (tg3_flag(tp, EEPROM_WRITE_PROT))  in tg3_reset_hw()
10447 			tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |  in tg3_reset_hw()
10450 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_reset_hw()
10453 	if (tg3_flag(tp, USING_MSIX)) {  in tg3_reset_hw()
10456 		if (tp->irq_cnt > 1)  in tg3_reset_hw()
10458 		if (!tg3_flag(tp, 1SHOT_MSI))  in tg3_reset_hw()
10463 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_reset_hw()
10474 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_reset_hw()
10475 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_reset_hw()
10476 		if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_reset_hw()
10477 		    (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||  in tg3_reset_hw()
10478 		     tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {  in tg3_reset_hw()
10481 			   !tg3_flag(tp, IS_5788)) {  in tg3_reset_hw()
10487 	if (tg3_flag(tp, 5755_PLUS))  in tg3_reset_hw()
10490 	if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_reset_hw()
10496 	if (tg3_flag(tp, PCIX_MODE)) {  in tg3_reset_hw()
10499 		pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_reset_hw()
10501 		if (tg3_asic_rev(tp) == ASIC_REV_5703) {  in tg3_reset_hw()
10504 		} else if (tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_reset_hw()
10508 		pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,  in tg3_reset_hw()
10515 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_reset_hw()
10516 	    tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_reset_hw()
10518 			if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))  in tg3_reset_hw()
10523 			val |= tg3_lso_rd_dma_workaround_bit(tp);  in tg3_reset_hw()
10525 			tg3_flag_set(tp, 5719_5720_RDMA_BUG);  in tg3_reset_hw()
10530 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_reset_hw()
10533 	if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_reset_hw()
10542 	if (tg3_flag(tp, LRG_PROD_RING_CAP))  in tg3_reset_hw()
10546 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_reset_hw()
10547 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_reset_hw()
10548 	    tg3_flag(tp, HW_TSO_3))  in tg3_reset_hw()
10551 	if (tg3_flag(tp, ENABLE_TSS))  in tg3_reset_hw()
10556 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {  in tg3_reset_hw()
10557 		err = tg3_load_5701_a0_firmware_fix(tp);  in tg3_reset_hw()
10562 	if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_reset_hw()
10566 		tg3_load_57766_firmware(tp);  in tg3_reset_hw()
10569 	if (tg3_flag(tp, TSO_CAPABLE)) {  in tg3_reset_hw()
10570 		err = tg3_load_tso_firmware(tp);  in tg3_reset_hw()
10575 	tp->tx_mode = TX_MODE_ENABLE;  in tg3_reset_hw()
10577 	if (tg3_flag(tp, 5755_PLUS) ||  in tg3_reset_hw()
10578 	    tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_reset_hw()
10579 		tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;  in tg3_reset_hw()
10581 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_reset_hw()
10582 	    tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_reset_hw()
10584 		tp->tx_mode &= ~val;  in tg3_reset_hw()
10585 		tp->tx_mode |= tr32(MAC_TX_MODE) & val;  in tg3_reset_hw()
10588 	tw32_f(MAC_TX_MODE, tp->tx_mode);  in tg3_reset_hw()
10591 	if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_reset_hw()
10594 		tg3_rss_write_indir_tbl(tp);  in tg3_reset_hw()
10602 	tp->rx_mode = RX_MODE_ENABLE;  in tg3_reset_hw()
10603 	if (tg3_flag(tp, 5755_PLUS))  in tg3_reset_hw()
10604 		tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;  in tg3_reset_hw()
10606 	if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_reset_hw()
10607 		tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;  in tg3_reset_hw()
10609 	if (tg3_flag(tp, ENABLE_RSS))  in tg3_reset_hw()
10610 		tp->rx_mode |= RX_MODE_RSS_ENABLE |  in tg3_reset_hw()
10617 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_reset_hw()
10620 	tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_reset_hw()
10623 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_reset_hw()
10627 	tw32_f(MAC_RX_MODE, tp->rx_mode);  in tg3_reset_hw()
10630 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_reset_hw()
10631 		if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&  in tg3_reset_hw()
10632 		    !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {  in tg3_reset_hw()
10640 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)  in tg3_reset_hw()
10647 	if (tg3_flag(tp, 57765_CLASS))  in tg3_reset_hw()
10653 	if (tg3_asic_rev(tp) == ASIC_REV_5704 &&  in tg3_reset_hw()
10654 	    (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_reset_hw()
10656 		tg3_flag_set(tp, HW_AUTONEG);  in tg3_reset_hw()
10659 	if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_reset_hw()
10660 	    tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_reset_hw()
10665 		tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;  in tg3_reset_hw()
10666 		tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;  in tg3_reset_hw()
10667 		tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);  in tg3_reset_hw()
10670 	if (!tg3_flag(tp, USE_PHYLIB)) {  in tg3_reset_hw()
10671 		if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_reset_hw()
10672 			tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;  in tg3_reset_hw()
10674 		err = tg3_setup_phy(tp, false);  in tg3_reset_hw()
10678 		if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_reset_hw()
10679 		    !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {  in tg3_reset_hw()
10683 			if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {  in tg3_reset_hw()
10684 				tg3_writephy(tp, MII_TG3_TEST1,  in tg3_reset_hw()
10686 				tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);  in tg3_reset_hw()
10691 	__tg3_set_rx_mode(tp->dev);  in tg3_reset_hw()
10699 	if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))  in tg3_reset_hw()
10703 	if (tg3_flag(tp, ENABLE_ASF))  in tg3_reset_hw()
10753 	if (tg3_flag(tp, ENABLE_APE))  in tg3_reset_hw()
10755 		tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,  in tg3_reset_hw()
10758 	tg3_write_sig_post_reset(tp, RESET_KIND_INIT);  in tg3_reset_hw()
10766 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)  in tg3_init_hw()  argument
10772 	tg3_enable_register_access(tp);  in tg3_init_hw()
10773 	tg3_poll_fw(tp);  in tg3_init_hw()
10775 	tg3_switch_clocks(tp);  in tg3_init_hw()
10779 	return tg3_reset_hw(tp, reset_phy);  in tg3_init_hw()
10783 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)  in tg3_sd_scan_scratchpad()  argument
10789 		tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);  in tg3_sd_scan_scratchpad()
10802 	struct tg3 *tp = dev_get_drvdata(dev);  in tg3_show_temp()  local
10805 	spin_lock_bh(&tp->lock);  in tg3_show_temp()
10806 	tg3_ape_scratchpad_read(tp, &temperature, attr->index,  in tg3_show_temp()
10808 	spin_unlock_bh(&tp->lock);  in tg3_show_temp()
10828 static void tg3_hwmon_close(struct tg3 *tp)  in tg3_hwmon_close()  argument
10830 	if (tp->hwmon_dev) {  in tg3_hwmon_close()
10831 		hwmon_device_unregister(tp->hwmon_dev);  in tg3_hwmon_close()
10832 		tp->hwmon_dev = NULL;  in tg3_hwmon_close()
10836 static void tg3_hwmon_open(struct tg3 *tp)  in tg3_hwmon_open()  argument
10840 	struct pci_dev *pdev = tp->pdev;  in tg3_hwmon_open()
10843 	tg3_sd_scan_scratchpad(tp, ocirs);  in tg3_hwmon_open()
10856 	tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",  in tg3_hwmon_open()
10857 							  tp, tg3_groups);  in tg3_hwmon_open()
10858 	if (IS_ERR(tp->hwmon_dev)) {  in tg3_hwmon_open()
10859 		tp->hwmon_dev = NULL;  in tg3_hwmon_open()
10864 static inline void tg3_hwmon_close(struct tg3 *tp) { }  in tg3_hwmon_close()  argument
10865 static inline void tg3_hwmon_open(struct tg3 *tp) { }  in tg3_hwmon_open()  argument
10876 static void tg3_periodic_fetch_stats(struct tg3 *tp)  in tg3_periodic_fetch_stats()  argument
10878 	struct tg3_hw_stats *sp = tp->hw_stats;  in tg3_periodic_fetch_stats()
10880 	if (!tp->link_up)  in tg3_periodic_fetch_stats()
10896 	if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&  in tg3_periodic_fetch_stats()
10902 		val &= ~tg3_lso_rd_dma_workaround_bit(tp);  in tg3_periodic_fetch_stats()
10904 		tg3_flag_clear(tp, 5719_5720_RDMA_BUG);  in tg3_periodic_fetch_stats()
10923 	if (tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_periodic_fetch_stats()
10924 	    tg3_asic_rev(tp) != ASIC_REV_5762 &&  in tg3_periodic_fetch_stats()
10925 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&  in tg3_periodic_fetch_stats()
10926 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {  in tg3_periodic_fetch_stats()
10942 static void tg3_chk_missed_msi(struct tg3 *tp)  in tg3_chk_missed_msi()  argument
10946 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_chk_missed_msi()
10947 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_chk_missed_msi()
10967 	struct tg3 *tp = from_timer(tp, t, timer);  in tg3_timer()  local
10969 	spin_lock(&tp->lock);  in tg3_timer()
10971 	if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {  in tg3_timer()
10972 		spin_unlock(&tp->lock);  in tg3_timer()
10976 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_timer()
10977 	    tg3_flag(tp, 57765_CLASS))  in tg3_timer()
10978 		tg3_chk_missed_msi(tp);  in tg3_timer()
10980 	if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {  in tg3_timer()
10985 	if (!tg3_flag(tp, TAGGED_STATUS)) {  in tg3_timer()
10990 		if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {  in tg3_timer()
10992 			     tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);  in tg3_timer()
10994 			tw32(HOSTCC_MODE, tp->coalesce_mode |  in tg3_timer()
10999 			spin_unlock(&tp->lock);  in tg3_timer()
11000 			tg3_reset_task_schedule(tp);  in tg3_timer()
11006 	if (!--tp->timer_counter) {  in tg3_timer()
11007 		if (tg3_flag(tp, 5705_PLUS))  in tg3_timer()
11008 			tg3_periodic_fetch_stats(tp);  in tg3_timer()
11010 		if (tp->setlpicnt && !--tp->setlpicnt)  in tg3_timer()
11011 			tg3_phy_eee_enable(tp);  in tg3_timer()
11013 		if (tg3_flag(tp, USE_LINKCHG_REG)) {  in tg3_timer()
11020 			if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {  in tg3_timer()
11027 				tg3_setup_phy(tp, false);  in tg3_timer()
11028 		} else if (tg3_flag(tp, POLL_SERDES)) {  in tg3_timer()
11032 			if (tp->link_up &&  in tg3_timer()
11036 			if (!tp->link_up &&  in tg3_timer()
11042 				if (!tp->serdes_counter) {  in tg3_timer()
11044 					     (tp->mac_mode &  in tg3_timer()
11047 					tw32_f(MAC_MODE, tp->mac_mode);  in tg3_timer()
11050 				tg3_setup_phy(tp, false);  in tg3_timer()
11052 		} else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&  in tg3_timer()
11053 			   tg3_flag(tp, 5780_CLASS)) {  in tg3_timer()
11054 			tg3_serdes_parallel_detect(tp);  in tg3_timer()
11055 		} else if (tg3_flag(tp, POLL_CPMU_LINK)) {  in tg3_timer()
11060 			if (link_up != tp->link_up)  in tg3_timer()
11061 				tg3_setup_phy(tp, false);  in tg3_timer()
11064 		tp->timer_counter = tp->timer_multiplier;  in tg3_timer()
11084 	if (!--tp->asf_counter) {  in tg3_timer()
11085 		if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {  in tg3_timer()
11086 			tg3_wait_for_event_ack(tp);  in tg3_timer()
11088 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,  in tg3_timer()
11090 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);  in tg3_timer()
11091 			tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,  in tg3_timer()
11094 			tg3_generate_fw_event(tp);  in tg3_timer()
11096 		tp->asf_counter = tp->asf_multiplier;  in tg3_timer()
11100 	tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL);  in tg3_timer()
11102 	spin_unlock(&tp->lock);  in tg3_timer()
11105 	tp->timer.expires = jiffies + tp->timer_offset;  in tg3_timer()
11106 	add_timer(&tp->timer);  in tg3_timer()
11109 static void tg3_timer_init(struct tg3 *tp)  in tg3_timer_init()  argument
11111 	if (tg3_flag(tp, TAGGED_STATUS) &&  in tg3_timer_init()
11112 	    tg3_asic_rev(tp) != ASIC_REV_5717 &&  in tg3_timer_init()
11113 	    !tg3_flag(tp, 57765_CLASS))  in tg3_timer_init()
11114 		tp->timer_offset = HZ;  in tg3_timer_init()
11116 		tp->timer_offset = HZ / 10;  in tg3_timer_init()
11118 	BUG_ON(tp->timer_offset > HZ);  in tg3_timer_init()
11120 	tp->timer_multiplier = (HZ / tp->timer_offset);  in tg3_timer_init()
11121 	tp->asf_multiplier = (HZ / tp->timer_offset) *  in tg3_timer_init()
11124 	timer_setup(&tp->timer, tg3_timer, 0);  in tg3_timer_init()
11127 static void tg3_timer_start(struct tg3 *tp)  in tg3_timer_start()  argument
11129 	tp->asf_counter   = tp->asf_multiplier;  in tg3_timer_start()
11130 	tp->timer_counter = tp->timer_multiplier;  in tg3_timer_start()
11132 	tp->timer.expires = jiffies + tp->timer_offset;  in tg3_timer_start()
11133 	add_timer(&tp->timer);  in tg3_timer_start()
11136 static void tg3_timer_stop(struct tg3 *tp)  in tg3_timer_stop()  argument
11138 	del_timer_sync(&tp->timer);  in tg3_timer_stop()
11144 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)  in tg3_restart_hw()  argument
11145 	__releases(tp->lock)  in tg3_restart_hw()
11146 	__acquires(tp->lock)  in tg3_restart_hw()
11150 	err = tg3_init_hw(tp, reset_phy);  in tg3_restart_hw()
11152 		netdev_err(tp->dev,  in tg3_restart_hw()
11154 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_restart_hw()
11155 		tg3_full_unlock(tp);  in tg3_restart_hw()
11156 		tg3_timer_stop(tp);  in tg3_restart_hw()
11157 		tp->irq_sync = 0;  in tg3_restart_hw()
11158 		tg3_napi_enable(tp);  in tg3_restart_hw()
11159 		dev_close(tp->dev);  in tg3_restart_hw()
11160 		tg3_full_lock(tp, 0);  in tg3_restart_hw()
11167 	struct tg3 *tp = container_of(work, struct tg3, reset_task);  in tg3_reset_task()  local
11171 	tg3_full_lock(tp, 0);  in tg3_reset_task()
11173 	if (tp->pcierr_recovery || !netif_running(tp->dev)) {  in tg3_reset_task()
11174 		tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task()
11175 		tg3_full_unlock(tp);  in tg3_reset_task()
11180 	tg3_full_unlock(tp);  in tg3_reset_task()
11182 	tg3_phy_stop(tp);  in tg3_reset_task()
11184 	tg3_netif_stop(tp);  in tg3_reset_task()
11186 	tg3_full_lock(tp, 1);  in tg3_reset_task()
11188 	if (tg3_flag(tp, TX_RECOVERY_PENDING)) {  in tg3_reset_task()
11189 		tp->write32_tx_mbox = tg3_write32_tx_mbox;  in tg3_reset_task()
11190 		tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_reset_task()
11191 		tg3_flag_set(tp, MBOX_WRITE_REORDER);  in tg3_reset_task()
11192 		tg3_flag_clear(tp, TX_RECOVERY_PENDING);  in tg3_reset_task()
11195 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);  in tg3_reset_task()
11196 	err = tg3_init_hw(tp, true);  in tg3_reset_task()
11198 		tg3_full_unlock(tp);  in tg3_reset_task()
11199 		tp->irq_sync = 0;  in tg3_reset_task()
11200 		tg3_napi_enable(tp);  in tg3_reset_task()
11204 		tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task()
11205 		dev_close(tp->dev);  in tg3_reset_task()
11209 	tg3_netif_start(tp);  in tg3_reset_task()
11210 	tg3_full_unlock(tp);  in tg3_reset_task()
11211 	tg3_phy_start(tp);  in tg3_reset_task()
11212 	tg3_flag_clear(tp, RESET_TASK_PENDING);  in tg3_reset_task()
11217 static int tg3_request_irq(struct tg3 *tp, int irq_num)  in tg3_request_irq()  argument
11222 	struct tg3_napi *tnapi = &tp->napi[irq_num];  in tg3_request_irq()
11224 	if (tp->irq_cnt == 1)  in tg3_request_irq()
11225 		name = tp->dev->name;  in tg3_request_irq()
11230 				 "%s-txrx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11233 				 "%s-tx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11236 				 "%s-rx-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11239 				 "%s-%d", tp->dev->name, irq_num);  in tg3_request_irq()
11243 	if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {  in tg3_request_irq()
11245 		if (tg3_flag(tp, 1SHOT_MSI))  in tg3_request_irq()
11250 		if (tg3_flag(tp, TAGGED_STATUS))  in tg3_request_irq()
11258 static int tg3_test_interrupt(struct tg3 *tp)  in tg3_test_interrupt()  argument
11260 	struct tg3_napi *tnapi = &tp->napi[0];  in tg3_test_interrupt()
11261 	struct net_device *dev = tp->dev;  in tg3_test_interrupt()
11268 	tg3_disable_ints(tp);  in tg3_test_interrupt()
11276 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_test_interrupt()
11287 	tg3_enable_ints(tp);  in tg3_test_interrupt()
11289 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_test_interrupt()
11304 		if (tg3_flag(tp, 57765_PLUS) &&  in tg3_test_interrupt()
11311 	tg3_disable_ints(tp);  in tg3_test_interrupt()
11315 	err = tg3_request_irq(tp, 0);  in tg3_test_interrupt()
11322 		if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {  in tg3_test_interrupt()
11335 static int tg3_test_msi(struct tg3 *tp)  in tg3_test_msi()  argument
11340 	if (!tg3_flag(tp, USING_MSI))  in tg3_test_msi()
11346 	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_test_msi()
11347 	pci_write_config_word(tp->pdev, PCI_COMMAND,  in tg3_test_msi()
11350 	err = tg3_test_interrupt(tp);  in tg3_test_msi()
11352 	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_test_msi()
11362 	netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "  in tg3_test_msi()
11366 	free_irq(tp->napi[0].irq_vec, &tp->napi[0]);  in tg3_test_msi()
11368 	pci_disable_msi(tp->pdev);  in tg3_test_msi()
11370 	tg3_flag_clear(tp, USING_MSI);  in tg3_test_msi()
11371 	tp->napi[0].irq_vec = tp->pdev->irq;  in tg3_test_msi()
11373 	err = tg3_request_irq(tp, 0);  in tg3_test_msi()
11380 	tg3_full_lock(tp, 1);  in tg3_test_msi()
11382 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_test_msi()
11383 	err = tg3_init_hw(tp, true);  in tg3_test_msi()
11385 	tg3_full_unlock(tp);  in tg3_test_msi()
11388 		free_irq(tp->napi[0].irq_vec, &tp->napi[0]);  in tg3_test_msi()
11393 static int tg3_request_firmware(struct tg3 *tp)  in tg3_request_firmware()  argument
11397 	if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {  in tg3_request_firmware()
11398 		netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",  in tg3_request_firmware()
11399 			   tp->fw_needed);  in tg3_request_firmware()
11403 	fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;  in tg3_request_firmware()
11410 	tp->fw_len = be32_to_cpu(fw_hdr->len);	/* includes bss */  in tg3_request_firmware()
11411 	if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {  in tg3_request_firmware()
11412 		netdev_err(tp->dev, "bogus length %d in \"%s\"\n",  in tg3_request_firmware()
11413 			   tp->fw_len, tp->fw_needed);  in tg3_request_firmware()
11414 		release_firmware(tp->fw);  in tg3_request_firmware()
11415 		tp->fw = NULL;  in tg3_request_firmware()
11420 	tp->fw_needed = NULL;  in tg3_request_firmware()
11424 static u32 tg3_irq_count(struct tg3 *tp)  in tg3_irq_count()  argument
11426 	u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);  in tg3_irq_count()
11434 		irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);  in tg3_irq_count()
11440 static bool tg3_enable_msix(struct tg3 *tp)  in tg3_enable_msix()  argument
11445 	tp->txq_cnt = tp->txq_req;  in tg3_enable_msix()
11446 	tp->rxq_cnt = tp->rxq_req;  in tg3_enable_msix()
11447 	if (!tp->rxq_cnt)  in tg3_enable_msix()
11448 		tp->rxq_cnt = netif_get_num_default_rss_queues();  in tg3_enable_msix()
11449 	if (tp->rxq_cnt > tp->rxq_max)  in tg3_enable_msix()
11450 		tp->rxq_cnt = tp->rxq_max;  in tg3_enable_msix()
11456 	if (!tp->txq_req)  in tg3_enable_msix()
11457 		tp->txq_cnt = 1;  in tg3_enable_msix()
11459 	tp->irq_cnt = tg3_irq_count(tp);  in tg3_enable_msix()
11461 	for (i = 0; i < tp->irq_max; i++) {  in tg3_enable_msix()
11466 	rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);  in tg3_enable_msix()
11469 	} else if (rc < tp->irq_cnt) {  in tg3_enable_msix()
11470 		netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",  in tg3_enable_msix()
11471 			      tp->irq_cnt, rc);  in tg3_enable_msix()
11472 		tp->irq_cnt = rc;  in tg3_enable_msix()
11473 		tp->rxq_cnt = max(rc - 1, 1);  in tg3_enable_msix()
11474 		if (tp->txq_cnt)  in tg3_enable_msix()
11475 			tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);  in tg3_enable_msix()
11478 	for (i = 0; i < tp->irq_max; i++)  in tg3_enable_msix()
11479 		tp->napi[i].irq_vec = msix_ent[i].vector;  in tg3_enable_msix()
11481 	if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {  in tg3_enable_msix()
11482 		pci_disable_msix(tp->pdev);  in tg3_enable_msix()
11486 	if (tp->irq_cnt == 1)  in tg3_enable_msix()
11489 	tg3_flag_set(tp, ENABLE_RSS);  in tg3_enable_msix()
11491 	if (tp->txq_cnt > 1)  in tg3_enable_msix()
11492 		tg3_flag_set(tp, ENABLE_TSS);  in tg3_enable_msix()
11494 	netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);  in tg3_enable_msix()
11499 static void tg3_ints_init(struct tg3 *tp)  in tg3_ints_init()  argument
11501 	if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&  in tg3_ints_init()
11502 	    !tg3_flag(tp, TAGGED_STATUS)) {  in tg3_ints_init()
11506 		netdev_warn(tp->dev,  in tg3_ints_init()
11511 	if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))  in tg3_ints_init()
11512 		tg3_flag_set(tp, USING_MSIX);  in tg3_ints_init()
11513 	else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)  in tg3_ints_init()
11514 		tg3_flag_set(tp, USING_MSI);  in tg3_ints_init()
11516 	if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {  in tg3_ints_init()
11518 		if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)  in tg3_ints_init()
11520 		if (!tg3_flag(tp, 1SHOT_MSI))  in tg3_ints_init()
11525 	if (!tg3_flag(tp, USING_MSIX)) {  in tg3_ints_init()
11526 		tp->irq_cnt = 1;  in tg3_ints_init()
11527 		tp->napi[0].irq_vec = tp->pdev->irq;  in tg3_ints_init()
11530 	if (tp->irq_cnt == 1) {  in tg3_ints_init()
11531 		tp->txq_cnt = 1;  in tg3_ints_init()
11532 		tp->rxq_cnt = 1;  in tg3_ints_init()
11533 		netif_set_real_num_tx_queues(tp->dev, 1);  in tg3_ints_init()
11534 		netif_set_real_num_rx_queues(tp->dev, 1);  in tg3_ints_init()
11538 static void tg3_ints_fini(struct tg3 *tp)  in tg3_ints_fini()  argument
11540 	if (tg3_flag(tp, USING_MSIX))  in tg3_ints_fini()
11541 		pci_disable_msix(tp->pdev);  in tg3_ints_fini()
11542 	else if (tg3_flag(tp, USING_MSI))  in tg3_ints_fini()
11543 		pci_disable_msi(tp->pdev);  in tg3_ints_fini()
11544 	tg3_flag_clear(tp, USING_MSI);  in tg3_ints_fini()
11545 	tg3_flag_clear(tp, USING_MSIX);  in tg3_ints_fini()
11546 	tg3_flag_clear(tp, ENABLE_RSS);  in tg3_ints_fini()
11547 	tg3_flag_clear(tp, ENABLE_TSS);  in tg3_ints_fini()
11550 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,  in tg3_start()  argument
11553 	struct net_device *dev = tp->dev;  in tg3_start()
11560 	tg3_ints_init(tp);  in tg3_start()
11562 	tg3_rss_check_indir_tbl(tp);  in tg3_start()
11567 	err = tg3_alloc_consistent(tp);  in tg3_start()
11571 	tg3_napi_init(tp);  in tg3_start()
11573 	tg3_napi_enable(tp);  in tg3_start()
11575 	for (i = 0; i < tp->irq_cnt; i++) {  in tg3_start()
11576 		err = tg3_request_irq(tp, i);  in tg3_start()
11579 				struct tg3_napi *tnapi = &tp->napi[i];  in tg3_start()
11587 	tg3_full_lock(tp, 0);  in tg3_start()
11590 		tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_start()
11592 	err = tg3_init_hw(tp, reset_phy);  in tg3_start()
11594 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_start()
11595 		tg3_free_rings(tp);  in tg3_start()
11598 	tg3_full_unlock(tp);  in tg3_start()
11603 	if (test_irq && tg3_flag(tp, USING_MSI)) {  in tg3_start()
11604 		err = tg3_test_msi(tp);  in tg3_start()
11607 			tg3_full_lock(tp, 0);  in tg3_start()
11608 			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_start()
11609 			tg3_free_rings(tp);  in tg3_start()
11610 			tg3_full_unlock(tp);  in tg3_start()
11615 		if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {  in tg3_start()
11623 	tg3_phy_start(tp);  in tg3_start()
11625 	tg3_hwmon_open(tp);  in tg3_start()
11627 	tg3_full_lock(tp, 0);  in tg3_start()
11629 	tg3_timer_start(tp);  in tg3_start()
11630 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_start()
11631 	tg3_enable_ints(tp);  in tg3_start()
11633 	tg3_ptp_resume(tp);  in tg3_start()
11635 	tg3_full_unlock(tp);  in tg3_start()
11649 	for (i = tp->irq_cnt - 1; i >= 0; i--) {  in tg3_start()
11650 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_start()
11655 	tg3_napi_disable(tp);  in tg3_start()
11656 	tg3_napi_fini(tp);  in tg3_start()
11657 	tg3_free_consistent(tp);  in tg3_start()
11660 	tg3_ints_fini(tp);  in tg3_start()
11665 static void tg3_stop(struct tg3 *tp)  in tg3_stop()  argument
11669 	tg3_reset_task_cancel(tp);  in tg3_stop()
11670 	tg3_netif_stop(tp);  in tg3_stop()
11672 	tg3_timer_stop(tp);  in tg3_stop()
11674 	tg3_hwmon_close(tp);  in tg3_stop()
11676 	tg3_phy_stop(tp);  in tg3_stop()
11678 	tg3_full_lock(tp, 1);  in tg3_stop()
11680 	tg3_disable_ints(tp);  in tg3_stop()
11682 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_stop()
11683 	tg3_free_rings(tp);  in tg3_stop()
11684 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_stop()
11686 	tg3_full_unlock(tp);  in tg3_stop()
11688 	for (i = tp->irq_cnt - 1; i >= 0; i--) {  in tg3_stop()
11689 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_stop()
11693 	tg3_ints_fini(tp);  in tg3_stop()
11695 	tg3_napi_fini(tp);  in tg3_stop()
11697 	tg3_free_consistent(tp);  in tg3_stop()
11702 	struct tg3 *tp = netdev_priv(dev);  in tg3_open()  local
11705 	if (tp->pcierr_recovery) {  in tg3_open()
11711 	if (tp->fw_needed) {  in tg3_open()
11712 		err = tg3_request_firmware(tp);  in tg3_open()
11713 		if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_open()
11715 				netdev_warn(tp->dev, "EEE capability disabled\n");  in tg3_open()
11716 				tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;  in tg3_open()
11717 			} else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_open()
11718 				netdev_warn(tp->dev, "EEE capability restored\n");  in tg3_open()
11719 				tp->phy_flags |= TG3_PHYFLG_EEE_CAP;  in tg3_open()
11721 		} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {  in tg3_open()
11725 			netdev_warn(tp->dev, "TSO capability disabled\n");  in tg3_open()
11726 			tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_open()
11727 		} else if (!tg3_flag(tp, TSO_CAPABLE)) {  in tg3_open()
11728 			netdev_notice(tp->dev, "TSO capability restored\n");  in tg3_open()
11729 			tg3_flag_set(tp, TSO_CAPABLE);  in tg3_open()
11733 	tg3_carrier_off(tp);  in tg3_open()
11735 	err = tg3_power_up(tp);  in tg3_open()
11739 	tg3_full_lock(tp, 0);  in tg3_open()
11741 	tg3_disable_ints(tp);  in tg3_open()
11742 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_open()
11744 	tg3_full_unlock(tp);  in tg3_open()
11746 	err = tg3_start(tp,  in tg3_open()
11747 			!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),  in tg3_open()
11750 		tg3_frob_aux_power(tp, false);  in tg3_open()
11751 		pci_set_power_state(tp->pdev, PCI_D3hot);  in tg3_open()
11759 	struct tg3 *tp = netdev_priv(dev);  in tg3_close()  local
11761 	if (tp->pcierr_recovery) {  in tg3_close()
11767 	tg3_stop(tp);  in tg3_close()
11769 	if (pci_device_is_present(tp->pdev)) {  in tg3_close()
11770 		tg3_power_down_prepare(tp);  in tg3_close()
11772 		tg3_carrier_off(tp);  in tg3_close()
11782 static u64 tg3_calc_crc_errors(struct tg3 *tp)  in tg3_calc_crc_errors()  argument
11784 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_calc_crc_errors()
11786 	if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_calc_crc_errors()
11787 	    (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_calc_crc_errors()
11788 	     tg3_asic_rev(tp) == ASIC_REV_5701)) {  in tg3_calc_crc_errors()
11791 		if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {  in tg3_calc_crc_errors()
11792 			tg3_writephy(tp, MII_TG3_TEST1,  in tg3_calc_crc_errors()
11794 			tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);  in tg3_calc_crc_errors()
11798 		tp->phy_crc_errors += val;  in tg3_calc_crc_errors()
11800 		return tp->phy_crc_errors;  in tg3_calc_crc_errors()
11810 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)  in tg3_get_estats()  argument
11812 	struct tg3_ethtool_stats *old_estats = &tp->estats_prev;  in tg3_get_estats()
11813 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_get_estats()
11894 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)  in tg3_get_nstats()  argument
11896 	struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;  in tg3_get_nstats()
11897 	struct tg3_hw_stats *hw_stats = tp->hw_stats;  in tg3_get_nstats()
11939 		tg3_calc_crc_errors(tp);  in tg3_get_nstats()
11944 	stats->rx_dropped = tp->rx_dropped;  in tg3_get_nstats()
11945 	stats->tx_dropped = tp->tx_dropped;  in tg3_get_nstats()
11956 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_regs()  local
11962 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_get_regs()
11965 	tg3_full_lock(tp, 0);  in tg3_get_regs()
11967 	tg3_dump_legacy_regs(tp, (u32 *)_p);  in tg3_get_regs()
11969 	tg3_full_unlock(tp);  in tg3_get_regs()
11974 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eeprom_len()  local
11976 	return tp->nvram_size;  in tg3_get_eeprom_len()
11981 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eeprom()  local
11987 	if (tg3_flag(tp, NO_NVRAM))  in tg3_get_eeprom()
11997 	if (tg3_flag(tp, CPMU_PRESENT)) {  in tg3_get_eeprom()
12007 	tg3_override_clk(tp);  in tg3_get_eeprom()
12017 		ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);  in tg3_get_eeprom()
12029 		ret = tg3_nvram_read_be32(tp, offset + i, &val);  in tg3_get_eeprom()
12053 		ret = tg3_nvram_read_be32(tp, b_offset, &val);  in tg3_get_eeprom()
12063 	tg3_restore_clk(tp);  in tg3_get_eeprom()
12072 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_eeprom()  local
12078 	if (tg3_flag(tp, NO_NVRAM) ||  in tg3_set_eeprom()
12087 		ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);  in tg3_set_eeprom()
12101 		ret = tg3_nvram_read_be32(tp, offset+len-4, &end);  in tg3_set_eeprom()
12118 	ret = tg3_nvram_write_block(tp, offset, len, buf);  in tg3_set_eeprom()
12129 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_link_ksettings()  local
12132 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_get_link_ksettings()
12134 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_get_link_ksettings()
12136 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_get_link_ksettings()
12144 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_get_link_ksettings()
12148 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_get_link_ksettings()
12162 	advertising = tp->link_config.advertising;  in tg3_get_link_ksettings()
12163 	if (tg3_flag(tp, PAUSE_AUTONEG)) {  in tg3_get_link_ksettings()
12164 		if (tp->link_config.flowctrl & FLOW_CTRL_RX) {  in tg3_get_link_ksettings()
12165 			if (tp->link_config.flowctrl & FLOW_CTRL_TX) {  in tg3_get_link_ksettings()
12171 		} else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {  in tg3_get_link_ksettings()
12178 	if (netif_running(dev) && tp->link_up) {  in tg3_get_link_ksettings()
12179 		cmd->base.speed = tp->link_config.active_speed;  in tg3_get_link_ksettings()
12180 		cmd->base.duplex = tp->link_config.active_duplex;  in tg3_get_link_ksettings()
12183 			tp->link_config.rmt_adv);  in tg3_get_link_ksettings()
12185 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {  in tg3_get_link_ksettings()
12186 			if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)  in tg3_get_link_ksettings()
12196 	cmd->base.phy_address = tp->phy_addr;  in tg3_get_link_ksettings()
12197 	cmd->base.autoneg = tp->link_config.autoneg;  in tg3_get_link_ksettings()
12204 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_link_ksettings()  local
12208 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_set_link_ksettings()
12210 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_set_link_ksettings()
12212 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_set_link_ksettings()
12233 		if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_set_link_ksettings()
12237 		if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_set_link_ksettings()
12258 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {  in tg3_set_link_ksettings()
12271 	tg3_full_lock(tp, 0);  in tg3_set_link_ksettings()
12273 	tp->link_config.autoneg = cmd->base.autoneg;  in tg3_set_link_ksettings()
12275 		tp->link_config.advertising = (advertising |  in tg3_set_link_ksettings()
12277 		tp->link_config.speed = SPEED_UNKNOWN;  in tg3_set_link_ksettings()
12278 		tp->link_config.duplex = DUPLEX_UNKNOWN;  in tg3_set_link_ksettings()
12280 		tp->link_config.advertising = 0;  in tg3_set_link_ksettings()
12281 		tp->link_config.speed = speed;  in tg3_set_link_ksettings()
12282 		tp->link_config.duplex = cmd->base.duplex;  in tg3_set_link_ksettings()
12285 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_link_ksettings()
12287 	tg3_warn_mgmt_link_flap(tp);  in tg3_set_link_ksettings()
12290 		tg3_setup_phy(tp, true);  in tg3_set_link_ksettings()
12292 	tg3_full_unlock(tp);  in tg3_set_link_ksettings()
12299 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_drvinfo()  local
12302 	strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));  in tg3_get_drvinfo()
12303 	strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));  in tg3_get_drvinfo()
12308 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_wol()  local
12310 	if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))  in tg3_get_wol()
12315 	if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))  in tg3_get_wol()
12322 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_wol()  local
12323 	struct device *dp = &tp->pdev->dev;  in tg3_set_wol()
12328 	    !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))  in tg3_set_wol()
12334 		tg3_flag_set(tp, WOL_ENABLE);  in tg3_set_wol()
12336 		tg3_flag_clear(tp, WOL_ENABLE);  in tg3_set_wol()
12343 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_msglevel()  local
12344 	return tp->msg_enable;  in tg3_get_msglevel()
12349 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_msglevel()  local
12350 	tp->msg_enable = value;  in tg3_set_msglevel()
12355 	struct tg3 *tp = netdev_priv(dev);  in tg3_nway_reset()  local
12361 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_nway_reset()
12364 	tg3_warn_mgmt_link_flap(tp);  in tg3_nway_reset()
12366 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_nway_reset()
12367 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_nway_reset()
12369 		r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr));  in tg3_nway_reset()
12373 		spin_lock_bh(&tp->lock);  in tg3_nway_reset()
12375 		tg3_readphy(tp, MII_BMCR, &bmcr);  in tg3_nway_reset()
12376 		if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&  in tg3_nway_reset()
12378 		     (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {  in tg3_nway_reset()
12379 			tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |  in tg3_nway_reset()
12383 		spin_unlock_bh(&tp->lock);  in tg3_nway_reset()
12394 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ringparam()  local
12396 	ering->rx_max_pending = tp->rx_std_ring_mask;  in tg3_get_ringparam()
12397 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_get_ringparam()
12398 		ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;  in tg3_get_ringparam()
12404 	ering->rx_pending = tp->rx_pending;  in tg3_get_ringparam()
12405 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_get_ringparam()
12406 		ering->rx_jumbo_pending = tp->rx_jumbo_pending;  in tg3_get_ringparam()
12410 	ering->tx_pending = tp->napi[0].tx_pending;  in tg3_get_ringparam()
12418 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_ringparam()  local
12422 	if ((ering->rx_pending > tp->rx_std_ring_mask) ||  in tg3_set_ringparam()
12423 	    (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||  in tg3_set_ringparam()
12426 	    (tg3_flag(tp, TSO_BUG) &&  in tg3_set_ringparam()
12431 		tg3_phy_stop(tp);  in tg3_set_ringparam()
12432 		tg3_netif_stop(tp);  in tg3_set_ringparam()
12436 	tg3_full_lock(tp, irq_sync);  in tg3_set_ringparam()
12438 	tp->rx_pending = ering->rx_pending;  in tg3_set_ringparam()
12440 	if (tg3_flag(tp, MAX_RXPEND_64) &&  in tg3_set_ringparam()
12441 	    tp->rx_pending > 63)  in tg3_set_ringparam()
12442 		tp->rx_pending = 63;  in tg3_set_ringparam()
12444 	if (tg3_flag(tp, JUMBO_RING_ENABLE))  in tg3_set_ringparam()
12445 		tp->rx_jumbo_pending = ering->rx_jumbo_pending;  in tg3_set_ringparam()
12447 	for (i = 0; i < tp->irq_max; i++)  in tg3_set_ringparam()
12448 		tp->napi[i].tx_pending = ering->tx_pending;  in tg3_set_ringparam()
12451 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_set_ringparam()
12453 		if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_ringparam()
12454 		    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_set_ringparam()
12455 		    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_set_ringparam()
12458 		err = tg3_restart_hw(tp, reset_phy);  in tg3_set_ringparam()
12460 			tg3_netif_start(tp);  in tg3_set_ringparam()
12463 	tg3_full_unlock(tp);  in tg3_set_ringparam()
12466 		tg3_phy_start(tp);  in tg3_set_ringparam()
12473 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_pauseparam()  local
12475 	epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);  in tg3_get_pauseparam()
12477 	if (tp->link_config.flowctrl & FLOW_CTRL_RX)  in tg3_get_pauseparam()
12482 	if (tp->link_config.flowctrl & FLOW_CTRL_TX)  in tg3_get_pauseparam()
12490 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_pauseparam()  local
12494 	if (tp->link_config.autoneg == AUTONEG_ENABLE)  in tg3_set_pauseparam()
12495 		tg3_warn_mgmt_link_flap(tp);  in tg3_set_pauseparam()
12497 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_set_pauseparam()
12500 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_set_pauseparam()
12505 		tp->link_config.flowctrl = 0;  in tg3_set_pauseparam()
12508 			tp->link_config.flowctrl |= FLOW_CTRL_RX;  in tg3_set_pauseparam()
12511 				tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12514 			tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12518 			tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12520 			tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12522 		if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {  in tg3_set_pauseparam()
12535 				tg3_setup_flow_control(tp, 0, 0);  in tg3_set_pauseparam()
12541 			tg3_netif_stop(tp);  in tg3_set_pauseparam()
12545 		tg3_full_lock(tp, irq_sync);  in tg3_set_pauseparam()
12548 			tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12550 			tg3_flag_clear(tp, PAUSE_AUTONEG);  in tg3_set_pauseparam()
12552 			tp->link_config.flowctrl |= FLOW_CTRL_RX;  in tg3_set_pauseparam()
12554 			tp->link_config.flowctrl &= ~FLOW_CTRL_RX;  in tg3_set_pauseparam()
12556 			tp->link_config.flowctrl |= FLOW_CTRL_TX;  in tg3_set_pauseparam()
12558 			tp->link_config.flowctrl &= ~FLOW_CTRL_TX;  in tg3_set_pauseparam()
12561 			tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_set_pauseparam()
12563 			if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_set_pauseparam()
12564 			    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_set_pauseparam()
12565 			    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_set_pauseparam()
12568 			err = tg3_restart_hw(tp, reset_phy);  in tg3_set_pauseparam()
12570 				tg3_netif_start(tp);  in tg3_set_pauseparam()
12573 		tg3_full_unlock(tp);  in tg3_set_pauseparam()
12576 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_pauseparam()
12596 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxnfc()  local
12598 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_get_rxnfc()
12603 		if (netif_running(tp->dev))  in tg3_get_rxnfc()
12604 			info->data = tp->rxq_cnt;  in tg3_get_rxnfc()
12621 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxfh_indir_size()  local
12623 	if (tg3_flag(tp, SUPPORT_MSIX))  in tg3_get_rxfh_indir_size()
12631 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_rxfh()  local
12640 		indir[i] = tp->rss_ind_tbl[i];  in tg3_get_rxfh()
12648 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_rxfh()  local
12662 		tp->rss_ind_tbl[i] = indir[i];  in tg3_set_rxfh()
12664 	if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))  in tg3_set_rxfh()
12670 	tg3_full_lock(tp, 0);  in tg3_set_rxfh()
12671 	tg3_rss_write_indir_tbl(tp);  in tg3_set_rxfh()
12672 	tg3_full_unlock(tp);  in tg3_set_rxfh()
12680 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_channels()  local
12683 	channel->max_rx = tp->rxq_max;  in tg3_get_channels()
12684 	channel->max_tx = tp->txq_max;  in tg3_get_channels()
12687 		channel->rx_count = tp->rxq_cnt;  in tg3_get_channels()
12688 		channel->tx_count = tp->txq_cnt;  in tg3_get_channels()
12690 		if (tp->rxq_req)  in tg3_get_channels()
12691 			channel->rx_count = tp->rxq_req;  in tg3_get_channels()
12693 			channel->rx_count = min(deflt_qs, tp->rxq_max);  in tg3_get_channels()
12695 		if (tp->txq_req)  in tg3_get_channels()
12696 			channel->tx_count = tp->txq_req;  in tg3_get_channels()
12698 			channel->tx_count = min(deflt_qs, tp->txq_max);  in tg3_get_channels()
12705 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_channels()  local
12707 	if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_set_channels()
12710 	if (channel->rx_count > tp->rxq_max ||  in tg3_set_channels()
12711 	    channel->tx_count > tp->txq_max)  in tg3_set_channels()
12714 	tp->rxq_req = channel->rx_count;  in tg3_set_channels()
12715 	tp->txq_req = channel->tx_count;  in tg3_set_channels()
12720 	tg3_stop(tp);  in tg3_set_channels()
12722 	tg3_carrier_off(tp);  in tg3_set_channels()
12724 	tg3_start(tp, true, false, false);  in tg3_set_channels()
12747 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_phys_id()  local
12769 		tw32(MAC_LED_CTRL, tp->led_ctrl);  in tg3_set_phys_id()
12779 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_ethtool_stats()  local
12781 	if (tp->hw_stats)  in tg3_get_ethtool_stats()
12782 		tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);  in tg3_get_ethtool_stats()
12787 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen)  in tg3_vpd_readblock()  argument
12794 	if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))  in tg3_vpd_readblock()
12801 			if (tg3_nvram_read(tp, offset, &val))  in tg3_vpd_readblock()
12811 			if (tg3_nvram_read(tp, offset + 4, &offset))  in tg3_vpd_readblock()
12814 			offset = tg3_nvram_logical_addr(tp, offset);  in tg3_vpd_readblock()
12831 			if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))  in tg3_vpd_readblock()
12836 		buf = pci_vpd_alloc(tp->pdev, vpdlen);  in tg3_vpd_readblock()
12858 static int tg3_test_nvram(struct tg3 *tp)  in tg3_test_nvram()  argument
12865 	if (tg3_flag(tp, NO_NVRAM))  in tg3_test_nvram()
12868 	if (tg3_nvram_read(tp, 0, &magic) != 0)  in tg3_test_nvram()
12911 		err = tg3_nvram_read_be32(tp, i, &buf[j]);  in tg3_test_nvram()
13002 	buf = tg3_vpd_readblock(tp, &len);  in tg3_test_nvram()
13018 static int tg3_test_link(struct tg3 *tp)  in tg3_test_link()  argument
13022 	if (!netif_running(tp->dev))  in tg3_test_link()
13025 	if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_test_link()
13031 		if (tp->link_up)  in tg3_test_link()
13042 static int tg3_test_registers(struct tg3 *tp)  in tg3_test_registers()  argument
13192 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_test_registers()
13194 		if (tg3_flag(tp, 5750_PLUS))  in tg3_test_registers()
13205 		if (tg3_flag(tp, IS_5788) &&  in tg3_test_registers()
13255 	if (netif_msg_hw(tp))  in tg3_test_registers()
13256 		netdev_err(tp->dev,  in tg3_test_registers()
13262 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)  in tg3_do_mem_test()  argument
13272 			tg3_write_mem(tp, offset + j, test_pattern[i]);  in tg3_do_mem_test()
13273 			tg3_read_mem(tp, offset + j, &val);  in tg3_do_mem_test()
13281 static int tg3_test_memory(struct tg3 *tp)  in tg3_test_memory()  argument
13328 	if (tg3_flag(tp, 5717_PLUS))  in tg3_test_memory()
13330 	else if (tg3_flag(tp, 57765_CLASS) ||  in tg3_test_memory()
13331 		 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_test_memory()
13333 	else if (tg3_flag(tp, 5755_PLUS))  in tg3_test_memory()
13335 	else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_test_memory()
13337 	else if (tg3_flag(tp, 5705_PLUS))  in tg3_test_memory()
13343 		err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);  in tg3_test_memory()
13374 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)  in tg3_run_loopback()  argument
13385 	struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;  in tg3_run_loopback()
13387 	tnapi = &tp->napi[0];  in tg3_run_loopback()
13388 	rnapi = &tp->napi[0];  in tg3_run_loopback()
13389 	if (tp->irq_cnt > 1) {  in tg3_run_loopback()
13390 		if (tg3_flag(tp, ENABLE_RSS))  in tg3_run_loopback()
13391 			rnapi = &tp->napi[1];  in tg3_run_loopback()
13392 		if (tg3_flag(tp, ENABLE_TSS))  in tg3_run_loopback()
13393 			tnapi = &tp->napi[1];  in tg3_run_loopback()
13400 	skb = netdev_alloc_skb(tp->dev, tx_len);  in tg3_run_loopback()
13405 	memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);  in tg3_run_loopback()
13429 		if (tg3_flag(tp, HW_TSO_1) ||  in tg3_run_loopback()
13430 		    tg3_flag(tp, HW_TSO_2) ||  in tg3_run_loopback()
13431 		    tg3_flag(tp, HW_TSO_3)) {  in tg3_run_loopback()
13439 		if (tg3_flag(tp, HW_TSO_3)) {  in tg3_run_loopback()
13444 		} else if (tg3_flag(tp, HW_TSO_2))  in tg3_run_loopback()
13446 		else if (tg3_flag(tp, HW_TSO_1) ||  in tg3_run_loopback()
13447 			 tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_run_loopback()
13458 		if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&  in tg3_run_loopback()
13466 	map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE);  in tg3_run_loopback()
13467 	if (dma_mapping_error(&tp->pdev->dev, map)) {  in tg3_run_loopback()
13476 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_run_loopback()
13503 		tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |  in tg3_run_loopback()
13565 		dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len,  in tg3_run_loopback()
13568 		rx_data += TG3_RX_OFFSET(tp);  in tg3_run_loopback()
13590 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)  in tg3_test_loopback()  argument
13596 	if (tp->dma_limit)  in tg3_test_loopback()
13597 		jmb_pkt_sz = tp->dma_limit - ETH_HLEN;  in tg3_test_loopback()
13599 	eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;  in tg3_test_loopback()
13600 	tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;  in tg3_test_loopback()
13602 	if (!netif_running(tp->dev)) {  in tg3_test_loopback()
13610 	err = tg3_reset_hw(tp, true);  in tg3_test_loopback()
13619 	if (tg3_flag(tp, ENABLE_RSS)) {  in tg3_test_loopback()
13633 	if (tg3_asic_rev(tp) != ASIC_REV_5780 &&  in tg3_test_loopback()
13634 	    !tg3_flag(tp, CPMU_PRESENT)) {  in tg3_test_loopback()
13635 		tg3_mac_loopback(tp, true);  in tg3_test_loopback()
13637 		if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13640 		if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13641 		    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13644 		tg3_mac_loopback(tp, false);  in tg3_test_loopback()
13647 	if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&  in tg3_test_loopback()
13648 	    !tg3_flag(tp, USE_PHYLIB)) {  in tg3_test_loopback()
13651 		tg3_phy_lpbk_set(tp, 0, false);  in tg3_test_loopback()
13660 		if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13662 		if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_test_loopback()
13663 		    tg3_run_loopback(tp, ETH_FRAME_LEN, true))  in tg3_test_loopback()
13665 		if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13666 		    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13670 			tg3_phy_lpbk_set(tp, 0, true);  in tg3_test_loopback()
13678 			if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))  in tg3_test_loopback()
13681 			if (tg3_flag(tp, TSO_CAPABLE) &&  in tg3_test_loopback()
13682 			    tg3_run_loopback(tp, ETH_FRAME_LEN, true))  in tg3_test_loopback()
13685 			if (tg3_flag(tp, JUMBO_RING_ENABLE) &&  in tg3_test_loopback()
13686 			    tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))  in tg3_test_loopback()
13692 		if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)  in tg3_test_loopback()
13693 			tg3_phy_toggle_apd(tp, true);  in tg3_test_loopback()
13700 	tp->phy_flags |= eee_cap;  in tg3_test_loopback()
13708 	struct tg3 *tp = netdev_priv(dev);  in tg3_self_test()  local
13711 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {  in tg3_self_test()
13712 		if (tg3_power_up(tp)) {  in tg3_self_test()
13717 		tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_self_test()
13722 	if (tg3_test_nvram(tp) != 0) {  in tg3_self_test()
13726 	if (!doextlpbk && tg3_test_link(tp)) {  in tg3_self_test()
13734 			tg3_phy_stop(tp);  in tg3_self_test()
13735 			tg3_netif_stop(tp);  in tg3_self_test()
13739 		tg3_full_lock(tp, irq_sync);  in tg3_self_test()
13740 		tg3_halt(tp, RESET_KIND_SUSPEND, 1);  in tg3_self_test()
13741 		err = tg3_nvram_lock(tp);  in tg3_self_test()
13742 		tg3_halt_cpu(tp, RX_CPU_BASE);  in tg3_self_test()
13743 		if (!tg3_flag(tp, 5705_PLUS))  in tg3_self_test()
13744 			tg3_halt_cpu(tp, TX_CPU_BASE);  in tg3_self_test()
13746 			tg3_nvram_unlock(tp);  in tg3_self_test()
13748 		if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)  in tg3_self_test()
13749 			tg3_phy_reset(tp);  in tg3_self_test()
13751 		if (tg3_test_registers(tp) != 0) {  in tg3_self_test()
13756 		if (tg3_test_memory(tp) != 0) {  in tg3_self_test()
13764 		if (tg3_test_loopback(tp, data, doextlpbk))  in tg3_self_test()
13767 		tg3_full_unlock(tp);  in tg3_self_test()
13769 		if (tg3_test_interrupt(tp) != 0) {  in tg3_self_test()
13774 		tg3_full_lock(tp, 0);  in tg3_self_test()
13776 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_self_test()
13778 			tg3_flag_set(tp, INIT_COMPLETE);  in tg3_self_test()
13779 			err2 = tg3_restart_hw(tp, true);  in tg3_self_test()
13781 				tg3_netif_start(tp);  in tg3_self_test()
13784 		tg3_full_unlock(tp);  in tg3_self_test()
13787 			tg3_phy_start(tp);  in tg3_self_test()
13789 	if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)  in tg3_self_test()
13790 		tg3_power_down_prepare(tp);  in tg3_self_test()
13796 	struct tg3 *tp = netdev_priv(dev);  in tg3_hwtstamp_set()  local
13799 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_hwtstamp_set()
13811 		tp->rxptpctl = 0;  in tg3_hwtstamp_set()
13814 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13818 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13822 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |  in tg3_hwtstamp_set()
13826 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13830 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13834 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13838 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13842 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13846 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13850 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |  in tg3_hwtstamp_set()
13854 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |  in tg3_hwtstamp_set()
13858 		tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |  in tg3_hwtstamp_set()
13865 	if (netif_running(dev) && tp->rxptpctl)  in tg3_hwtstamp_set()
13867 		     tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);  in tg3_hwtstamp_set()
13870 		tg3_flag_set(tp, TX_TSTAMP_EN);  in tg3_hwtstamp_set()
13872 		tg3_flag_clear(tp, TX_TSTAMP_EN);  in tg3_hwtstamp_set()
13880 	struct tg3 *tp = netdev_priv(dev);  in tg3_hwtstamp_get()  local
13883 	if (!tg3_flag(tp, PTP_CAPABLE))  in tg3_hwtstamp_get()
13887 	stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?  in tg3_hwtstamp_get()
13890 	switch (tp->rxptpctl) {  in tg3_hwtstamp_get()
13942 	struct tg3 *tp = netdev_priv(dev);  in tg3_ioctl()  local
13945 	if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_ioctl()
13947 		if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))  in tg3_ioctl()
13949 		phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr);  in tg3_ioctl()
13955 		data->phy_id = tp->phy_addr;  in tg3_ioctl()
13961 		if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_ioctl()
13967 		spin_lock_bh(&tp->lock);  in tg3_ioctl()
13968 		err = __tg3_readphy(tp, data->phy_id & 0x1f,  in tg3_ioctl()
13970 		spin_unlock_bh(&tp->lock);  in tg3_ioctl()
13978 		if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_ioctl()
13984 		spin_lock_bh(&tp->lock);  in tg3_ioctl()
13985 		err = __tg3_writephy(tp, data->phy_id & 0x1f,  in tg3_ioctl()
13987 		spin_unlock_bh(&tp->lock);  in tg3_ioctl()
14009 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_coalesce()  local
14011 	memcpy(ec, &tp->coal, sizeof(*ec));  in tg3_get_coalesce()
14020 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_coalesce()  local
14024 	if (!tg3_flag(tp, 5705_PLUS)) {  in tg3_set_coalesce()
14046 	tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;  in tg3_set_coalesce()
14047 	tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;  in tg3_set_coalesce()
14048 	tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;  in tg3_set_coalesce()
14049 	tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;  in tg3_set_coalesce()
14050 	tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;  in tg3_set_coalesce()
14051 	tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;  in tg3_set_coalesce()
14052 	tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;  in tg3_set_coalesce()
14053 	tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;  in tg3_set_coalesce()
14054 	tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;  in tg3_set_coalesce()
14057 		tg3_full_lock(tp, 0);  in tg3_set_coalesce()
14058 		__tg3_set_coalesce(tp, &tp->coal);  in tg3_set_coalesce()
14059 		tg3_full_unlock(tp);  in tg3_set_coalesce()
14066 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_eee()  local
14068 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_set_eee()
14069 		netdev_warn(tp->dev, "Board does not support EEE!\n");  in tg3_set_eee()
14073 	if (edata->advertised != tp->eee.advertised) {  in tg3_set_eee()
14074 		netdev_warn(tp->dev,  in tg3_set_eee()
14080 		netdev_warn(tp->dev,  in tg3_set_eee()
14086 	tp->eee = *edata;  in tg3_set_eee()
14088 	tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;  in tg3_set_eee()
14089 	tg3_warn_mgmt_link_flap(tp);  in tg3_set_eee()
14091 	if (netif_running(tp->dev)) {  in tg3_set_eee()
14092 		tg3_full_lock(tp, 0);  in tg3_set_eee()
14093 		tg3_setup_eee(tp);  in tg3_set_eee()
14094 		tg3_phy_reset(tp);  in tg3_set_eee()
14095 		tg3_full_unlock(tp);  in tg3_set_eee()
14103 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_eee()  local
14105 	if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {  in tg3_get_eee()
14106 		netdev_warn(tp->dev,  in tg3_get_eee()
14111 	*edata = tp->eee;  in tg3_get_eee()
14160 	struct tg3 *tp = netdev_priv(dev);  in tg3_get_stats64()  local
14162 	spin_lock_bh(&tp->lock);  in tg3_get_stats64()
14163 	if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) {  in tg3_get_stats64()
14164 		*stats = tp->net_stats_prev;  in tg3_get_stats64()
14165 		spin_unlock_bh(&tp->lock);  in tg3_get_stats64()
14169 	tg3_get_nstats(tp, stats);  in tg3_get_stats64()
14170 	spin_unlock_bh(&tp->lock);  in tg3_get_stats64()
14175 	struct tg3 *tp = netdev_priv(dev);  in tg3_set_rx_mode()  local
14180 	tg3_full_lock(tp, 0);  in tg3_set_rx_mode()
14182 	tg3_full_unlock(tp);  in tg3_set_rx_mode()
14185 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,  in tg3_set_mtu()  argument
14191 		if (tg3_flag(tp, 5780_CLASS)) {  in tg3_set_mtu()
14193 			tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_set_mtu()
14195 			tg3_flag_set(tp, JUMBO_RING_ENABLE);  in tg3_set_mtu()
14198 		if (tg3_flag(tp, 5780_CLASS)) {  in tg3_set_mtu()
14199 			tg3_flag_set(tp, TSO_CAPABLE);  in tg3_set_mtu()
14202 		tg3_flag_clear(tp, JUMBO_RING_ENABLE);  in tg3_set_mtu()
14208 	struct tg3 *tp = netdev_priv(dev);  in tg3_change_mtu()  local
14216 		tg3_set_mtu(dev, tp, new_mtu);  in tg3_change_mtu()
14220 	tg3_phy_stop(tp);  in tg3_change_mtu()
14222 	tg3_netif_stop(tp);  in tg3_change_mtu()
14224 	tg3_set_mtu(dev, tp, new_mtu);  in tg3_change_mtu()
14226 	tg3_full_lock(tp, 1);  in tg3_change_mtu()
14228 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_change_mtu()
14233 	if (tg3_asic_rev(tp) == ASIC_REV_57766 ||  in tg3_change_mtu()
14234 	    tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_change_mtu()
14235 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_change_mtu()
14236 	    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_change_mtu()
14239 	err = tg3_restart_hw(tp, reset_phy);  in tg3_change_mtu()
14242 		tg3_netif_start(tp);  in tg3_change_mtu()
14244 	tg3_full_unlock(tp);  in tg3_change_mtu()
14247 		tg3_phy_start(tp);  in tg3_change_mtu()
14270 static void tg3_get_eeprom_size(struct tg3 *tp)  in tg3_get_eeprom_size()  argument
14274 	tp->nvram_size = EEPROM_CHIP_SIZE;  in tg3_get_eeprom_size()
14276 	if (tg3_nvram_read(tp, 0, &magic) != 0)  in tg3_get_eeprom_size()
14291 	while (cursize < tp->nvram_size) {  in tg3_get_eeprom_size()
14292 		if (tg3_nvram_read(tp, cursize, &val) != 0)  in tg3_get_eeprom_size()
14301 	tp->nvram_size = cursize;  in tg3_get_eeprom_size()
14304 static void tg3_get_nvram_size(struct tg3 *tp)  in tg3_get_nvram_size()  argument
14308 	if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)  in tg3_get_nvram_size()
14313 		tg3_get_eeprom_size(tp);  in tg3_get_nvram_size()
14317 	if (tg3_nvram_read(tp, 0xf0, &val) == 0) {  in tg3_get_nvram_size()
14330 			tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;  in tg3_get_nvram_size()
14334 	tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_nvram_size()
14337 static void tg3_get_nvram_info(struct tg3 *tp)  in tg3_get_nvram_info()  argument
14343 		tg3_flag_set(tp, FLASH);  in tg3_get_nvram_info()
14349 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_get_nvram_info()
14350 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_nvram_info()
14353 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14354 			tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;  in tg3_get_nvram_info()
14355 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14358 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14359 			tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;  in tg3_get_nvram_info()
14362 			tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14363 			tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_nvram_info()
14364 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14367 			tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_nvram_info()
14368 			tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;  in tg3_get_nvram_info()
14369 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14372 			tp->nvram_jedecnum = JEDEC_SAIFUN;  in tg3_get_nvram_info()
14373 			tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;  in tg3_get_nvram_info()
14377 			tp->nvram_jedecnum = JEDEC_SST;  in tg3_get_nvram_info()
14378 			tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;  in tg3_get_nvram_info()
14382 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_nvram_info()
14383 		tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;  in tg3_get_nvram_info()
14384 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_nvram_info()
14388 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)  in tg3_nvram_get_pagesize()  argument
14392 		tp->nvram_pagesize = 256;  in tg3_nvram_get_pagesize()
14395 		tp->nvram_pagesize = 512;  in tg3_nvram_get_pagesize()
14398 		tp->nvram_pagesize = 1024;  in tg3_nvram_get_pagesize()
14401 		tp->nvram_pagesize = 2048;  in tg3_nvram_get_pagesize()
14404 		tp->nvram_pagesize = 4096;  in tg3_nvram_get_pagesize()
14407 		tp->nvram_pagesize = 264;  in tg3_nvram_get_pagesize()
14410 		tp->nvram_pagesize = 528;  in tg3_nvram_get_pagesize()
14415 static void tg3_get_5752_nvram_info(struct tg3 *tp)  in tg3_get_5752_nvram_info()  argument
14423 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5752_nvram_info()
14428 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5752_nvram_info()
14429 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14432 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5752_nvram_info()
14433 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14434 		tg3_flag_set(tp, FLASH);  in tg3_get_5752_nvram_info()
14439 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5752_nvram_info()
14440 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5752_nvram_info()
14441 		tg3_flag_set(tp, FLASH);  in tg3_get_5752_nvram_info()
14445 	if (tg3_flag(tp, FLASH)) {  in tg3_get_5752_nvram_info()
14446 		tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5752_nvram_info()
14449 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5752_nvram_info()
14456 static void tg3_get_5755_nvram_info(struct tg3 *tp)  in tg3_get_5755_nvram_info()  argument
14464 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5755_nvram_info()
14474 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5755_nvram_info()
14475 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5755_nvram_info()
14476 		tg3_flag_set(tp, FLASH);  in tg3_get_5755_nvram_info()
14477 		tp->nvram_pagesize = 264;  in tg3_get_5755_nvram_info()
14480 			tp->nvram_size = (protect ? 0x3e200 :  in tg3_get_5755_nvram_info()
14483 			tp->nvram_size = (protect ? 0x1f200 :  in tg3_get_5755_nvram_info()
14486 			tp->nvram_size = (protect ? 0x1f200 :  in tg3_get_5755_nvram_info()
14492 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5755_nvram_info()
14493 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5755_nvram_info()
14494 		tg3_flag_set(tp, FLASH);  in tg3_get_5755_nvram_info()
14495 		tp->nvram_pagesize = 256;  in tg3_get_5755_nvram_info()
14497 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14501 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14505 			tp->nvram_size = (protect ?  in tg3_get_5755_nvram_info()
14512 static void tg3_get_5787_nvram_info(struct tg3 *tp)  in tg3_get_5787_nvram_info()  argument
14523 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5787_nvram_info()
14524 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14525 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5787_nvram_info()
14534 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5787_nvram_info()
14535 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14536 		tg3_flag_set(tp, FLASH);  in tg3_get_5787_nvram_info()
14537 		tp->nvram_pagesize = 264;  in tg3_get_5787_nvram_info()
14542 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5787_nvram_info()
14543 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5787_nvram_info()
14544 		tg3_flag_set(tp, FLASH);  in tg3_get_5787_nvram_info()
14545 		tp->nvram_pagesize = 256;  in tg3_get_5787_nvram_info()
14550 static void tg3_get_5761_nvram_info(struct tg3 *tp)  in tg3_get_5761_nvram_info()  argument
14558 		tg3_flag_set(tp, PROTECTED_NVRAM);  in tg3_get_5761_nvram_info()
14572 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5761_nvram_info()
14573 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5761_nvram_info()
14574 		tg3_flag_set(tp, FLASH);  in tg3_get_5761_nvram_info()
14575 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5761_nvram_info()
14576 		tp->nvram_pagesize = 256;  in tg3_get_5761_nvram_info()
14586 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5761_nvram_info()
14587 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5761_nvram_info()
14588 		tg3_flag_set(tp, FLASH);  in tg3_get_5761_nvram_info()
14589 		tp->nvram_pagesize = 256;  in tg3_get_5761_nvram_info()
14594 		tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);  in tg3_get_5761_nvram_info()
14601 			tp->nvram_size = TG3_NVRAM_SIZE_2MB;  in tg3_get_5761_nvram_info()
14607 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5761_nvram_info()
14613 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5761_nvram_info()
14619 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5761_nvram_info()
14625 static void tg3_get_5906_nvram_info(struct tg3 *tp)  in tg3_get_5906_nvram_info()  argument
14627 	tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5906_nvram_info()
14628 	tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5906_nvram_info()
14629 	tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5906_nvram_info()
14632 static void tg3_get_57780_nvram_info(struct tg3 *tp)  in tg3_get_57780_nvram_info()  argument
14641 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_57780_nvram_info()
14642 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14643 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_57780_nvram_info()
14655 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_57780_nvram_info()
14656 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14657 		tg3_flag_set(tp, FLASH);  in tg3_get_57780_nvram_info()
14663 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_57780_nvram_info()
14667 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_57780_nvram_info()
14671 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_57780_nvram_info()
14678 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_57780_nvram_info()
14679 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_57780_nvram_info()
14680 		tg3_flag_set(tp, FLASH);  in tg3_get_57780_nvram_info()
14684 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_57780_nvram_info()
14687 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_57780_nvram_info()
14690 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_57780_nvram_info()
14695 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_57780_nvram_info()
14699 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_57780_nvram_info()
14700 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_57780_nvram_info()
14701 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_57780_nvram_info()
14705 static void tg3_get_5717_nvram_info(struct tg3 *tp)  in tg3_get_5717_nvram_info()  argument
14714 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5717_nvram_info()
14715 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14716 		tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5717_nvram_info()
14728 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5717_nvram_info()
14729 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14730 		tg3_flag_set(tp, FLASH);  in tg3_get_5717_nvram_info()
14738 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5717_nvram_info()
14741 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5717_nvram_info()
14755 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5717_nvram_info()
14756 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5717_nvram_info()
14757 		tg3_flag_set(tp, FLASH);  in tg3_get_5717_nvram_info()
14766 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5717_nvram_info()
14769 			tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5717_nvram_info()
14774 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5717_nvram_info()
14778 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5717_nvram_info()
14779 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_5717_nvram_info()
14780 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5717_nvram_info()
14783 static void tg3_get_5720_nvram_info(struct tg3 *tp)  in tg3_get_5720_nvram_info()  argument
14790 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_get_5720_nvram_info()
14792 			tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14802 			tp->nvram_pagesize = 4096;  in tg3_get_5720_nvram_info()
14803 			tp->nvram_jedecnum = JEDEC_MACRONIX;  in tg3_get_5720_nvram_info()
14804 			tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14805 			tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5720_nvram_info()
14806 			tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14808 			tp->nvram_size =  in tg3_get_5720_nvram_info()
14832 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5720_nvram_info()
14833 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14838 			tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;  in tg3_get_5720_nvram_info()
14840 			tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;  in tg3_get_5720_nvram_info()
14854 		tp->nvram_jedecnum = JEDEC_ATMEL;  in tg3_get_5720_nvram_info()
14855 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14856 		tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14862 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5720_nvram_info()
14867 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5720_nvram_info()
14871 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5720_nvram_info()
14874 			if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_get_5720_nvram_info()
14875 				tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5720_nvram_info()
14897 		tp->nvram_jedecnum = JEDEC_ST;  in tg3_get_5720_nvram_info()
14898 		tg3_flag_set(tp, NVRAM_BUFFERED);  in tg3_get_5720_nvram_info()
14899 		tg3_flag_set(tp, FLASH);  in tg3_get_5720_nvram_info()
14906 			tp->nvram_size = TG3_NVRAM_SIZE_256KB;  in tg3_get_5720_nvram_info()
14912 			tp->nvram_size = TG3_NVRAM_SIZE_512KB;  in tg3_get_5720_nvram_info()
14918 			tp->nvram_size = TG3_NVRAM_SIZE_1MB;  in tg3_get_5720_nvram_info()
14921 			if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_get_5720_nvram_info()
14922 				tp->nvram_size = TG3_NVRAM_SIZE_128KB;  in tg3_get_5720_nvram_info()
14927 		tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14931 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5720_nvram_info()
14932 	if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)  in tg3_get_5720_nvram_info()
14933 		tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);  in tg3_get_5720_nvram_info()
14935 	if (tg3_asic_rev(tp) == ASIC_REV_5762) {  in tg3_get_5720_nvram_info()
14938 		if (tg3_nvram_read(tp, 0, &val))  in tg3_get_5720_nvram_info()
14943 			tg3_flag_set(tp, NO_NVRAM);  in tg3_get_5720_nvram_info()
14948 static void tg3_nvram_init(struct tg3 *tp)  in tg3_nvram_init()  argument
14950 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_nvram_init()
14952 		tg3_flag_clear(tp, NVRAM);  in tg3_nvram_init()
14953 		tg3_flag_clear(tp, NVRAM_BUFFERED);  in tg3_nvram_init()
14954 		tg3_flag_set(tp, NO_NVRAM);  in tg3_nvram_init()
14970 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_nvram_init()
14971 	    tg3_asic_rev(tp) != ASIC_REV_5701) {  in tg3_nvram_init()
14972 		tg3_flag_set(tp, NVRAM);  in tg3_nvram_init()
14974 		if (tg3_nvram_lock(tp)) {  in tg3_nvram_init()
14975 			netdev_warn(tp->dev,  in tg3_nvram_init()
14980 		tg3_enable_nvram_access(tp);  in tg3_nvram_init()
14982 		tp->nvram_size = 0;  in tg3_nvram_init()
14984 		if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_nvram_init()
14985 			tg3_get_5752_nvram_info(tp);  in tg3_nvram_init()
14986 		else if (tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_nvram_init()
14987 			tg3_get_5755_nvram_info(tp);  in tg3_nvram_init()
14988 		else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_nvram_init()
14989 			 tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_nvram_init()
14990 			 tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_nvram_init()
14991 			tg3_get_5787_nvram_info(tp);  in tg3_nvram_init()
14992 		else if (tg3_asic_rev(tp) == ASIC_REV_5761)  in tg3_nvram_init()
14993 			tg3_get_5761_nvram_info(tp);  in tg3_nvram_init()
14994 		else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_nvram_init()
14995 			tg3_get_5906_nvram_info(tp);  in tg3_nvram_init()
14996 		else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_nvram_init()
14997 			 tg3_flag(tp, 57765_CLASS))  in tg3_nvram_init()
14998 			tg3_get_57780_nvram_info(tp);  in tg3_nvram_init()
14999 		else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_nvram_init()
15000 			 tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_nvram_init()
15001 			tg3_get_5717_nvram_info(tp);  in tg3_nvram_init()
15002 		else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_nvram_init()
15003 			 tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_nvram_init()
15004 			tg3_get_5720_nvram_info(tp);  in tg3_nvram_init()
15006 			tg3_get_nvram_info(tp);  in tg3_nvram_init()
15008 		if (tp->nvram_size == 0)  in tg3_nvram_init()
15009 			tg3_get_nvram_size(tp);  in tg3_nvram_init()
15011 		tg3_disable_nvram_access(tp);  in tg3_nvram_init()
15012 		tg3_nvram_unlock(tp);  in tg3_nvram_init()
15015 		tg3_flag_clear(tp, NVRAM);  in tg3_nvram_init()
15016 		tg3_flag_clear(tp, NVRAM_BUFFERED);  in tg3_nvram_init()
15018 		tg3_get_eeprom_size(tp);  in tg3_nvram_init()
15091 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)  in tg3_lookup_by_subsys()  argument
15097 		     tp->pdev->subsystem_vendor) &&  in tg3_lookup_by_subsys()
15099 		     tp->pdev->subsystem_device))  in tg3_lookup_by_subsys()
15105 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)  in tg3_get_eeprom_hw_cfg()  argument
15109 	tp->phy_id = TG3_PHY_ID_INVALID;  in tg3_get_eeprom_hw_cfg()
15110 	tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15113 	tg3_flag_set(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15114 	tg3_flag_set(tp, WOL_CAP);  in tg3_get_eeprom_hw_cfg()
15116 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_eeprom_hw_cfg()
15118 			tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15119 			tg3_flag_set(tp, IS_NIC);  in tg3_get_eeprom_hw_cfg()
15123 			tg3_flag_set(tp, ASPM_WORKAROUND);  in tg3_get_eeprom_hw_cfg()
15126 			tg3_flag_set(tp, WOL_ENABLE);  in tg3_get_eeprom_hw_cfg()
15127 			device_set_wakeup_enable(&tp->pdev->dev, true);  in tg3_get_eeprom_hw_cfg()
15132 	tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);  in tg3_get_eeprom_hw_cfg()
15139 		tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);  in tg3_get_eeprom_hw_cfg()
15140 		tp->nic_sram_data_cfg = nic_cfg;  in tg3_get_eeprom_hw_cfg()
15142 		tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);  in tg3_get_eeprom_hw_cfg()
15144 		if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_get_eeprom_hw_cfg()
15145 		    tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_get_eeprom_hw_cfg()
15146 		    tg3_asic_rev(tp) != ASIC_REV_5703 &&  in tg3_get_eeprom_hw_cfg()
15148 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);  in tg3_get_eeprom_hw_cfg()
15150 		if (tg3_asic_rev(tp) == ASIC_REV_5785)  in tg3_get_eeprom_hw_cfg()
15151 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);  in tg3_get_eeprom_hw_cfg()
15153 		if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_eeprom_hw_cfg()
15154 		    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_eeprom_hw_cfg()
15155 		    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_get_eeprom_hw_cfg()
15156 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);  in tg3_get_eeprom_hw_cfg()
15162 		tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);  in tg3_get_eeprom_hw_cfg()
15173 		tp->phy_id = eeprom_phy_id;  in tg3_get_eeprom_hw_cfg()
15175 			if (!tg3_flag(tp, 5705_PLUS))  in tg3_get_eeprom_hw_cfg()
15176 				tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_get_eeprom_hw_cfg()
15178 				tp->phy_flags |= TG3_PHYFLG_MII_SERDES;  in tg3_get_eeprom_hw_cfg()
15181 		if (tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15190 			tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15194 			tp->led_ctrl = LED_CTRL_MODE_PHY_2;  in tg3_get_eeprom_hw_cfg()
15198 			tp->led_ctrl = LED_CTRL_MODE_MAC;  in tg3_get_eeprom_hw_cfg()
15203 			if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_eeprom_hw_cfg()
15204 			    tg3_asic_rev(tp) == ASIC_REV_5701)  in tg3_get_eeprom_hw_cfg()
15205 				tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15210 			tp->led_ctrl = LED_CTRL_MODE_SHARED;  in tg3_get_eeprom_hw_cfg()
15211 			if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&  in tg3_get_eeprom_hw_cfg()
15212 			    tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)  in tg3_get_eeprom_hw_cfg()
15213 				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |  in tg3_get_eeprom_hw_cfg()
15216 			if (tg3_flag(tp, 5717_PLUS) ||  in tg3_get_eeprom_hw_cfg()
15217 			    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_eeprom_hw_cfg()
15218 				tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |  in tg3_get_eeprom_hw_cfg()
15224 			tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;  in tg3_get_eeprom_hw_cfg()
15228 			tp->led_ctrl = LED_CTRL_MODE_COMBO;  in tg3_get_eeprom_hw_cfg()
15229 			if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)  in tg3_get_eeprom_hw_cfg()
15230 				tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |  in tg3_get_eeprom_hw_cfg()
15236 		if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_eeprom_hw_cfg()
15237 		     tg3_asic_rev(tp) == ASIC_REV_5701) &&  in tg3_get_eeprom_hw_cfg()
15238 		    tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)  in tg3_get_eeprom_hw_cfg()
15239 			tp->led_ctrl = LED_CTRL_MODE_PHY_2;  in tg3_get_eeprom_hw_cfg()
15241 		if (tg3_chip_rev(tp) == CHIPREV_5784_AX)  in tg3_get_eeprom_hw_cfg()
15242 			tp->led_ctrl = LED_CTRL_MODE_PHY_1;  in tg3_get_eeprom_hw_cfg()
15245 			tg3_flag_set(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15246 			if ((tp->pdev->subsystem_vendor ==  in tg3_get_eeprom_hw_cfg()
15248 			    (tp->pdev->subsystem_device == 0x205a ||  in tg3_get_eeprom_hw_cfg()
15249 			     tp->pdev->subsystem_device == 0x2063))  in tg3_get_eeprom_hw_cfg()
15250 				tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15252 			tg3_flag_clear(tp, EEPROM_WRITE_PROT);  in tg3_get_eeprom_hw_cfg()
15253 			tg3_flag_set(tp, IS_NIC);  in tg3_get_eeprom_hw_cfg()
15257 			tg3_flag_set(tp, ENABLE_ASF);  in tg3_get_eeprom_hw_cfg()
15258 			if (tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15259 				tg3_flag_set(tp, ASF_NEW_HANDSHAKE);  in tg3_get_eeprom_hw_cfg()
15263 		    tg3_flag(tp, 5750_PLUS))  in tg3_get_eeprom_hw_cfg()
15264 			tg3_flag_set(tp, ENABLE_APE);  in tg3_get_eeprom_hw_cfg()
15266 		if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&  in tg3_get_eeprom_hw_cfg()
15268 			tg3_flag_clear(tp, WOL_CAP);  in tg3_get_eeprom_hw_cfg()
15270 		if (tg3_flag(tp, WOL_CAP) &&  in tg3_get_eeprom_hw_cfg()
15272 			tg3_flag_set(tp, WOL_ENABLE);  in tg3_get_eeprom_hw_cfg()
15273 			device_set_wakeup_enable(&tp->pdev->dev, true);  in tg3_get_eeprom_hw_cfg()
15277 			tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;  in tg3_get_eeprom_hw_cfg()
15282 			tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;  in tg3_get_eeprom_hw_cfg()
15284 		if ((tg3_flag(tp, 57765_PLUS) ||  in tg3_get_eeprom_hw_cfg()
15285 		     (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_get_eeprom_hw_cfg()
15286 		      tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&  in tg3_get_eeprom_hw_cfg()
15288 			tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;  in tg3_get_eeprom_hw_cfg()
15290 		if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_get_eeprom_hw_cfg()
15293 			tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);  in tg3_get_eeprom_hw_cfg()
15294 			if (tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_get_eeprom_hw_cfg()
15295 			    !tg3_flag(tp, 57765_PLUS) &&  in tg3_get_eeprom_hw_cfg()
15297 				tg3_flag_set(tp, ASPM_WORKAROUND);  in tg3_get_eeprom_hw_cfg()
15299 				tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;  in tg3_get_eeprom_hw_cfg()
15301 				tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;  in tg3_get_eeprom_hw_cfg()
15305 			tg3_flag_set(tp, RGMII_INBAND_DISABLE);  in tg3_get_eeprom_hw_cfg()
15307 			tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);  in tg3_get_eeprom_hw_cfg()
15309 			tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);  in tg3_get_eeprom_hw_cfg()
15312 			tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;  in tg3_get_eeprom_hw_cfg()
15315 	if (tg3_flag(tp, WOL_CAP))  in tg3_get_eeprom_hw_cfg()
15316 		device_set_wakeup_enable(&tp->pdev->dev,  in tg3_get_eeprom_hw_cfg()
15317 					 tg3_flag(tp, WOL_ENABLE));  in tg3_get_eeprom_hw_cfg()
15319 		device_set_wakeup_capable(&tp->pdev->dev, false);  in tg3_get_eeprom_hw_cfg()
15322 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)  in tg3_ape_otp_read()  argument
15327 	err = tg3_nvram_lock(tp);  in tg3_ape_otp_read()
15331 	tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);  in tg3_ape_otp_read()
15332 	tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |  in tg3_ape_otp_read()
15334 	tg3_ape_read32(tp, TG3_APE_OTP_CTRL);  in tg3_ape_otp_read()
15338 		val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);  in tg3_ape_otp_read()
15340 			*val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);  in tg3_ape_otp_read()
15346 	tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);  in tg3_ape_otp_read()
15348 	tg3_nvram_unlock(tp);  in tg3_ape_otp_read()
15355 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)  in tg3_issue_otp_command()  argument
15378 static u32 tg3_read_otp_phycfg(struct tg3 *tp)  in tg3_read_otp_phycfg()  argument
15384 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))  in tg3_read_otp_phycfg()
15389 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))  in tg3_read_otp_phycfg()
15396 	if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))  in tg3_read_otp_phycfg()
15404 static void tg3_phy_init_link_config(struct tg3 *tp)  in tg3_phy_init_link_config()  argument
15408 	if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {  in tg3_phy_init_link_config()
15409 		if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))  in tg3_phy_init_link_config()
15414 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_phy_init_link_config()
15423 	tp->link_config.advertising = adv;  in tg3_phy_init_link_config()
15424 	tp->link_config.speed = SPEED_UNKNOWN;  in tg3_phy_init_link_config()
15425 	tp->link_config.duplex = DUPLEX_UNKNOWN;  in tg3_phy_init_link_config()
15426 	tp->link_config.autoneg = AUTONEG_ENABLE;  in tg3_phy_init_link_config()
15427 	tp->link_config.active_speed = SPEED_UNKNOWN;  in tg3_phy_init_link_config()
15428 	tp->link_config.active_duplex = DUPLEX_UNKNOWN;  in tg3_phy_init_link_config()
15430 	tp->old_link = -1;  in tg3_phy_init_link_config()
15433 static int tg3_phy_probe(struct tg3 *tp)  in tg3_phy_probe()  argument
15440 	tg3_flag_set(tp, PAUSE_AUTONEG);  in tg3_phy_probe()
15441 	tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;  in tg3_phy_probe()
15443 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_phy_probe()
15444 		switch (tp->pci_fn) {  in tg3_phy_probe()
15446 			tp->phy_ape_lock = TG3_APE_LOCK_PHY0;  in tg3_phy_probe()
15449 			tp->phy_ape_lock = TG3_APE_LOCK_PHY1;  in tg3_phy_probe()
15452 			tp->phy_ape_lock = TG3_APE_LOCK_PHY2;  in tg3_phy_probe()
15455 			tp->phy_ape_lock = TG3_APE_LOCK_PHY3;  in tg3_phy_probe()
15460 	if (!tg3_flag(tp, ENABLE_ASF) &&  in tg3_phy_probe()
15461 	    !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15462 	    !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))  in tg3_phy_probe()
15463 		tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |  in tg3_phy_probe()
15466 	if (tg3_flag(tp, USE_PHYLIB))  in tg3_phy_probe()
15467 		return tg3_phy_init(tp);  in tg3_phy_probe()
15473 	if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {  in tg3_phy_probe()
15481 		err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);  in tg3_phy_probe()
15482 		err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);  in tg3_phy_probe()
15492 		tp->phy_id = hw_phy_id;  in tg3_phy_probe()
15494 			tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15496 			tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15498 		if (tp->phy_id != TG3_PHY_ID_INVALID) {  in tg3_phy_probe()
15508 			p = tg3_lookup_by_subsys(tp);  in tg3_phy_probe()
15510 				tp->phy_id = p->phy_id;  in tg3_phy_probe()
15511 			} else if (!tg3_flag(tp, IS_SSB_CORE)) {  in tg3_phy_probe()
15522 			if (!tp->phy_id ||  in tg3_phy_probe()
15523 			    tp->phy_id == TG3_PHY_ID_BCM8002)  in tg3_phy_probe()
15524 				tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;  in tg3_phy_probe()
15528 	if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15529 	    (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_phy_probe()
15530 	     tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_phy_probe()
15531 	     tg3_asic_rev(tp) == ASIC_REV_57766 ||  in tg3_phy_probe()
15532 	     tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_phy_probe()
15533 	     (tg3_asic_rev(tp) == ASIC_REV_5717 &&  in tg3_phy_probe()
15534 	      tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||  in tg3_phy_probe()
15535 	     (tg3_asic_rev(tp) == ASIC_REV_57765 &&  in tg3_phy_probe()
15536 	      tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {  in tg3_phy_probe()
15537 		tp->phy_flags |= TG3_PHYFLG_EEE_CAP;  in tg3_phy_probe()
15539 		tp->eee.supported = SUPPORTED_100baseT_Full |  in tg3_phy_probe()
15541 		tp->eee.advertised = ADVERTISED_100baseT_Full |  in tg3_phy_probe()
15543 		tp->eee.eee_enabled = 1;  in tg3_phy_probe()
15544 		tp->eee.tx_lpi_enabled = 1;  in tg3_phy_probe()
15545 		tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;  in tg3_phy_probe()
15548 	tg3_phy_init_link_config(tp);  in tg3_phy_probe()
15550 	if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&  in tg3_phy_probe()
15551 	    !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&  in tg3_phy_probe()
15552 	    !tg3_flag(tp, ENABLE_APE) &&  in tg3_phy_probe()
15553 	    !tg3_flag(tp, ENABLE_ASF)) {  in tg3_phy_probe()
15556 		tg3_readphy(tp, MII_BMSR, &bmsr);  in tg3_phy_probe()
15557 		if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&  in tg3_phy_probe()
15561 		err = tg3_phy_reset(tp);  in tg3_phy_probe()
15565 		tg3_phy_set_wirespeed(tp);  in tg3_phy_probe()
15567 		if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {  in tg3_phy_probe()
15568 			tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,  in tg3_phy_probe()
15569 					    tp->link_config.flowctrl);  in tg3_phy_probe()
15571 			tg3_writephy(tp, MII_BMCR,  in tg3_phy_probe()
15577 	if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {  in tg3_phy_probe()
15578 		err = tg3_init_5401phy_dsp(tp);  in tg3_phy_probe()
15582 		err = tg3_init_5401phy_dsp(tp);  in tg3_phy_probe()
15588 static void tg3_read_vpd(struct tg3 *tp)  in tg3_read_vpd()  argument
15594 	vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);  in tg3_read_vpd()
15611 	memset(tp->fw_ver, 0, sizeof(tp->fw_ver));  in tg3_read_vpd()
15612 	snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i);  in tg3_read_vpd()
15623 	memcpy(tp->board_part_number, &vpd_data[i], len);  in tg3_read_vpd()
15627 	if (tp->board_part_number[0])  in tg3_read_vpd()
15631 	if (tg3_asic_rev(tp) == ASIC_REV_5717) {  in tg3_read_vpd()
15632 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_read_vpd()
15633 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)  in tg3_read_vpd()
15634 			strcpy(tp->board_part_number, "BCM5717");  in tg3_read_vpd()
15635 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)  in tg3_read_vpd()
15636 			strcpy(tp->board_part_number, "BCM5718");  in tg3_read_vpd()
15639 	} else if (tg3_asic_rev(tp) == ASIC_REV_57780) {  in tg3_read_vpd()
15640 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)  in tg3_read_vpd()
15641 			strcpy(tp->board_part_number, "BCM57780");  in tg3_read_vpd()
15642 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)  in tg3_read_vpd()
15643 			strcpy(tp->board_part_number, "BCM57760");  in tg3_read_vpd()
15644 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)  in tg3_read_vpd()
15645 			strcpy(tp->board_part_number, "BCM57790");  in tg3_read_vpd()
15646 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)  in tg3_read_vpd()
15647 			strcpy(tp->board_part_number, "BCM57788");  in tg3_read_vpd()
15650 	} else if (tg3_asic_rev(tp) == ASIC_REV_57765) {  in tg3_read_vpd()
15651 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)  in tg3_read_vpd()
15652 			strcpy(tp->board_part_number, "BCM57761");  in tg3_read_vpd()
15653 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)  in tg3_read_vpd()
15654 			strcpy(tp->board_part_number, "BCM57765");  in tg3_read_vpd()
15655 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)  in tg3_read_vpd()
15656 			strcpy(tp->board_part_number, "BCM57781");  in tg3_read_vpd()
15657 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)  in tg3_read_vpd()
15658 			strcpy(tp->board_part_number, "BCM57785");  in tg3_read_vpd()
15659 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)  in tg3_read_vpd()
15660 			strcpy(tp->board_part_number, "BCM57791");  in tg3_read_vpd()
15661 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)  in tg3_read_vpd()
15662 			strcpy(tp->board_part_number, "BCM57795");  in tg3_read_vpd()
15665 	} else if (tg3_asic_rev(tp) == ASIC_REV_57766) {  in tg3_read_vpd()
15666 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)  in tg3_read_vpd()
15667 			strcpy(tp->board_part_number, "BCM57762");  in tg3_read_vpd()
15668 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)  in tg3_read_vpd()
15669 			strcpy(tp->board_part_number, "BCM57766");  in tg3_read_vpd()
15670 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)  in tg3_read_vpd()
15671 			strcpy(tp->board_part_number, "BCM57782");  in tg3_read_vpd()
15672 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)  in tg3_read_vpd()
15673 			strcpy(tp->board_part_number, "BCM57786");  in tg3_read_vpd()
15676 	} else if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_read_vpd()
15677 		strcpy(tp->board_part_number, "BCM95906");  in tg3_read_vpd()
15680 		strcpy(tp->board_part_number, "none");  in tg3_read_vpd()
15684 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)  in tg3_fw_img_is_valid()  argument
15688 	if (tg3_nvram_read(tp, offset, &val) ||  in tg3_fw_img_is_valid()
15690 	    tg3_nvram_read(tp, offset + 4, &val) ||  in tg3_fw_img_is_valid()
15697 static void tg3_read_bc_ver(struct tg3 *tp)  in tg3_read_bc_ver()  argument
15703 	if (tg3_nvram_read(tp, 0xc, &offset) ||  in tg3_read_bc_ver()
15704 	    tg3_nvram_read(tp, 0x4, &start))  in tg3_read_bc_ver()
15707 	offset = tg3_nvram_logical_addr(tp, offset);  in tg3_read_bc_ver()
15709 	if (tg3_nvram_read(tp, offset, &val))  in tg3_read_bc_ver()
15713 		if (tg3_nvram_read(tp, offset + 4, &val))  in tg3_read_bc_ver()
15720 	dst_off = strlen(tp->fw_ver);  in tg3_read_bc_ver()
15724 		    tg3_nvram_read(tp, offset + 8, &ver_offset))  in tg3_read_bc_ver()
15730 			if (tg3_nvram_read_be32(tp, offset + i, &v))  in tg3_read_bc_ver()
15733 			memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));  in tg3_read_bc_ver()
15738 		if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))  in tg3_read_bc_ver()
15744 		snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,  in tg3_read_bc_ver()
15749 static void tg3_read_hwsb_ver(struct tg3 *tp)  in tg3_read_hwsb_ver()  argument
15754 	if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))  in tg3_read_hwsb_ver()
15762 	snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);  in tg3_read_hwsb_ver()
15765 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)  in tg3_read_sb_ver()  argument
15769 	strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);  in tg3_read_sb_ver()
15797 	if (tg3_nvram_read(tp, offset, &val))  in tg3_read_sb_ver()
15809 	offset = strlen(tp->fw_ver);  in tg3_read_sb_ver()
15810 	snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,  in tg3_read_sb_ver()
15814 		offset = strlen(tp->fw_ver);  in tg3_read_sb_ver()
15816 			tp->fw_ver[offset] = 'a' + build - 1;  in tg3_read_sb_ver()
15820 static void tg3_read_mgmtfw_ver(struct tg3 *tp)  in tg3_read_mgmtfw_ver()  argument
15828 		if (tg3_nvram_read(tp, offset, &val))  in tg3_read_mgmtfw_ver()
15838 	if (!tg3_flag(tp, 5705_PLUS))  in tg3_read_mgmtfw_ver()
15840 	else if (tg3_nvram_read(tp, offset - 4, &start))  in tg3_read_mgmtfw_ver()
15843 	if (tg3_nvram_read(tp, offset + 4, &offset) ||  in tg3_read_mgmtfw_ver()
15844 	    !tg3_fw_img_is_valid(tp, offset) ||  in tg3_read_mgmtfw_ver()
15845 	    tg3_nvram_read(tp, offset + 8, &val))  in tg3_read_mgmtfw_ver()
15850 	vlen = strlen(tp->fw_ver);  in tg3_read_mgmtfw_ver()
15852 	tp->fw_ver[vlen++] = ',';  in tg3_read_mgmtfw_ver()
15853 	tp->fw_ver[vlen++] = ' ';  in tg3_read_mgmtfw_ver()
15857 		if (tg3_nvram_read_be32(tp, offset, &v))  in tg3_read_mgmtfw_ver()
15863 			memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);  in tg3_read_mgmtfw_ver()
15867 		memcpy(&tp->fw_ver[vlen], &v, sizeof(v));  in tg3_read_mgmtfw_ver()
15872 static void tg3_probe_ncsi(struct tg3 *tp)  in tg3_probe_ncsi()  argument
15876 	apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);  in tg3_probe_ncsi()
15880 	apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);  in tg3_probe_ncsi()
15884 	if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)  in tg3_probe_ncsi()
15885 		tg3_flag_set(tp, APE_HAS_NCSI);  in tg3_probe_ncsi()
15888 static void tg3_read_dash_ver(struct tg3 *tp)  in tg3_read_dash_ver()  argument
15894 	apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);  in tg3_read_dash_ver()
15896 	if (tg3_flag(tp, APE_HAS_NCSI))  in tg3_read_dash_ver()
15898 	else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)  in tg3_read_dash_ver()
15903 	vlen = strlen(tp->fw_ver);  in tg3_read_dash_ver()
15905 	snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",  in tg3_read_dash_ver()
15913 static void tg3_read_otp_ver(struct tg3 *tp)  in tg3_read_otp_ver()  argument
15917 	if (tg3_asic_rev(tp) != ASIC_REV_5762)  in tg3_read_otp_ver()
15920 	if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&  in tg3_read_otp_ver()
15921 	    !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&  in tg3_read_otp_ver()
15933 		vlen = strlen(tp->fw_ver);  in tg3_read_otp_ver()
15934 		snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);  in tg3_read_otp_ver()
15938 static void tg3_read_fw_ver(struct tg3 *tp)  in tg3_read_fw_ver()  argument
15943 	if (tp->fw_ver[0] != 0)  in tg3_read_fw_ver()
15946 	if (tg3_flag(tp, NO_NVRAM)) {  in tg3_read_fw_ver()
15947 		strcat(tp->fw_ver, "sb");  in tg3_read_fw_ver()
15948 		tg3_read_otp_ver(tp);  in tg3_read_fw_ver()
15952 	if (tg3_nvram_read(tp, 0, &val))  in tg3_read_fw_ver()
15956 		tg3_read_bc_ver(tp);  in tg3_read_fw_ver()
15958 		tg3_read_sb_ver(tp, val);  in tg3_read_fw_ver()
15960 		tg3_read_hwsb_ver(tp);  in tg3_read_fw_ver()
15962 	if (tg3_flag(tp, ENABLE_ASF)) {  in tg3_read_fw_ver()
15963 		if (tg3_flag(tp, ENABLE_APE)) {  in tg3_read_fw_ver()
15964 			tg3_probe_ncsi(tp);  in tg3_read_fw_ver()
15966 				tg3_read_dash_ver(tp);  in tg3_read_fw_ver()
15968 			tg3_read_mgmtfw_ver(tp);  in tg3_read_fw_ver()
15972 	tp->fw_ver[TG3_VER_SIZE - 1] = 0;  in tg3_read_fw_ver()
15975 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)  in tg3_rx_ret_ring_size()  argument
15977 	if (tg3_flag(tp, LRG_PROD_RING_CAP))  in tg3_rx_ret_ring_size()
15979 	else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))  in tg3_rx_ret_ring_size()
15992 static struct pci_dev *tg3_find_peer(struct tg3 *tp)  in tg3_find_peer()  argument
15995 	unsigned int func, devnr = tp->pdev->devfn & ~7;  in tg3_find_peer()
15998 		peer = pci_get_slot(tp->pdev->bus, devnr | func);  in tg3_find_peer()
15999 		if (peer && peer != tp->pdev)  in tg3_find_peer()
16007 		peer = tp->pdev;  in tg3_find_peer()
16020 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)  in tg3_detect_asic_rev()  argument
16022 	tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;  in tg3_detect_asic_rev()
16023 	if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {  in tg3_detect_asic_rev()
16029 		tg3_flag_set(tp, CPMU_PRESENT);  in tg3_detect_asic_rev()
16031 		if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_detect_asic_rev()
16032 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||  in tg3_detect_asic_rev()
16033 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||  in tg3_detect_asic_rev()
16034 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||  in tg3_detect_asic_rev()
16035 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||  in tg3_detect_asic_rev()
16036 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||  in tg3_detect_asic_rev()
16037 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||  in tg3_detect_asic_rev()
16038 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||  in tg3_detect_asic_rev()
16039 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||  in tg3_detect_asic_rev()
16040 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||  in tg3_detect_asic_rev()
16041 		    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)  in tg3_detect_asic_rev()
16043 		else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||  in tg3_detect_asic_rev()
16044 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||  in tg3_detect_asic_rev()
16045 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||  in tg3_detect_asic_rev()
16046 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||  in tg3_detect_asic_rev()
16047 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||  in tg3_detect_asic_rev()
16048 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||  in tg3_detect_asic_rev()
16049 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||  in tg3_detect_asic_rev()
16050 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||  in tg3_detect_asic_rev()
16051 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||  in tg3_detect_asic_rev()
16052 			 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)  in tg3_detect_asic_rev()
16057 		pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);  in tg3_detect_asic_rev()
16063 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)  in tg3_detect_asic_rev()
16064 		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;  in tg3_detect_asic_rev()
16066 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)  in tg3_detect_asic_rev()
16067 		tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;  in tg3_detect_asic_rev()
16069 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_detect_asic_rev()
16070 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_detect_asic_rev()
16071 	    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_detect_asic_rev()
16072 		tg3_flag_set(tp, 5717_PLUS);  in tg3_detect_asic_rev()
16074 	if (tg3_asic_rev(tp) == ASIC_REV_57765 ||  in tg3_detect_asic_rev()
16075 	    tg3_asic_rev(tp) == ASIC_REV_57766)  in tg3_detect_asic_rev()
16076 		tg3_flag_set(tp, 57765_CLASS);  in tg3_detect_asic_rev()
16078 	if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||  in tg3_detect_asic_rev()
16079 	     tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_detect_asic_rev()
16080 		tg3_flag_set(tp, 57765_PLUS);  in tg3_detect_asic_rev()
16083 	if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_detect_asic_rev()
16084 	    tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_detect_asic_rev()
16085 	    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_detect_asic_rev()
16086 	    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_detect_asic_rev()
16087 	    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_detect_asic_rev()
16088 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_detect_asic_rev()
16089 	    tg3_flag(tp, 57765_PLUS))  in tg3_detect_asic_rev()
16090 		tg3_flag_set(tp, 5755_PLUS);  in tg3_detect_asic_rev()
16092 	if (tg3_asic_rev(tp) == ASIC_REV_5780 ||  in tg3_detect_asic_rev()
16093 	    tg3_asic_rev(tp) == ASIC_REV_5714)  in tg3_detect_asic_rev()
16094 		tg3_flag_set(tp, 5780_CLASS);  in tg3_detect_asic_rev()
16096 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_detect_asic_rev()
16097 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_detect_asic_rev()
16098 	    tg3_asic_rev(tp) == ASIC_REV_5906 ||  in tg3_detect_asic_rev()
16099 	    tg3_flag(tp, 5755_PLUS) ||  in tg3_detect_asic_rev()
16100 	    tg3_flag(tp, 5780_CLASS))  in tg3_detect_asic_rev()
16101 		tg3_flag_set(tp, 5750_PLUS);  in tg3_detect_asic_rev()
16103 	if (tg3_asic_rev(tp) == ASIC_REV_5705 ||  in tg3_detect_asic_rev()
16104 	    tg3_flag(tp, 5750_PLUS))  in tg3_detect_asic_rev()
16105 		tg3_flag_set(tp, 5705_PLUS);  in tg3_detect_asic_rev()
16108 static bool tg3_10_100_only_device(struct tg3 *tp,  in tg3_10_100_only_device()  argument
16113 	if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&  in tg3_10_100_only_device()
16115 	    (tp->phy_flags & TG3_PHYFLG_IS_FET))  in tg3_10_100_only_device()
16119 		if (tg3_asic_rev(tp) == ASIC_REV_5705) {  in tg3_10_100_only_device()
16130 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)  in tg3_get_invariants()  argument
16145 	pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16147 	pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16154 	pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16156 	tp->misc_host_ctrl |= (misc_ctrl_reg &  in tg3_get_invariants()
16158 	pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16159 			       tp->misc_host_ctrl);  in tg3_get_invariants()
16161 	tg3_detect_asic_rev(tp, misc_ctrl_reg);  in tg3_get_invariants()
16180 	if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||  in tg3_get_invariants()
16181 	    (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {  in tg3_get_invariants()
16213 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16214 				tg3_flag_set(tp, ICH_WORKAROUND);  in tg3_get_invariants()
16221 	if (tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_get_invariants()
16243 			     tp->pdev->bus->number) &&  in tg3_get_invariants()
16245 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16246 				tg3_flag_set(tp, 5701_DMA_BUG);  in tg3_get_invariants()
16259 	if (tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16260 		tg3_flag_set(tp, 40BIT_DMA_BUG);  in tg3_get_invariants()
16261 		tp->msi_cap = tp->pdev->msi_cap;  in tg3_get_invariants()
16271 			     tp->pdev->bus->number) &&  in tg3_get_invariants()
16273 			     tp->pdev->bus->number)) {  in tg3_get_invariants()
16274 				tg3_flag_set(tp, 40BIT_DMA_BUG);  in tg3_get_invariants()
16281 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_invariants()
16282 	    tg3_asic_rev(tp) == ASIC_REV_5714)  in tg3_get_invariants()
16283 		tp->pdev_peer = tg3_find_peer(tp);  in tg3_get_invariants()
16286 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)  in tg3_get_invariants()
16288 	else if (tg3_flag(tp, 57765_PLUS))  in tg3_get_invariants()
16289 		tg3_flag_set(tp, HW_TSO_3);  in tg3_get_invariants()
16290 	else if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16291 		 tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16292 		tg3_flag_set(tp, HW_TSO_2);  in tg3_get_invariants()
16293 	else if (tg3_flag(tp, 5750_PLUS)) {  in tg3_get_invariants()
16294 		tg3_flag_set(tp, HW_TSO_1);  in tg3_get_invariants()
16295 		tg3_flag_set(tp, TSO_BUG);  in tg3_get_invariants()
16296 		if (tg3_asic_rev(tp) == ASIC_REV_5750 &&  in tg3_get_invariants()
16297 		    tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)  in tg3_get_invariants()
16298 			tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16299 	} else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_get_invariants()
16300 		   tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_get_invariants()
16301 		   tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {  in tg3_get_invariants()
16302 		tg3_flag_set(tp, FW_TSO);  in tg3_get_invariants()
16303 		tg3_flag_set(tp, TSO_BUG);  in tg3_get_invariants()
16304 		if (tg3_asic_rev(tp) == ASIC_REV_5705)  in tg3_get_invariants()
16305 			tp->fw_needed = FIRMWARE_TG3TSO5;  in tg3_get_invariants()
16307 			tp->fw_needed = FIRMWARE_TG3TSO;  in tg3_get_invariants()
16311 	if (tg3_flag(tp, HW_TSO_1) ||  in tg3_get_invariants()
16312 	    tg3_flag(tp, HW_TSO_2) ||  in tg3_get_invariants()
16313 	    tg3_flag(tp, HW_TSO_3) ||  in tg3_get_invariants()
16314 	    tg3_flag(tp, FW_TSO)) {  in tg3_get_invariants()
16319 		tg3_flag_set(tp, TSO_CAPABLE);  in tg3_get_invariants()
16321 		tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16322 		tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16323 		tp->fw_needed = NULL;  in tg3_get_invariants()
16326 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)  in tg3_get_invariants()
16327 		tp->fw_needed = FIRMWARE_TG3;  in tg3_get_invariants()
16329 	if (tg3_asic_rev(tp) == ASIC_REV_57766)  in tg3_get_invariants()
16330 		tp->fw_needed = FIRMWARE_TG357766;  in tg3_get_invariants()
16332 	tp->irq_max = 1;  in tg3_get_invariants()
16334 	if (tg3_flag(tp, 5750_PLUS)) {  in tg3_get_invariants()
16335 		tg3_flag_set(tp, SUPPORT_MSI);  in tg3_get_invariants()
16336 		if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||  in tg3_get_invariants()
16337 		    tg3_chip_rev(tp) == CHIPREV_5750_BX ||  in tg3_get_invariants()
16338 		    (tg3_asic_rev(tp) == ASIC_REV_5714 &&  in tg3_get_invariants()
16339 		     tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&  in tg3_get_invariants()
16340 		     tp->pdev_peer == tp->pdev))  in tg3_get_invariants()
16341 			tg3_flag_clear(tp, SUPPORT_MSI);  in tg3_get_invariants()
16343 		if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16344 		    tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16345 			tg3_flag_set(tp, 1SHOT_MSI);  in tg3_get_invariants()
16348 		if (tg3_flag(tp, 57765_PLUS)) {  in tg3_get_invariants()
16349 			tg3_flag_set(tp, SUPPORT_MSIX);  in tg3_get_invariants()
16350 			tp->irq_max = TG3_IRQ_MAX_VECS;  in tg3_get_invariants()
16354 	tp->txq_max = 1;  in tg3_get_invariants()
16355 	tp->rxq_max = 1;  in tg3_get_invariants()
16356 	if (tp->irq_max > 1) {  in tg3_get_invariants()
16357 		tp->rxq_max = TG3_RSS_MAX_NUM_QS;  in tg3_get_invariants()
16358 		tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);  in tg3_get_invariants()
16360 		if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16361 		    tg3_asic_rev(tp) == ASIC_REV_5720)  in tg3_get_invariants()
16362 			tp->txq_max = tp->irq_max - 1;  in tg3_get_invariants()
16365 	if (tg3_flag(tp, 5755_PLUS) ||  in tg3_get_invariants()
16366 	    tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16367 		tg3_flag_set(tp, SHORT_DMA_BUG);  in tg3_get_invariants()
16369 	if (tg3_asic_rev(tp) == ASIC_REV_5719)  in tg3_get_invariants()
16370 		tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;  in tg3_get_invariants()
16372 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16373 	    tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16374 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_get_invariants()
16375 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16376 		tg3_flag_set(tp, LRG_PROD_RING_CAP);  in tg3_get_invariants()
16378 	if (tg3_flag(tp, 57765_PLUS) &&  in tg3_get_invariants()
16379 	    tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)  in tg3_get_invariants()
16380 		tg3_flag_set(tp, USE_JUMBO_BDFLAG);  in tg3_get_invariants()
16382 	if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_get_invariants()
16383 	    tg3_flag(tp, 5780_CLASS) ||  in tg3_get_invariants()
16384 	    tg3_flag(tp, USE_JUMBO_BDFLAG))  in tg3_get_invariants()
16385 		tg3_flag_set(tp, JUMBO_CAPABLE);  in tg3_get_invariants()
16387 	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16390 	if (pci_is_pcie(tp->pdev)) {  in tg3_get_invariants()
16393 		tg3_flag_set(tp, PCI_EXPRESS);  in tg3_get_invariants()
16395 		pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);  in tg3_get_invariants()
16397 			if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16398 				tg3_flag_clear(tp, HW_TSO_2);  in tg3_get_invariants()
16399 				tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16401 			if (tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_get_invariants()
16402 			    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_get_invariants()
16403 			    tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||  in tg3_get_invariants()
16404 			    tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)  in tg3_get_invariants()
16405 				tg3_flag_set(tp, CLKREQ_BUG);  in tg3_get_invariants()
16406 		} else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {  in tg3_get_invariants()
16407 			tg3_flag_set(tp, L1PLLPD_EN);  in tg3_get_invariants()
16409 	} else if (tg3_asic_rev(tp) == ASIC_REV_5785) {  in tg3_get_invariants()
16414 		tg3_flag_set(tp, PCI_EXPRESS);  in tg3_get_invariants()
16415 	} else if (!tg3_flag(tp, 5705_PLUS) ||  in tg3_get_invariants()
16416 		   tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16417 		tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);  in tg3_get_invariants()
16418 		if (!tp->pcix_cap) {  in tg3_get_invariants()
16419 			dev_err(&tp->pdev->dev,  in tg3_get_invariants()
16425 			tg3_flag_set(tp, PCIX_MODE);  in tg3_get_invariants()
16435 	    !tg3_flag(tp, PCI_EXPRESS))  in tg3_get_invariants()
16436 		tg3_flag_set(tp, MBOX_WRITE_REORDER);  in tg3_get_invariants()
16438 	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,  in tg3_get_invariants()
16439 			     &tp->pci_cacheline_sz);  in tg3_get_invariants()
16440 	pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_get_invariants()
16441 			     &tp->pci_lat_timer);  in tg3_get_invariants()
16442 	if (tg3_asic_rev(tp) == ASIC_REV_5703 &&  in tg3_get_invariants()
16443 	    tp->pci_lat_timer < 64) {  in tg3_get_invariants()
16444 		tp->pci_lat_timer = 64;  in tg3_get_invariants()
16445 		pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,  in tg3_get_invariants()
16446 				      tp->pci_lat_timer);  in tg3_get_invariants()
16452 	if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {  in tg3_get_invariants()
16456 		tg3_flag_set(tp, TXD_MBOX_HWBUG);  in tg3_get_invariants()
16463 		if (tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16466 			tg3_flag_set(tp, PCIX_TARGET_HWBUG);  in tg3_get_invariants()
16472 			pci_read_config_dword(tp->pdev,  in tg3_get_invariants()
16473 					      tp->pdev->pm_cap + PCI_PM_CTRL,  in tg3_get_invariants()
16477 			pci_write_config_dword(tp->pdev,  in tg3_get_invariants()
16478 					       tp->pdev->pm_cap + PCI_PM_CTRL,  in tg3_get_invariants()
16482 			pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16484 			pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16489 		tg3_flag_set(tp, PCI_HIGH_SPEED);  in tg3_get_invariants()
16491 		tg3_flag_set(tp, PCI_32BIT);  in tg3_get_invariants()
16494 	if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&  in tg3_get_invariants()
16497 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);  in tg3_get_invariants()
16501 	tp->read32 = tg3_read32;  in tg3_get_invariants()
16502 	tp->write32 = tg3_write32;  in tg3_get_invariants()
16503 	tp->read32_mbox = tg3_read32;  in tg3_get_invariants()
16504 	tp->write32_mbox = tg3_write32;  in tg3_get_invariants()
16505 	tp->write32_tx_mbox = tg3_write32;  in tg3_get_invariants()
16506 	tp->write32_rx_mbox = tg3_write32;  in tg3_get_invariants()
16509 	if (tg3_flag(tp, PCIX_TARGET_HWBUG))  in tg3_get_invariants()
16510 		tp->write32 = tg3_write_indirect_reg32;  in tg3_get_invariants()
16511 	else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||  in tg3_get_invariants()
16512 		 (tg3_flag(tp, PCI_EXPRESS) &&  in tg3_get_invariants()
16513 		  tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {  in tg3_get_invariants()
16521 		tp->write32 = tg3_write_flush_reg32;  in tg3_get_invariants()
16524 	if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {  in tg3_get_invariants()
16525 		tp->write32_tx_mbox = tg3_write32_tx_mbox;  in tg3_get_invariants()
16526 		if (tg3_flag(tp, MBOX_WRITE_REORDER))  in tg3_get_invariants()
16527 			tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16530 	if (tg3_flag(tp, ICH_WORKAROUND)) {  in tg3_get_invariants()
16531 		tp->read32 = tg3_read_indirect_reg32;  in tg3_get_invariants()
16532 		tp->write32 = tg3_write_indirect_reg32;  in tg3_get_invariants()
16533 		tp->read32_mbox = tg3_read_indirect_mbox;  in tg3_get_invariants()
16534 		tp->write32_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16535 		tp->write32_tx_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16536 		tp->write32_rx_mbox = tg3_write_indirect_mbox;  in tg3_get_invariants()
16538 		iounmap(tp->regs);  in tg3_get_invariants()
16539 		tp->regs = NULL;  in tg3_get_invariants()
16541 		pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);  in tg3_get_invariants()
16543 		pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);  in tg3_get_invariants()
16545 	if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_get_invariants()
16546 		tp->read32_mbox = tg3_read32_mbox_5906;  in tg3_get_invariants()
16547 		tp->write32_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16548 		tp->write32_tx_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16549 		tp->write32_rx_mbox = tg3_write32_mbox_5906;  in tg3_get_invariants()
16552 	if (tp->write32 == tg3_write_indirect_reg32 ||  in tg3_get_invariants()
16553 	    (tg3_flag(tp, PCIX_MODE) &&  in tg3_get_invariants()
16554 	     (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16555 	      tg3_asic_rev(tp) == ASIC_REV_5701)))  in tg3_get_invariants()
16556 		tg3_flag_set(tp, SRAM_USE_CONFIG);  in tg3_get_invariants()
16566 	tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;  in tg3_get_invariants()
16567 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_invariants()
16568 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_invariants()
16569 		if (tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16570 			pci_read_config_dword(tp->pdev,  in tg3_get_invariants()
16571 					      tp->pcix_cap + PCI_X_STATUS,  in tg3_get_invariants()
16573 			tp->pci_fn = val & 0x7;  in tg3_get_invariants()
16575 	} else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16576 		   tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_get_invariants()
16577 		   tg3_asic_rev(tp) == ASIC_REV_5720) {  in tg3_get_invariants()
16578 		tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);  in tg3_get_invariants()
16582 		if (tg3_asic_rev(tp) == ASIC_REV_5717)  in tg3_get_invariants()
16583 			tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;  in tg3_get_invariants()
16585 			tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>  in tg3_get_invariants()
16589 	if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {  in tg3_get_invariants()
16590 		tp->write32_tx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16591 		tp->write32_rx_mbox = tg3_write_flush_reg32;  in tg3_get_invariants()
16602 	tg3_get_eeprom_hw_cfg(tp);  in tg3_get_invariants()
16604 	if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {  in tg3_get_invariants()
16605 		tg3_flag_clear(tp, TSO_CAPABLE);  in tg3_get_invariants()
16606 		tg3_flag_clear(tp, TSO_BUG);  in tg3_get_invariants()
16607 		tp->fw_needed = NULL;  in tg3_get_invariants()
16610 	if (tg3_flag(tp, ENABLE_APE)) {  in tg3_get_invariants()
16617 		pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16620 		tg3_ape_lock_init(tp);  in tg3_get_invariants()
16621 		tp->ape_hb_interval =  in tg3_get_invariants()
16630 	tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;  in tg3_get_invariants()
16631 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16632 	    tg3_flag(tp, EEPROM_WRITE_PROT))  in tg3_get_invariants()
16633 		tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |  in tg3_get_invariants()
16638 	else if (tg3_asic_rev(tp) == ASIC_REV_5752)  in tg3_get_invariants()
16639 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;  in tg3_get_invariants()
16641 	if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_get_invariants()
16642 	    tg3_asic_rev(tp) == ASIC_REV_57780 ||  in tg3_get_invariants()
16643 	    tg3_flag(tp, 57765_CLASS))  in tg3_get_invariants()
16644 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;  in tg3_get_invariants()
16646 	if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_get_invariants()
16647 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {  in tg3_get_invariants()
16649 		tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;  in tg3_get_invariants()
16650 		if (tg3_flag(tp, IS_NIC))  in tg3_get_invariants()
16652 			tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |  in tg3_get_invariants()
16656 	if (tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16657 		tp->grc_local_ctrl |=  in tg3_get_invariants()
16661 	tg3_pwrsrc_switch_to_vmain(tp);  in tg3_get_invariants()
16666 	if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))  in tg3_get_invariants()
16667 		tg3_flag_set(tp, JUMBO_RING_ENABLE);  in tg3_get_invariants()
16670 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16671 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_get_invariants()
16672 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||  in tg3_get_invariants()
16673 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {  in tg3_get_invariants()
16674 		tg3_flag_clear(tp, WOL_SPEED_100MB);  in tg3_get_invariants()
16676 		tg3_flag_set(tp, WOL_SPEED_100MB);  in tg3_get_invariants()
16679 	if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_invariants()
16680 		tp->phy_flags |= TG3_PHYFLG_IS_FET;  in tg3_get_invariants()
16683 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_get_invariants()
16684 	    (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_get_invariants()
16685 	     (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&  in tg3_get_invariants()
16686 	     (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||  in tg3_get_invariants()
16687 	    (tp->phy_flags & TG3_PHYFLG_IS_FET) ||  in tg3_get_invariants()
16688 	    (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))  in tg3_get_invariants()
16689 		tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;  in tg3_get_invariants()
16691 	if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||  in tg3_get_invariants()
16692 	    tg3_chip_rev(tp) == CHIPREV_5704_AX)  in tg3_get_invariants()
16693 		tp->phy_flags |= TG3_PHYFLG_ADC_BUG;  in tg3_get_invariants()
16694 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)  in tg3_get_invariants()
16695 		tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;  in tg3_get_invariants()
16697 	if (tg3_flag(tp, 5705_PLUS) &&  in tg3_get_invariants()
16698 	    !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&  in tg3_get_invariants()
16699 	    tg3_asic_rev(tp) != ASIC_REV_5785 &&  in tg3_get_invariants()
16700 	    tg3_asic_rev(tp) != ASIC_REV_57780 &&  in tg3_get_invariants()
16701 	    !tg3_flag(tp, 57765_PLUS)) {  in tg3_get_invariants()
16702 		if (tg3_asic_rev(tp) == ASIC_REV_5755 ||  in tg3_get_invariants()
16703 		    tg3_asic_rev(tp) == ASIC_REV_5787 ||  in tg3_get_invariants()
16704 		    tg3_asic_rev(tp) == ASIC_REV_5784 ||  in tg3_get_invariants()
16705 		    tg3_asic_rev(tp) == ASIC_REV_5761) {  in tg3_get_invariants()
16706 			if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&  in tg3_get_invariants()
16707 			    tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)  in tg3_get_invariants()
16708 				tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;  in tg3_get_invariants()
16709 			if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)  in tg3_get_invariants()
16710 				tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;  in tg3_get_invariants()
16712 			tp->phy_flags |= TG3_PHYFLG_BER_BUG;  in tg3_get_invariants()
16715 	if (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_get_invariants()
16716 	    tg3_chip_rev(tp) != CHIPREV_5784_AX) {  in tg3_get_invariants()
16717 		tp->phy_otp = tg3_read_otp_phycfg(tp);  in tg3_get_invariants()
16718 		if (tp->phy_otp == 0)  in tg3_get_invariants()
16719 			tp->phy_otp = TG3_OTP_DEFAULT;  in tg3_get_invariants()
16722 	if (tg3_flag(tp, CPMU_PRESENT))  in tg3_get_invariants()
16723 		tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;  in tg3_get_invariants()
16725 		tp->mi_mode = MAC_MI_MODE_BASE;  in tg3_get_invariants()
16727 	tp->coalesce_mode = 0;  in tg3_get_invariants()
16728 	if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&  in tg3_get_invariants()
16729 	    tg3_chip_rev(tp) != CHIPREV_5700_BX)  in tg3_get_invariants()
16730 		tp->coalesce_mode |= HOSTCC_MODE_32BYTE;  in tg3_get_invariants()
16733 	if (tg3_asic_rev(tp) == ASIC_REV_5717 ||  in tg3_get_invariants()
16734 	    tg3_asic_rev(tp) == ASIC_REV_5762 ||  in tg3_get_invariants()
16735 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||  in tg3_get_invariants()
16736 	    tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {  in tg3_get_invariants()
16737 		tp->coalesce_mode |= HOSTCC_MODE_ATTN;  in tg3_get_invariants()
16738 		tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;  in tg3_get_invariants()
16741 	if (tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_get_invariants()
16742 	    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_get_invariants()
16743 		tg3_flag_set(tp, USE_PHYLIB);  in tg3_get_invariants()
16745 	err = tg3_mdio_init(tp);  in tg3_get_invariants()
16751 	if (tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_get_invariants()
16752 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_get_invariants()
16761 	tw32(GRC_MODE, val | tp->grc_mode);  in tg3_get_invariants()
16763 	tg3_switch_clocks(tp);  in tg3_get_invariants()
16771 	pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,  in tg3_get_invariants()
16774 	    !tg3_flag(tp, PCIX_TARGET_HWBUG)) {  in tg3_get_invariants()
16775 		if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||  in tg3_get_invariants()
16776 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||  in tg3_get_invariants()
16777 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||  in tg3_get_invariants()
16778 		    tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {  in tg3_get_invariants()
16785 			sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;  in tg3_get_invariants()
16791 				tg3_flag_set(tp, PCIX_TARGET_HWBUG);  in tg3_get_invariants()
16796 	tg3_nvram_init(tp);  in tg3_get_invariants()
16799 	if (tg3_asic_rev(tp) == ASIC_REV_57766 &&  in tg3_get_invariants()
16800 	    !tg3_flag(tp, NO_NVRAM))  in tg3_get_invariants()
16801 		tp->fw_needed = NULL;  in tg3_get_invariants()
16806 	if (tg3_asic_rev(tp) == ASIC_REV_5705 &&  in tg3_get_invariants()
16809 		tg3_flag_set(tp, IS_5788);  in tg3_get_invariants()
16811 	if (!tg3_flag(tp, IS_5788) &&  in tg3_get_invariants()
16812 	    tg3_asic_rev(tp) != ASIC_REV_5700)  in tg3_get_invariants()
16813 		tg3_flag_set(tp, TAGGED_STATUS);  in tg3_get_invariants()
16814 	if (tg3_flag(tp, TAGGED_STATUS)) {  in tg3_get_invariants()
16815 		tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |  in tg3_get_invariants()
16818 		tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;  in tg3_get_invariants()
16819 		pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,  in tg3_get_invariants()
16820 				       tp->misc_host_ctrl);  in tg3_get_invariants()
16824 	if (tg3_flag(tp, ENABLE_APE))  in tg3_get_invariants()
16825 		tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;  in tg3_get_invariants()
16827 		tp->mac_mode = 0;  in tg3_get_invariants()
16829 	if (tg3_10_100_only_device(tp, ent))  in tg3_get_invariants()
16830 		tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;  in tg3_get_invariants()
16832 	err = tg3_phy_probe(tp);  in tg3_get_invariants()
16834 		dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);  in tg3_get_invariants()
16836 		tg3_mdio_fini(tp);  in tg3_get_invariants()
16839 	tg3_read_vpd(tp);  in tg3_get_invariants()
16840 	tg3_read_fw_ver(tp);  in tg3_get_invariants()
16842 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {  in tg3_get_invariants()
16843 		tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16845 		if (tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_get_invariants()
16846 			tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16848 			tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16855 	if (tg3_asic_rev(tp) == ASIC_REV_5700)  in tg3_get_invariants()
16856 		tg3_flag_set(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16858 		tg3_flag_clear(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16864 	if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&  in tg3_get_invariants()
16865 	    tg3_asic_rev(tp) == ASIC_REV_5701 &&  in tg3_get_invariants()
16866 	    !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {  in tg3_get_invariants()
16867 		tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;  in tg3_get_invariants()
16868 		tg3_flag_set(tp, USE_LINKCHG_REG);  in tg3_get_invariants()
16872 	if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)  in tg3_get_invariants()
16873 		tg3_flag_set(tp, POLL_SERDES);  in tg3_get_invariants()
16875 		tg3_flag_clear(tp, POLL_SERDES);  in tg3_get_invariants()
16877 	if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))  in tg3_get_invariants()
16878 		tg3_flag_set(tp, POLL_CPMU_LINK);  in tg3_get_invariants()
16880 	tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;  in tg3_get_invariants()
16881 	tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;  in tg3_get_invariants()
16882 	if (tg3_asic_rev(tp) == ASIC_REV_5701 &&  in tg3_get_invariants()
16883 	    tg3_flag(tp, PCIX_MODE)) {  in tg3_get_invariants()
16884 		tp->rx_offset = NET_SKB_PAD;  in tg3_get_invariants()
16886 		tp->rx_copy_thresh = ~(u16)0;  in tg3_get_invariants()
16890 	tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;  in tg3_get_invariants()
16891 	tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;  in tg3_get_invariants()
16892 	tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;  in tg3_get_invariants()
16894 	tp->rx_std_max_post = tp->rx_std_ring_mask + 1;  in tg3_get_invariants()
16899 	if (tg3_asic_rev(tp) == ASIC_REV_5750 ||  in tg3_get_invariants()
16900 	    tg3_asic_rev(tp) == ASIC_REV_5752 ||  in tg3_get_invariants()
16901 	    tg3_asic_rev(tp) == ASIC_REV_5755)  in tg3_get_invariants()
16902 		tp->rx_std_max_post = 8;  in tg3_get_invariants()
16904 	if (tg3_flag(tp, ASPM_WORKAROUND))  in tg3_get_invariants()
16905 		tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &  in tg3_get_invariants()
16911 static int tg3_get_device_address(struct tg3 *tp, u8 *addr)  in tg3_get_device_address()  argument
16917 	if (!eth_platform_get_mac_address(&tp->pdev->dev, addr))  in tg3_get_device_address()
16920 	if (tg3_flag(tp, IS_SSB_CORE)) {  in tg3_get_device_address()
16921 		err = ssb_gige_get_macaddr(tp->pdev, addr);  in tg3_get_device_address()
16927 	if (tg3_asic_rev(tp) == ASIC_REV_5704 ||  in tg3_get_device_address()
16928 	    tg3_flag(tp, 5780_CLASS)) {  in tg3_get_device_address()
16931 		if (tg3_nvram_lock(tp))  in tg3_get_device_address()
16934 			tg3_nvram_unlock(tp);  in tg3_get_device_address()
16935 	} else if (tg3_flag(tp, 5717_PLUS)) {  in tg3_get_device_address()
16936 		if (tp->pci_fn & 1)  in tg3_get_device_address()
16938 		if (tp->pci_fn > 1)  in tg3_get_device_address()
16940 	} else if (tg3_asic_rev(tp) == ASIC_REV_5906)  in tg3_get_device_address()
16944 	tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);  in tg3_get_device_address()
16949 		tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);  in tg3_get_device_address()
16960 		if (!tg3_flag(tp, NO_NVRAM) &&  in tg3_get_device_address()
16961 		    !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&  in tg3_get_device_address()
16962 		    !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {  in tg3_get_device_address()
16988 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)  in tg3_calc_dma_bndry()  argument
16994 	pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);  in tg3_calc_dma_bndry()
17003 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_calc_dma_bndry()
17004 	    tg3_asic_rev(tp) != ASIC_REV_5701 &&  in tg3_calc_dma_bndry()
17005 	    !tg3_flag(tp, PCI_EXPRESS))  in tg3_calc_dma_bndry()
17018 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_calc_dma_bndry()
17037 	if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {  in tg3_calc_dma_bndry()
17062 	} else if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_calc_dma_bndry()
17129 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,  in tg3_do_test_dma()  argument
17180 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,  in tg3_do_test_dma()
17182 		pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);  in tg3_do_test_dma()
17184 	pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);  in tg3_do_test_dma()
17217 static int tg3_test_dma(struct tg3 *tp)  in tg3_test_dma()  argument
17223 	buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,  in tg3_test_dma()
17230 	tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |  in tg3_test_dma()
17233 	tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);  in tg3_test_dma()
17235 	if (tg3_flag(tp, 57765_PLUS))  in tg3_test_dma()
17238 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_test_dma()
17240 		tp->dma_rwctrl |= 0x00180000;  in tg3_test_dma()
17241 	} else if (!tg3_flag(tp, PCIX_MODE)) {  in tg3_test_dma()
17242 		if (tg3_asic_rev(tp) == ASIC_REV_5705 ||  in tg3_test_dma()
17243 		    tg3_asic_rev(tp) == ASIC_REV_5750)  in tg3_test_dma()
17244 			tp->dma_rwctrl |= 0x003f0000;  in tg3_test_dma()
17246 			tp->dma_rwctrl |= 0x003f000f;  in tg3_test_dma()
17248 		if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_test_dma()
17249 		    tg3_asic_rev(tp) == ASIC_REV_5704) {  in tg3_test_dma()
17257 			if (tg3_flag(tp, 40BIT_DMA_BUG) &&  in tg3_test_dma()
17258 			    tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_test_dma()
17259 				tp->dma_rwctrl |= 0x8000;  in tg3_test_dma()
17261 				tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;  in tg3_test_dma()
17263 			if (tg3_asic_rev(tp) == ASIC_REV_5703)  in tg3_test_dma()
17266 			tp->dma_rwctrl |=  in tg3_test_dma()
17270 		} else if (tg3_asic_rev(tp) == ASIC_REV_5780) {  in tg3_test_dma()
17272 			tp->dma_rwctrl |= 0x00144000;  in tg3_test_dma()
17273 		} else if (tg3_asic_rev(tp) == ASIC_REV_5714) {  in tg3_test_dma()
17275 			tp->dma_rwctrl |= 0x00148000;  in tg3_test_dma()
17277 			tp->dma_rwctrl |= 0x001b000f;  in tg3_test_dma()
17280 	if (tg3_flag(tp, ONE_DMA_AT_ONCE))  in tg3_test_dma()
17281 		tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;  in tg3_test_dma()
17283 	if (tg3_asic_rev(tp) == ASIC_REV_5703 ||  in tg3_test_dma()
17284 	    tg3_asic_rev(tp) == ASIC_REV_5704)  in tg3_test_dma()
17285 		tp->dma_rwctrl &= 0xfffffff0;  in tg3_test_dma()
17287 	if (tg3_asic_rev(tp) == ASIC_REV_5700 ||  in tg3_test_dma()
17288 	    tg3_asic_rev(tp) == ASIC_REV_5701) {  in tg3_test_dma()
17290 		tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;  in tg3_test_dma()
17302 		tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;  in tg3_test_dma()
17305 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17308 	if (tg3_asic_rev(tp) != ASIC_REV_5700 &&  in tg3_test_dma()
17309 	    tg3_asic_rev(tp) != ASIC_REV_5701)  in tg3_test_dma()
17315 	saved_dma_rwctrl = tp->dma_rwctrl;  in tg3_test_dma()
17316 	tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17317 	tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17326 		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);  in tg3_test_dma()
17328 			dev_err(&tp->pdev->dev,  in tg3_test_dma()
17335 		ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);  in tg3_test_dma()
17337 			dev_err(&tp->pdev->dev, "%s: Buffer read failed. "  in tg3_test_dma()
17347 			if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=  in tg3_test_dma()
17349 				tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17350 				tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;  in tg3_test_dma()
17351 				tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17354 				dev_err(&tp->pdev->dev,  in tg3_test_dma()
17368 	if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=  in tg3_test_dma()
17375 			tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;  in tg3_test_dma()
17376 			tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;  in tg3_test_dma()
17379 			tp->dma_rwctrl = saved_dma_rwctrl;  in tg3_test_dma()
17382 		tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);  in tg3_test_dma()
17386 	dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);  in tg3_test_dma()
17391 static void tg3_init_bufmgr_config(struct tg3 *tp)  in tg3_init_bufmgr_config()  argument
17393 	if (tg3_flag(tp, 57765_PLUS)) {  in tg3_init_bufmgr_config()
17394 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17396 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17398 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17401 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17403 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17405 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17407 	} else if (tg3_flag(tp, 5705_PLUS)) {  in tg3_init_bufmgr_config()
17408 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17410 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17412 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17414 		if (tg3_asic_rev(tp) == ASIC_REV_5906) {  in tg3_init_bufmgr_config()
17415 			tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17417 			tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17421 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17423 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17425 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17428 		tp->bufmgr_config.mbuf_read_dma_low_water =  in tg3_init_bufmgr_config()
17430 		tp->bufmgr_config.mbuf_mac_rx_low_water =  in tg3_init_bufmgr_config()
17432 		tp->bufmgr_config.mbuf_high_water =  in tg3_init_bufmgr_config()
17435 		tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =  in tg3_init_bufmgr_config()
17437 		tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =  in tg3_init_bufmgr_config()
17439 		tp->bufmgr_config.mbuf_high_water_jumbo =  in tg3_init_bufmgr_config()
17443 	tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;  in tg3_init_bufmgr_config()
17444 	tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;  in tg3_init_bufmgr_config()
17447 static char *tg3_phy_string(struct tg3 *tp)  in tg3_phy_string()  argument
17449 	switch (tp->phy_id & TG3_PHY_ID_MASK) {  in tg3_phy_string()
17479 static char *tg3_bus_string(struct tg3 *tp, char *str)  in tg3_bus_string()  argument
17481 	if (tg3_flag(tp, PCI_EXPRESS)) {  in tg3_bus_string()
17484 	} else if (tg3_flag(tp, PCIX_MODE)) {  in tg3_bus_string()
17503 		if (tg3_flag(tp, PCI_HIGH_SPEED))  in tg3_bus_string()
17508 	if (tg3_flag(tp, PCI_32BIT))  in tg3_bus_string()
17515 static void tg3_init_coal(struct tg3 *tp)  in tg3_init_coal()  argument
17517 	struct ethtool_coalesce *ec = &tp->coal;  in tg3_init_coal()
17531 	if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |  in tg3_init_coal()
17539 	if (tg3_flag(tp, 5705_PLUS)) {  in tg3_init_coal()
17550 	struct tg3 *tp;  in tg3_init_one()  local
17572 	dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);  in tg3_init_one()
17580 	tp = netdev_priv(dev);  in tg3_init_one()
17581 	tp->pdev = pdev;  in tg3_init_one()
17582 	tp->dev = dev;  in tg3_init_one()
17583 	tp->rx_mode = TG3_DEF_RX_MODE;  in tg3_init_one()
17584 	tp->tx_mode = TG3_DEF_TX_MODE;  in tg3_init_one()
17585 	tp->irq_sync = 1;  in tg3_init_one()
17586 	tp->pcierr_recovery = false;  in tg3_init_one()
17589 		tp->msg_enable = tg3_debug;  in tg3_init_one()
17591 		tp->msg_enable = TG3_DEF_MSG_ENABLE;  in tg3_init_one()
17594 		tg3_flag_set(tp, IS_SSB_CORE);  in tg3_init_one()
17596 			tg3_flag_set(tp, FLUSH_POSTED_WRITES);  in tg3_init_one()
17598 			tg3_flag_set(tp, ONE_DMA_AT_ONCE);  in tg3_init_one()
17600 			tg3_flag_set(tp, USE_PHYLIB);  in tg3_init_one()
17601 			tg3_flag_set(tp, ROBOSWITCH);  in tg3_init_one()
17604 			tg3_flag_set(tp, RGMII_MODE);  in tg3_init_one()
17611 	tp->misc_host_ctrl =  in tg3_init_one()
17623 	tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |  in tg3_init_one()
17626 	tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;  in tg3_init_one()
17628 	spin_lock_init(&tp->lock);  in tg3_init_one()
17629 	spin_lock_init(&tp->indirect_lock);  in tg3_init_one()
17630 	INIT_WORK(&tp->reset_task, tg3_reset_task);  in tg3_init_one()
17632 	tp->regs = pci_ioremap_bar(pdev, BAR_0);  in tg3_init_one()
17633 	if (!tp->regs) {  in tg3_init_one()
17639 	if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||  in tg3_init_one()
17640 	    tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||  in tg3_init_one()
17641 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||  in tg3_init_one()
17642 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||  in tg3_init_one()
17643 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||  in tg3_init_one()
17644 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||  in tg3_init_one()
17645 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||  in tg3_init_one()
17646 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||  in tg3_init_one()
17647 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||  in tg3_init_one()
17648 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||  in tg3_init_one()
17649 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||  in tg3_init_one()
17650 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||  in tg3_init_one()
17651 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||  in tg3_init_one()
17652 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||  in tg3_init_one()
17653 	    tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {  in tg3_init_one()
17654 		tg3_flag_set(tp, ENABLE_APE);  in tg3_init_one()
17655 		tp->aperegs = pci_ioremap_bar(pdev, BAR_2);  in tg3_init_one()
17656 		if (!tp->aperegs) {  in tg3_init_one()
17664 	tp->rx_pending = TG3_DEF_RX_RING_PENDING;  in tg3_init_one()
17665 	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;  in tg3_init_one()
17672 	err = tg3_get_invariants(tp, ent);  in tg3_init_one()
17685 	if (tg3_flag(tp, IS_5788))  in tg3_init_one()
17687 	else if (tg3_flag(tp, 40BIT_DMA_BUG)) {  in tg3_init_one()
17718 	tg3_init_bufmgr_config(tp);  in tg3_init_one()
17723 	if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {  in tg3_init_one()
17726 		if (tg3_flag(tp, 5755_PLUS))  in tg3_init_one()
17734 	if ((tg3_flag(tp, HW_TSO_1) ||  in tg3_init_one()
17735 	     tg3_flag(tp, HW_TSO_2) ||  in tg3_init_one()
17736 	     tg3_flag(tp, HW_TSO_3)) &&  in tg3_init_one()
17739 	if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {  in tg3_init_one()
17742 		if (tg3_flag(tp, HW_TSO_3) ||  in tg3_init_one()
17743 		    tg3_asic_rev(tp) == ASIC_REV_5761 ||  in tg3_init_one()
17744 		    (tg3_asic_rev(tp) == ASIC_REV_5784 &&  in tg3_init_one()
17745 		     tg3_chip_rev(tp) != CHIPREV_5784_AX) ||  in tg3_init_one()
17746 		    tg3_asic_rev(tp) == ASIC_REV_5785 ||  in tg3_init_one()
17747 		    tg3_asic_rev(tp) == ASIC_REV_57780)  in tg3_init_one()
17760 	if (tg3_asic_rev(tp) != ASIC_REV_5780 &&  in tg3_init_one()
17761 	    !tg3_flag(tp, CPMU_PRESENT))  in tg3_init_one()
17770 	dev->max_mtu = TG3_MAX_MTU(tp);  in tg3_init_one()
17772 	if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&  in tg3_init_one()
17773 	    !tg3_flag(tp, TSO_CAPABLE) &&  in tg3_init_one()
17775 		tg3_flag_set(tp, MAX_RXPEND_64);  in tg3_init_one()
17776 		tp->rx_pending = 63;  in tg3_init_one()
17779 	err = tg3_get_device_address(tp, addr);  in tg3_init_one()
17790 	for (i = 0; i < tp->irq_max; i++) {  in tg3_init_one()
17791 		struct tg3_napi *tnapi = &tp->napi[i];  in tg3_init_one()
17793 		tnapi->tp = tp;  in tg3_init_one()
17807 		if (!tg3_flag(tp, SUPPORT_MSIX))  in tg3_init_one()
17835 		tg3_full_lock(tp, 0);  in tg3_init_one()
17837 		tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_init_one()
17838 		tg3_full_unlock(tp);  in tg3_init_one()
17841 	err = tg3_test_dma(tp);  in tg3_init_one()
17847 	tg3_init_coal(tp);  in tg3_init_one()
17851 	if (tg3_asic_rev(tp) == ASIC_REV_5719 ||  in tg3_init_one()
17852 	    tg3_asic_rev(tp) == ASIC_REV_5720 ||  in tg3_init_one()
17853 	    tg3_asic_rev(tp) == ASIC_REV_5762)  in tg3_init_one()
17854 		tg3_flag_set(tp, PTP_CAPABLE);  in tg3_init_one()
17856 	tg3_timer_init(tp);  in tg3_init_one()
17858 	tg3_carrier_off(tp);  in tg3_init_one()
17866 	if (tg3_flag(tp, PTP_CAPABLE)) {  in tg3_init_one()
17867 		tg3_ptp_init(tp);  in tg3_init_one()
17868 		tp->ptp_clock = ptp_clock_register(&tp->ptp_info,  in tg3_init_one()
17869 						   &tp->pdev->dev);  in tg3_init_one()
17870 		if (IS_ERR(tp->ptp_clock))  in tg3_init_one()
17871 			tp->ptp_clock = NULL;  in tg3_init_one()
17875 		    tp->board_part_number,  in tg3_init_one()
17876 		    tg3_chip_rev_id(tp),  in tg3_init_one()
17877 		    tg3_bus_string(tp, str),  in tg3_init_one()
17880 	if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) {  in tg3_init_one()
17883 		if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)  in tg3_init_one()
17885 		else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)  in tg3_init_one()
17892 			    tg3_phy_string(tp), ethtype,  in tg3_init_one()
17893 			    (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,  in tg3_init_one()
17894 			    (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);  in tg3_init_one()
17899 		    tg3_flag(tp, USE_LINKCHG_REG) != 0,  in tg3_init_one()
17900 		    (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,  in tg3_init_one()
17901 		    tg3_flag(tp, ENABLE_ASF) != 0,  in tg3_init_one()
17902 		    tg3_flag(tp, TSO_CAPABLE) != 0);  in tg3_init_one()
17904 		    tp->dma_rwctrl,  in tg3_init_one()
17913 	if (tp->aperegs) {  in tg3_init_one()
17914 		iounmap(tp->aperegs);  in tg3_init_one()
17915 		tp->aperegs = NULL;  in tg3_init_one()
17919 	if (tp->regs) {  in tg3_init_one()
17920 		iounmap(tp->regs);  in tg3_init_one()
17921 		tp->regs = NULL;  in tg3_init_one()
17941 		struct tg3 *tp = netdev_priv(dev);  in tg3_remove_one()  local
17943 		tg3_ptp_fini(tp);  in tg3_remove_one()
17945 		release_firmware(tp->fw);  in tg3_remove_one()
17947 		tg3_reset_task_cancel(tp);  in tg3_remove_one()
17949 		if (tg3_flag(tp, USE_PHYLIB)) {  in tg3_remove_one()
17950 			tg3_phy_fini(tp);  in tg3_remove_one()
17951 			tg3_mdio_fini(tp);  in tg3_remove_one()
17955 		if (tp->aperegs) {  in tg3_remove_one()
17956 			iounmap(tp->aperegs);  in tg3_remove_one()
17957 			tp->aperegs = NULL;  in tg3_remove_one()
17959 		if (tp->regs) {  in tg3_remove_one()
17960 			iounmap(tp->regs);  in tg3_remove_one()
17961 			tp->regs = NULL;  in tg3_remove_one()
17973 	struct tg3 *tp = netdev_priv(dev);  in tg3_suspend()  local
17981 	tg3_reset_task_cancel(tp);  in tg3_suspend()
17982 	tg3_phy_stop(tp);  in tg3_suspend()
17983 	tg3_netif_stop(tp);  in tg3_suspend()
17985 	tg3_timer_stop(tp);  in tg3_suspend()
17987 	tg3_full_lock(tp, 1);  in tg3_suspend()
17988 	tg3_disable_ints(tp);  in tg3_suspend()
17989 	tg3_full_unlock(tp);  in tg3_suspend()
17993 	tg3_full_lock(tp, 0);  in tg3_suspend()
17994 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);  in tg3_suspend()
17995 	tg3_flag_clear(tp, INIT_COMPLETE);  in tg3_suspend()
17996 	tg3_full_unlock(tp);  in tg3_suspend()
17998 	err = tg3_power_down_prepare(tp);  in tg3_suspend()
18002 		tg3_full_lock(tp, 0);  in tg3_suspend()
18004 		tg3_flag_set(tp, INIT_COMPLETE);  in tg3_suspend()
18005 		err2 = tg3_restart_hw(tp, true);  in tg3_suspend()
18009 		tg3_timer_start(tp);  in tg3_suspend()
18012 		tg3_netif_start(tp);  in tg3_suspend()
18015 		tg3_full_unlock(tp);  in tg3_suspend()
18018 			tg3_phy_start(tp);  in tg3_suspend()
18029 	struct tg3 *tp = netdev_priv(dev);  in tg3_resume()  local
18039 	tg3_full_lock(tp, 0);  in tg3_resume()
18041 	tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_resume()
18043 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_resume()
18044 	err = tg3_restart_hw(tp,  in tg3_resume()
18045 			     !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));  in tg3_resume()
18049 	tg3_timer_start(tp);  in tg3_resume()
18051 	tg3_netif_start(tp);  in tg3_resume()
18054 	tg3_full_unlock(tp);  in tg3_resume()
18057 		tg3_phy_start(tp);  in tg3_resume()
18070 	struct tg3 *tp = netdev_priv(dev);  in tg3_shutdown()  local
18072 	tg3_reset_task_cancel(tp);  in tg3_shutdown()
18081 	tg3_power_down(tp);  in tg3_shutdown()
18100 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_error_detected()  local
18106 	tg3_reset_task_cancel(tp);  in tg3_io_error_detected()
18111 	if (!netdev || tp->pcierr_recovery || !netif_running(netdev))  in tg3_io_error_detected()
18116 		tp->pcierr_recovery = true;  in tg3_io_error_detected()
18118 	tg3_phy_stop(tp);  in tg3_io_error_detected()
18120 	tg3_netif_stop(tp);  in tg3_io_error_detected()
18122 	tg3_timer_stop(tp);  in tg3_io_error_detected()
18127 	tg3_full_lock(tp, 0);  in tg3_io_error_detected()
18128 	tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);  in tg3_io_error_detected()
18129 	tg3_full_unlock(tp);  in tg3_io_error_detected()
18134 			tg3_napi_enable(tp);  in tg3_io_error_detected()
18159 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_slot_reset()  local
18180 	err = tg3_power_up(tp);  in tg3_io_slot_reset()
18188 		tg3_napi_enable(tp);  in tg3_io_slot_reset()
18206 	struct tg3 *tp = netdev_priv(netdev);  in tg3_io_resume()  local
18214 	tg3_full_lock(tp, 0);  in tg3_io_resume()
18215 	tg3_ape_driver_state_change(tp, RESET_KIND_INIT);  in tg3_io_resume()
18216 	tg3_flag_set(tp, INIT_COMPLETE);  in tg3_io_resume()
18217 	err = tg3_restart_hw(tp, true);  in tg3_io_resume()
18219 		tg3_full_unlock(tp);  in tg3_io_resume()
18226 	tg3_timer_start(tp);  in tg3_io_resume()
18228 	tg3_netif_start(tp);  in tg3_io_resume()
18230 	tg3_full_unlock(tp);  in tg3_io_resume()
18232 	tg3_phy_start(tp);  in tg3_io_resume()
18235 	tp->pcierr_recovery = false;  in tg3_io_resume()