Lines Matching +full:0 +full:x1f
6 #define NA 0xCD
8 #define IDLE_CHK_E1 0x01
9 #define IDLE_CHK_E1H 0x02
10 #define IDLE_CHK_E2 0x04
11 #define IDLE_CHK_E3A0 0x08
12 #define IDLE_CHK_E3B0 0x10
118 /*line 2*/{(0x3), 1, 0x2114,
119 NA, 1, 0, pand_neq,
121 "PCIE: ucorr_err_status is not 0",
122 {NA, NA, 0x0FF010, 0, NA, NA} },
124 /*line 3*/{(0x3), 1, 0x2114,
125 NA, 1, 0, pand_neq,
128 {NA, NA, 0x100000, 0, NA, NA} },
130 /*line 4*/{(0x3), 1, 0x2120,
131 NA, 1, 0, pand_neq_x2,
133 "PCIE: corr_err_status is not 0x2000",
134 {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
136 /*line 5*/{(0x3), 1, 0x2814,
137 NA, 1, 0, pand_neq,
139 "PCIE: attentions register is not 0x40100",
140 {NA, NA, ~0x40100, 0, NA, NA} },
142 /*line 6*/{(0x2), 1, 0x281c,
143 NA, 1, 0, pand_neq,
145 "PCIE: attentions register is not 0x40040100",
146 {NA, NA, ~0x40040100, 0, NA, NA} },
148 /*line 7*/{(0x2), 1, 0x2820,
149 NA, 1, 0, pand_neq,
151 "PCIE: attentions register is not 0x40040100",
152 {NA, NA, ~0x40040100, 0, NA, NA} },
154 /*line 8*/{(0x3), 1, PXP2_REG_PGL_EXP_ROM2,
155 NA, 1, 0, pneq,
157 …g read requests. Not all completios have arrived for read requests on tags that are marked with 0",
158 {NA, NA, 0xffffffff, NA, NA, NA} },
160 /*line 9*/{(0x3), 2, 0x212c,
163 "PCIE: error packet header is not 0",
164 {NA, NA, 0, NA, NA, NA} },
166 /*line 10*/{(0x1C), 1, 0x2104,
167 NA, 1, 0, pand_neq,
169 "PCIE: ucorr_err_status is not 0",
170 {NA, NA, 0x0FD010, 0, NA, NA} },
172 /*line 11*/{(0x1C), 1, 0x2104,
173 NA, 1, 0, pand_neq,
176 {NA, NA, 0x100000, 0, NA, NA} },
178 /*line 12*/{(0x1C), 1, 0x2104,
179 NA, 1, 0, pand_neq,
182 {NA, NA, 0x2000, 0, NA, NA} },
184 /*line 13*/{(0x1C), 1, 0x2110,
185 NA, 1, 0, pand_neq_x2,
187 "PCIE: corr_err_status is not 0x2000",
188 {NA, NA, 0x31C1, 0x2000, 0x31C1, 0} },
190 /*line 14*/{(0x1C), 1, 0x2814,
191 NA, 1, 0, pand_neq,
193 "PCIE: TTX_BRIDGE_FORWARD_ERR - Received master request while BME was 0",
194 {NA, NA, 0x2000000, 0, NA, NA} },
196 /*line 15*/{(0x1C), 1, 0x2814,
197 NA, 1, 0, pand_neq,
199 "PCIE: Func 0 1: attentions register is not 0x2040902",
200 {NA, NA, ~0x2040902, 0, NA, NA} },
202 /*line 16*/{(0x1C), 1, 0x2854,
203 NA, 1, 0, pand_neq,
205 "PCIE: Func 2 3 4: attentions register is not 0x10240902",
206 {NA, NA, ~0x10240902, 0, NA, NA} },
208 /*line 17*/{(0x1C), 1, 0x285c,
209 NA, 1, 0, pand_neq,
211 "PCIE: Func 5 6 7: attentions register is not 0x10240902",
212 {NA, NA, ~0x10240902, 0, NA, NA} },
214 /*line 18*/{(0x18), 1, 0x3040,
215 NA, 1, 0, pand_neq,
218 {NA, NA, 0x2, 0, NA, NA} },
220 /*line 19*/{(0x1C), 1, PXP2_REG_PGL_EXP_ROM2,
221 NA, 1, 0, pneq,
223 …tstanding read requests for tags 0-31. Not all completios have arrived for read requests on tags t…
224 {NA, NA, 0xffffffff, NA, NA, NA} },
226 /*line 20*/{(0x1C), 2, 0x211c,
229 "PCIE: error packet header is not 0",
230 {NA, NA, 0, NA, NA, NA} },
232 /*line 21*/{(0x1C), 1, PGLUE_B_REG_INCORRECT_RCV_DETAILS,
233 NA, 1, 0, pneq,
236 {NA, NA, 0, NA, NA, NA} },
238 /*line 22*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_31_0,
239 NA, 1, 0, pneq,
241 "PGLUE_B: was_error for VFs 0-31 is not 0",
242 {NA, NA, 0, NA, NA, NA} },
244 /*line 23*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_63_32,
245 NA, 1, 0, pneq,
247 "PGLUE_B: was_error for VFs 32-63 is not 0",
248 {NA, NA, 0, NA, NA, NA} },
250 /*line 24*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_95_64,
251 NA, 1, 0, pneq,
253 "PGLUE_B: was_error for VFs 64-95 is not 0",
254 {NA, NA, 0, NA, NA, NA} },
256 /*line 25*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_VF_127_96,
257 NA, 1, 0, pneq,
259 "PGLUE_B: was_error for VFs 96-127 is not 0",
260 {NA, NA, 0, NA, NA, NA} },
262 /*line 26*/{(0x1C), 1, PGLUE_B_REG_WAS_ERROR_PF_7_0,
263 NA, 1, 0, pneq,
265 "PGLUE_B: was_error for PFs 0-7 is not 0",
266 {NA, NA, 0, NA, NA, NA} },
268 /*line 27*/{(0x1C), 1, PGLUE_B_REG_RX_ERR_DETAILS,
269 NA, 1, 0, pneq,
271 …PGLUE_B: Completion received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Err…
272 {NA, NA, 0, NA, NA, NA} },
274 /*line 28*/{(0x1C), 1, PGLUE_B_REG_RX_TCPL_ERR_DETAILS,
275 NA, 1, 0, pneq,
277 …"PGLUE_B: ATS TCPL received with error. (2:0) - PFID. (3) - VF_VALID. (9:4) - VFID. (11:10) - Erro…
278 {NA, NA, 0, NA, NA, NA} },
280 /*line 29*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_31_0,
281 NA, 1, 0, pneq,
283 "PGLUE_B: Error in master write. Address(31:0) is not 0",
284 {NA, NA, 0, NA, NA, NA} },
286 /*line 30*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_ADD_63_32,
287 NA, 1, 0, pneq,
289 "PGLUE_B: Error in master write. Address(63:32) is not 0",
290 {NA, NA, 0, NA, NA, NA} },
292 /*line 31*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS,
293 NA, 1, 0, pneq,
295 …"PGLUE_B: Error in master write. Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24)…
296 {NA, NA, 0, NA, NA, NA} },
298 /*line 32*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_WR_DETAILS2,
299 NA, 1, 0, pneq,
301 …"PGLUE_B: Error in master write. Error details 2nd register is not 0. (21) - was_error set; (22) -…
302 {NA, NA, 0, NA, NA, NA} },
304 /*line 33*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_31_0,
305 NA, 1, 0, pneq,
307 "PGLUE: Error in master read address(31:0) is not 0",
308 {NA, NA, 0, NA, NA, NA} },
310 /*line 34*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_ADD_63_32,
311 NA, 1, 0, pneq,
313 "PGLUE_B: Error in master read address(63:32) is not 0",
314 {NA, NA, 0, NA, NA, NA} },
316 /*line 35*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS,
317 NA, 1, 0, pneq,
319 …"PGLUE_B: Error in master read Error details register is not 0. (4:0) VQID. (23:21) - PFID. (24) -…
320 {NA, NA, 0, NA, NA, NA} },
322 /*line 36*/{(0x1C), 1, PGLUE_B_REG_TX_ERR_RD_DETAILS2,
323 NA, 1, 0, pneq,
325 …"PGLUE_B: Error in master read Error details 2nd register is not 0. (21) - was_error set; (22) - B…
326 {NA, NA, 0, NA, NA, NA} },
328 /*line 37*/{(0x1C), 1, PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS,
329 NA, 1, 0, pneq,
332 {NA, NA, 0, NA, NA, NA} },
334 /*line 38*/{(0x1C), 1, PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS,
335 NA, 1, 0, pneq,
338 {NA, NA, 0, NA, NA, NA} },
340 /*line 39*/{(0x1C), 1, PGLUE_B_REG_TAGS_63_32,
341 NA, 1, 0, pneq,
343 … for tags 32-63. Not all completios have arrived for read requests on tags that are marked with 0",
344 {NA, NA, 0xffffffff, NA, NA, NA} },
346 /*line 40*/{(0x1C), 3, PXP_REG_HST_VF_DISABLED_ERROR_VALID,
347 PXP_REG_HST_VF_DISABLED_ERROR_DATA, 1, 0, pneq,
350 {NA, NA, 0, NA, NA, NA} },
352 /*line 41*/{(0x1C), 1, PXP_REG_HST_PER_VIOLATION_VALID,
353 NA, 1, 0, pneq,
356 {NA, NA, 0, NA, NA, NA} },
358 /*line 42*/{(0x1C), 1, PXP_REG_HST_INCORRECT_ACCESS_VALID,
359 NA, 1, 0, pneq,
362 {NA, NA, 0, NA, NA, NA} },
364 /*line 43*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS,
365 NA, 1, 0, pneq,
367 …"PXP2: Completion received with error. Error details register is not 0. (15:0) - ECHO. (28:16) - S…
368 {NA, NA, 0, NA, NA, NA} },
370 /*line 44*/{(0x1C), 1, PXP2_REG_RD_CPL_ERR_DETAILS2,
371 NA, 1, 0, pneq,
373 …"PXP2: Completion received with error. Error details 2nd register is not 0. (4:0) - VQ ID. (8:5) -…
374 {NA, NA, 0, NA, NA, NA} },
376 /*line 45*/{(0x1F), 1, PXP2_REG_RQ_VQ0_ENTRY_CNT,
377 NA, 1, 0, pneq,
380 {NA, NA, 0, NA, NA, NA} },
382 /*line 46*/{(0x1F), 1, PXP2_REG_RQ_VQ1_ENTRY_CNT,
383 NA, 1, 0, pneq,
386 {NA, NA, 0, NA, NA, NA} },
388 /*line 47*/{(0x1F), 1, PXP2_REG_RQ_VQ2_ENTRY_CNT,
389 NA, 1, 0, pneq,
392 {NA, NA, 0, NA, NA, NA} },
394 /*line 48*/{(0x1F), 1, PXP2_REG_RQ_VQ3_ENTRY_CNT,
395 NA, 1, 0, pgt,
400 /*line 49*/{(0x1F), 1, PXP2_REG_RQ_VQ4_ENTRY_CNT,
401 NA, 1, 0, pneq,
404 {NA, NA, 0, NA, NA, NA} },
406 /*line 50*/{(0x1F), 1, PXP2_REG_RQ_VQ5_ENTRY_CNT,
407 NA, 1, 0, pneq,
410 {NA, NA, 0, NA, NA, NA} },
412 /*line 51*/{(0x1F), 1, PXP2_REG_RQ_VQ6_ENTRY_CNT,
413 NA, 1, 0, pneq,
416 {NA, NA, 0, NA, NA, NA} },
418 /*line 52*/{(0x1F), 1, PXP2_REG_RQ_VQ7_ENTRY_CNT,
419 NA, 1, 0, pneq,
422 {NA, NA, 0, NA, NA, NA} },
424 /*line 53*/{(0x1F), 1, PXP2_REG_RQ_VQ8_ENTRY_CNT,
425 NA, 1, 0, pneq,
428 {NA, NA, 0, NA, NA, NA} },
430 /*line 54*/{(0x1F), 1, PXP2_REG_RQ_VQ9_ENTRY_CNT,
431 NA, 1, 0, pneq,
434 {NA, NA, 0, NA, NA, NA} },
436 /*line 55*/{(0x1F), 1, PXP2_REG_RQ_VQ10_ENTRY_CNT,
437 NA, 1, 0, pneq,
440 {NA, NA, 0, NA, NA, NA} },
442 /*line 56*/{(0x1F), 1, PXP2_REG_RQ_VQ11_ENTRY_CNT,
443 NA, 1, 0, pneq,
446 {NA, NA, 0, NA, NA, NA} },
448 /*line 57*/{(0x1F), 1, PXP2_REG_RQ_VQ12_ENTRY_CNT,
449 NA, 1, 0, pneq,
452 {NA, NA, 0, NA, NA, NA} },
454 /*line 58*/{(0x1F), 1, PXP2_REG_RQ_VQ13_ENTRY_CNT,
455 NA, 1, 0, pneq,
458 {NA, NA, 0, NA, NA, NA} },
460 /*line 59*/{(0x1F), 1, PXP2_REG_RQ_VQ14_ENTRY_CNT,
461 NA, 1, 0, pneq,
464 {NA, NA, 0, NA, NA, NA} },
466 /*line 60*/{(0x1F), 1, PXP2_REG_RQ_VQ15_ENTRY_CNT,
467 NA, 1, 0, pneq,
470 {NA, NA, 0, NA, NA, NA} },
472 /*line 61*/{(0x1F), 1, PXP2_REG_RQ_VQ16_ENTRY_CNT,
473 NA, 1, 0, pneq,
476 {NA, NA, 0, NA, NA, NA} },
478 /*line 62*/{(0x1F), 1, PXP2_REG_RQ_VQ17_ENTRY_CNT,
479 NA, 1, 0, pneq,
482 {NA, NA, 0, NA, NA, NA} },
484 /*line 63*/{(0x1F), 1, PXP2_REG_RQ_VQ18_ENTRY_CNT,
485 NA, 1, 0, pneq,
488 {NA, NA, 0, NA, NA, NA} },
490 /*line 64*/{(0x1F), 1, PXP2_REG_RQ_VQ19_ENTRY_CNT,
491 NA, 1, 0, pneq,
494 {NA, NA, 0, NA, NA, NA} },
496 /*line 65*/{(0x1F), 1, PXP2_REG_RQ_VQ20_ENTRY_CNT,
497 NA, 1, 0, pneq,
500 {NA, NA, 0, NA, NA, NA} },
502 /*line 66*/{(0x1F), 1, PXP2_REG_RQ_VQ21_ENTRY_CNT,
503 NA, 1, 0, pneq,
506 {NA, NA, 0, NA, NA, NA} },
508 /*line 67*/{(0x1F), 1, PXP2_REG_RQ_VQ22_ENTRY_CNT,
509 NA, 1, 0, pneq,
512 {NA, NA, 0, NA, NA, NA} },
514 /*line 68*/{(0x1F), 1, PXP2_REG_RQ_VQ23_ENTRY_CNT,
515 NA, 1, 0, pneq,
518 {NA, NA, 0, NA, NA, NA} },
520 /*line 69*/{(0x1F), 1, PXP2_REG_RQ_VQ24_ENTRY_CNT,
521 NA, 1, 0, pneq,
524 {NA, NA, 0, NA, NA, NA} },
526 /*line 70*/{(0x1F), 1, PXP2_REG_RQ_VQ25_ENTRY_CNT,
527 NA, 1, 0, pneq,
530 {NA, NA, 0, NA, NA, NA} },
532 /*line 71*/{(0x1F), 1, PXP2_REG_RQ_VQ26_ENTRY_CNT,
533 NA, 1, 0, pneq,
536 {NA, NA, 0, NA, NA, NA} },
538 /*line 72*/{(0x1F), 1, PXP2_REG_RQ_VQ27_ENTRY_CNT,
539 NA, 1, 0, pneq,
542 {NA, NA, 0, NA, NA, NA} },
544 /*line 73*/{(0x1F), 1, PXP2_REG_RQ_VQ28_ENTRY_CNT,
545 NA, 1, 0, pneq,
548 {NA, NA, 0, NA, NA, NA} },
550 /*line 74*/{(0x1F), 1, PXP2_REG_RQ_VQ29_ENTRY_CNT,
551 NA, 1, 0, pneq,
554 {NA, NA, 0, NA, NA, NA} },
556 /*line 75*/{(0x1F), 1, PXP2_REG_RQ_VQ30_ENTRY_CNT,
557 NA, 1, 0, pneq,
560 {NA, NA, 0, NA, NA, NA} },
562 /*line 76*/{(0x1F), 1, PXP2_REG_RQ_VQ31_ENTRY_CNT,
563 NA, 1, 0, pneq,
566 {NA, NA, 0, NA, NA, NA} },
568 /*line 77*/{(0x1F), 1, PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY,
569 NA, 1, 0, pneq,
571 "PXP2: rq_ufifo_num_of_entry is not 0",
572 {NA, NA, 0, NA, NA, NA} },
574 /*line 78*/{(0x1F), 1, PXP2_REG_RQ_RBC_DONE,
575 NA, 1, 0, pneq,
580 /*line 79*/{(0x1F), 1, PXP2_REG_RQ_CFG_DONE,
581 NA, 1, 0, pneq,
586 /*line 80*/{(0x3), 1, PXP2_REG_PSWRQ_BW_CREDIT,
587 NA, 1, 0, pneq,
590 {NA, NA, 0x1B, NA, NA, NA} },
592 /*line 81*/{(0x1F), 1, PXP2_REG_RD_START_INIT,
593 NA, 1, 0, pneq,
598 /*line 82*/{(0x1F), 1, PXP2_REG_RD_INIT_DONE,
599 NA, 1, 0, pneq,
604 /*line 83*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
605 PXP2_REG_RD_SR_NUM_CFG, 1, 0, pne_sub_r2,
610 /*line 84*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
611 PXP2_REG_RD_BLK_NUM_CFG, 1, 0, pneq_r2,
616 /*line 85*/{(0x1F), 3, PXP2_REG_RD_SR_CNT,
617 PXP2_REG_RD_SR_NUM_CFG, 1, 0, plt_sub_r2,
622 /*line 86*/{(0x1F), 3, PXP2_REG_RD_BLK_CNT,
623 PXP2_REG_RD_BLK_NUM_CFG, 1, 0, plt_sub_r2,
628 /*line 87*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_0,
629 NA, 1, 0, pneq,
634 /*line 88*/{(0x1F), 1, PXP2_REG_RD_PORT_IS_IDLE_1,
635 NA, 1, 0, pneq,
640 /*line 89*/{(0x1F), 2, PXP2_REG_RD_ALMOST_FULL_0,
643 "PXP2: rd_almost_full is not 0",
644 {NA, NA, 0, NA, NA, NA} },
646 /*line 90*/{(0x1F), 1, PXP2_REG_RD_DISABLE_INPUTS,
647 NA, 1, 0, pneq,
650 {NA, NA, 0, NA, NA, NA} },
652 /*line 91*/{(0x1F), 1, PXP2_REG_HST_HEADER_FIFO_STATUS,
653 NA, 1, 0, pneq,
655 "PXP2: HST header FIFO status is not 0",
656 {NA, NA, 0, NA, NA, NA} },
658 /*line 92*/{(0x1F), 1, PXP2_REG_HST_DATA_FIFO_STATUS,
659 NA, 1, 0, pneq,
661 "PXP2: HST data FIFO status is not 0",
662 {NA, NA, 0, NA, NA, NA} },
664 /*line 93*/{(0x3), 1, PXP2_REG_PGL_WRITE_BLOCKED,
665 NA, 1, 0, pneq,
667 "PXP2: pgl_write_blocked is not 0",
668 {NA, NA, 0, NA, NA, NA} },
670 /*line 94*/{(0x3), 1, PXP2_REG_PGL_READ_BLOCKED,
671 NA, 1, 0, pneq,
673 "PXP2: pgl_read_blocked is not 0",
674 {NA, NA, 0, NA, NA, NA} },
676 /*line 95*/{(0x1C), 1, PXP2_REG_PGL_WRITE_BLOCKED,
677 NA, 1, 0, pneq,
679 "PXP2: pgl_write_blocked is not 0",
680 {NA, NA, 0, NA, NA, NA} },
682 /*line 96*/{(0x1C), 1, PXP2_REG_PGL_READ_BLOCKED,
683 NA, 1, 0, pneq,
685 "PXP2: pgl_read_blocked is not 0",
686 {NA, NA, 0, NA, NA, NA} },
688 /*line 97*/{(0x1F), 1, PXP2_REG_PGL_TXW_CDTS,
689 NA, 1, 0, prsh_and_neq,
692 {NA, NA, 17, 1, 0, NA} },
694 /*line 98*/{(0x1F), 1, PXP_REG_HST_ARB_IS_IDLE,
695 NA, 1, 0, pneq,
700 /*line 99*/{(0x1F), 1, PXP_REG_HST_CLIENTS_WAITING_TO_ARB,
701 NA, 1, 0, pneq,
704 {NA, NA, 0, NA, NA, NA} },
706 /*line 100*/{(0x1E), 1, PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS,
707 NA, 1, 0, pneq,
710 {NA, NA, 0, NA, NA, NA} },
712 /*line 101*/{(0x1E), 1, PXP_REG_HST_DISCARD_DOORBELLS_STATUS,
713 NA, 1, 0, pneq,
716 {NA, NA, 0, NA, NA, NA} },
718 /*line 102*/{(0x1C), 1, PXP2_REG_RQ_GARB,
719 NA, 1, 0, pand_neq,
722 {NA, NA, 0x1000, 0, NA, NA} },
724 /*line 103*/{(0x1F), 1, DMAE_REG_GO_C0,
725 NA, 1, 0, pneq,
727 "DMAE: command 0 go is not 0",
728 {NA, NA, 0, NA, NA, NA} },
730 /*line 104*/{(0x1F), 1, DMAE_REG_GO_C1,
731 NA, 1, 0, pneq,
733 "DMAE: command 1 go is not 0",
734 {NA, NA, 0, NA, NA, NA} },
736 /*line 105*/{(0x1F), 1, DMAE_REG_GO_C2,
737 NA, 1, 0, pneq,
739 "DMAE: command 2 go is not 0",
740 {NA, NA, 0, NA, NA, NA} },
742 /*line 106*/{(0x1F), 1, DMAE_REG_GO_C3,
743 NA, 1, 0, pneq,
745 "DMAE: command 3 go is not 0",
746 {NA, NA, 0, NA, NA, NA} },
748 /*line 107*/{(0x1F), 1, DMAE_REG_GO_C4,
749 NA, 1, 0, pneq,
751 "DMAE: command 4 go is not 0",
752 {NA, NA, 0, NA, NA, NA} },
754 /*line 108*/{(0x1F), 1, DMAE_REG_GO_C5,
755 NA, 1, 0, pneq,
757 "DMAE: command 5 go is not 0",
758 {NA, NA, 0, NA, NA, NA} },
760 /*line 109*/{(0x1F), 1, DMAE_REG_GO_C6,
761 NA, 1, 0, pneq,
763 "DMAE: command 6 go is not 0",
764 {NA, NA, 0, NA, NA, NA} },
766 /*line 110*/{(0x1F), 1, DMAE_REG_GO_C7,
767 NA, 1, 0, pneq,
769 "DMAE: command 7 go is not 0",
770 {NA, NA, 0, NA, NA, NA} },
772 /*line 111*/{(0x1F), 1, DMAE_REG_GO_C8,
773 NA, 1, 0, pneq,
775 "DMAE: command 8 go is not 0",
776 {NA, NA, 0, NA, NA, NA} },
778 /*line 112*/{(0x1F), 1, DMAE_REG_GO_C9,
779 NA, 1, 0, pneq,
781 "DMAE: command 9 go is not 0",
782 {NA, NA, 0, NA, NA, NA} },
784 /*line 113*/{(0x1F), 1, DMAE_REG_GO_C10,
785 NA, 1, 0, pneq,
787 "DMAE: command 10 go is not 0",
788 {NA, NA, 0, NA, NA, NA} },
790 /*line 114*/{(0x1F), 1, DMAE_REG_GO_C11,
791 NA, 1, 0, pneq,
793 "DMAE: command 11 go is not 0",
794 {NA, NA, 0, NA, NA, NA} },
796 /*line 115*/{(0x1F), 1, DMAE_REG_GO_C12,
797 NA, 1, 0, pneq,
799 "DMAE: command 12 go is not 0",
800 {NA, NA, 0, NA, NA, NA} },
802 /*line 116*/{(0x1F), 1, DMAE_REG_GO_C13,
803 NA, 1, 0, pneq,
805 "DMAE: command 13 go is not 0",
806 {NA, NA, 0, NA, NA, NA} },
808 /*line 117*/{(0x1F), 1, DMAE_REG_GO_C14,
809 NA, 1, 0, pneq,
811 "DMAE: command 14 go is not 0",
812 {NA, NA, 0, NA, NA, NA} },
814 /*line 118*/{(0x1F), 1, DMAE_REG_GO_C15,
815 NA, 1, 0, pneq,
817 "DMAE: command 15 go is not 0",
818 {NA, NA, 0, NA, NA, NA} },
820 /*line 119*/{(0x1F), 1, CFC_REG_ERROR_VECTOR,
821 NA, 1, 0, pneq,
823 "CFC: error vector is not 0",
824 {NA, NA, 0, NA, NA, NA} },
826 /*line 120*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ARRIVING,
827 NA, 1, 0, pneq,
829 "CFC: number of arriving LCIDs is not 0",
830 {NA, NA, 0, NA, NA, NA} },
832 /*line 121*/{(0x1F), 1, CFC_REG_NUM_LCIDS_ALLOC,
833 NA, 1, 0, pneq,
835 "CFC: number of alloc LCIDs is not 0",
836 {NA, NA, 0, NA, NA, NA} },
838 /*line 122*/{(0x1F), 1, CFC_REG_NUM_LCIDS_LEAVING,
839 NA, 1, 0, pneq,
841 "CFC: number of leaving LCIDs is not 0",
842 {NA, NA, 0, NA, NA, NA} },
844 /*line 123*/{(0x1F), 7, CFC_REG_INFO_RAM,
847 "CFC: AC is neither 0 nor 2 on connType 0 (ETH)",
848 {NA, NA, 0, 0, 2, NA} },
850 /*line 124*/{(0x1F), 7, CFC_REG_INFO_RAM,
853 "CFC: AC is not 0 on connType 1 (TOE)",
854 {NA, NA, 1, 0, NA, NA} },
856 /*line 125*/{(0x1F), 7, CFC_REG_INFO_RAM,
859 "CFC: AC is not 0 on connType 3 (iSCSI)",
860 {NA, NA, 3, 0, NA, NA} },
862 /*line 126*/{(0x1F), 7, CFC_REG_INFO_RAM,
865 "CFC: AC is not 0 on connType 4 (FCoE)",
866 {NA, NA, 4, 0, NA, NA} },
868 /*line 127*/{(0x1F), 2, QM_REG_QTASKCTR_0,
872 {NA, NA, 0, NA, NA, NA} },
874 /*line 128*/{(0xF), 3, QM_REG_VOQCREDIT_0,
875 QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
880 /*line 129*/{(0xF), 3, QM_REG_VOQCREDIT_1,
881 QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
886 /*line 130*/{(0xF), 3, QM_REG_VOQCREDIT_4,
887 QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
892 /*line 131*/{(0x3), 3, QM_REG_PORT0BYTECRD,
893 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
898 /*line 132*/{(0x3), 3, QM_REG_PORT1BYTECRD,
899 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
904 /*line 133*/{(0x1F), 1, CCM_REG_CAM_OCCUP,
905 NA, 1, 0, pneq,
908 {NA, NA, 0, NA, NA, NA} },
910 /*line 134*/{(0x1F), 1, TCM_REG_CAM_OCCUP,
911 NA, 1, 0, pneq,
914 {NA, NA, 0, NA, NA, NA} },
916 /*line 135*/{(0x1F), 1, UCM_REG_CAM_OCCUP,
917 NA, 1, 0, pneq,
920 {NA, NA, 0, NA, NA, NA} },
922 /*line 136*/{(0x1F), 1, XCM_REG_CAM_OCCUP,
923 NA, 1, 0, pneq,
926 {NA, NA, 0, NA, NA, NA} },
928 /*line 137*/{(0x1F), 1, BRB1_REG_NUM_OF_FULL_BLOCKS,
929 NA, 1, 0, pneq,
932 {NA, NA, 0, NA, NA, NA} },
934 /*line 138*/{(0x1F), 1, CSEM_REG_SLEEP_THREADS_VALID,
935 NA, 1, 0, pneq,
938 {NA, NA, 0, NA, NA, NA} },
940 /*line 139*/{(0x1F), 1, TSEM_REG_SLEEP_THREADS_VALID,
941 NA, 1, 0, pneq,
944 {NA, NA, 0, NA, NA, NA} },
946 /*line 140*/{(0x1F), 1, USEM_REG_SLEEP_THREADS_VALID,
947 NA, 1, 0, pneq,
950 {NA, NA, 0, NA, NA, NA} },
952 /*line 141*/{(0x1F), 1, XSEM_REG_SLEEP_THREADS_VALID,
953 NA, 1, 0, pneq,
956 {NA, NA, 0, NA, NA, NA} },
958 /*line 142*/{(0x1F), 1, CSEM_REG_SLOW_EXT_STORE_EMPTY,
959 NA, 1, 0, pneq,
964 /*line 143*/{(0x1F), 1, TSEM_REG_SLOW_EXT_STORE_EMPTY,
965 NA, 1, 0, pneq,
970 /*line 144*/{(0x1F), 1, USEM_REG_SLOW_EXT_STORE_EMPTY,
971 NA, 1, 0, pneq,
976 /*line 145*/{(0x1F), 1, XSEM_REG_SLOW_EXT_STORE_EMPTY,
977 NA, 1, 0, pneq,
982 /*line 146*/{(0x1F), 1, CSDM_REG_SYNC_PARSER_EMPTY,
983 NA, 1, 0, pneq,
988 /*line 147*/{(0x1F), 1, TSDM_REG_SYNC_PARSER_EMPTY,
989 NA, 1, 0, pneq,
994 /*line 148*/{(0x1F), 1, USDM_REG_SYNC_PARSER_EMPTY,
995 NA, 1, 0, pneq,
1000 /*line 149*/{(0x1F), 1, XSDM_REG_SYNC_PARSER_EMPTY,
1001 NA, 1, 0, pneq,
1006 /*line 150*/{(0x1F), 1, CSDM_REG_SYNC_SYNC_EMPTY,
1007 NA, 1, 0, pneq,
1012 /*line 151*/{(0x1F), 1, TSDM_REG_SYNC_SYNC_EMPTY,
1013 NA, 1, 0, pneq,
1018 /*line 152*/{(0x1F), 1, USDM_REG_SYNC_SYNC_EMPTY,
1019 NA, 1, 0, pneq,
1024 /*line 153*/{(0x1F), 1, XSDM_REG_SYNC_SYNC_EMPTY,
1025 NA, 1, 0, pneq,
1030 /*line 154*/{(0x1F), 1, CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1031 NA, 1, 0, pneq,
1036 /*line 155*/{(0x1F), 1, TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1037 NA, 1, 0, pneq,
1042 /*line 156*/{(0x1F), 1, USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1043 NA, 1, 0, pneq,
1048 /*line 157*/{(0x1F), 1, XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY,
1049 NA, 1, 0, pneq,
1054 /*line 158*/{(0x1F), 1, DORQ_REG_DQ_FILL_LVLF,
1055 NA, 1, 0, pneq,
1058 {NA, NA, 0, NA, NA, NA} },
1060 /*line 159*/{(0x1F), 1, CFC_REG_CFC_INT_STS,
1061 NA, 1, 0, pneq,
1063 "CFC: Interrupt status is not 0",
1064 {NA, NA, 0, NA, NA, NA} },
1066 /*line 160*/{(0x1F), 1, CDU_REG_CDU_INT_STS,
1067 NA, 1, 0, pneq,
1069 "CDU: Interrupt status is not 0",
1070 {NA, NA, 0, NA, NA, NA} },
1072 /*line 161*/{(0x1F), 1, CCM_REG_CCM_INT_STS,
1073 NA, 1, 0, pneq,
1075 "CCM: Interrupt status is not 0",
1076 {NA, NA, 0, NA, NA, NA} },
1078 /*line 162*/{(0x1F), 1, TCM_REG_TCM_INT_STS,
1079 NA, 1, 0, pneq,
1081 "TCM: Interrupt status is not 0",
1082 {NA, NA, 0, NA, NA, NA} },
1084 /*line 163*/{(0x1F), 1, UCM_REG_UCM_INT_STS,
1085 NA, 1, 0, pneq,
1087 "UCM: Interrupt status is not 0",
1088 {NA, NA, 0, NA, NA, NA} },
1090 /*line 164*/{(0x1F), 1, XCM_REG_XCM_INT_STS,
1091 NA, 1, 0, pneq,
1093 "XCM: Interrupt status is not 0",
1094 {NA, NA, 0, NA, NA, NA} },
1096 /*line 165*/{(0xF), 1, PBF_REG_PBF_INT_STS,
1097 NA, 1, 0, pneq,
1099 "PBF: Interrupt status is not 0",
1100 {NA, NA, 0, NA, NA, NA} },
1102 /*line 166*/{(0x1F), 1, TM_REG_TM_INT_STS,
1103 NA, 1, 0, pneq,
1105 "TIMERS: Interrupt status is not 0",
1106 {NA, NA, 0, NA, NA, NA} },
1108 /*line 167*/{(0x1F), 1, DORQ_REG_DORQ_INT_STS,
1109 NA, 1, 0, pneq,
1111 "DORQ: Interrupt status is not 0",
1112 {NA, NA, 0, NA, NA, NA} },
1114 /*line 168*/{(0x1F), 1, SRC_REG_SRC_INT_STS,
1115 NA, 1, 0, pneq,
1117 "SRCH: Interrupt status is not 0",
1118 {NA, NA, 0, NA, NA, NA} },
1120 /*line 169*/{(0x1F), 1, PRS_REG_PRS_INT_STS,
1121 NA, 1, 0, pneq,
1123 "PRS: Interrupt status is not 0",
1124 {NA, NA, 0, NA, NA, NA} },
1126 /*line 170*/{(0x1F), 1, BRB1_REG_BRB1_INT_STS,
1127 NA, 1, 0, pand_neq,
1129 "BRB1: Interrupt status is not 0",
1130 {NA, NA, ~0xFC00, 0, NA, NA} },
1132 /*line 171*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_INT_STS,
1133 NA, 1, 0, pneq,
1135 "XPB: Interrupt status is not 0",
1136 {NA, NA, 0, NA, NA, NA} },
1138 /*line 172*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_INT_STS,
1139 NA, 1, 0, pneq,
1141 "UPB: Interrupt status is not 0",
1142 {NA, NA, 0, NA, NA, NA} },
1144 /*line 173*/{(0x1), 1, PXP2_REG_PXP2_INT_STS,
1145 NA, 1, 0, pneq,
1147 "PXP2: Interrupt status 0 is not 0",
1148 {NA, NA, 0, NA, NA, NA} },
1150 /*line 174*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_0,
1151 NA, 1, 0, pneq,
1153 "PXP2: Interrupt status 0 is not 0",
1154 {NA, NA, 0, NA, NA, NA} },
1156 /*line 175*/{(0x1E), 1, PXP2_REG_PXP2_INT_STS_1,
1157 NA, 1, 0, pneq,
1159 "PXP2: Interrupt status 1 is not 0",
1160 {NA, NA, 0, NA, NA, NA} },
1162 /*line 176*/{(0x1F), 1, QM_REG_QM_INT_STS,
1163 NA, 1, 0, pneq,
1165 "QM: Interrupt status is not 0",
1166 {NA, NA, 0, NA, NA, NA} },
1168 /*line 177*/{(0x1F), 1, PXP_REG_PXP_INT_STS_0,
1169 NA, 1, 0, pneq,
1171 "PXP: P0 Interrupt status is not 0",
1172 {NA, NA, 0, NA, NA, NA} },
1174 /*line 178*/{(0x1F), 1, PXP_REG_PXP_INT_STS_1,
1175 NA, 1, 0, pneq,
1177 "PXP: P1 Interrupt status is not 0",
1178 {NA, NA, 0, NA, NA, NA} },
1180 /*line 179*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_INT_STS,
1181 NA, 1, 0, pneq,
1183 "PGLUE_B: Interrupt status is not 0",
1184 {NA, NA, 0, NA, NA, NA} },
1186 /*line 180*/{(0x1F), 1, DORQ_REG_RSPA_CRD_CNT,
1187 NA, 1, 0, pneq,
1192 /*line 181*/{(0x1F), 1, DORQ_REG_RSPB_CRD_CNT,
1193 NA, 1, 0, pneq,
1198 /*line 182*/{(0x3), 1, QM_REG_VOQCRDERRREG,
1199 NA, 1, 0, pneq,
1201 "QM: Credit error register is not 0 (byte or credit overflow/underflow)",
1202 {NA, NA, 0, NA, NA, NA} },
1204 /*line 183*/{(0x1F), 1, DORQ_REG_DQ_FULL_ST,
1205 NA, 1, 0, pneq,
1208 {NA, NA, 0, NA, NA, NA} },
1210 /*line 184*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0,
1211 NA, 1, 0, pand_neq,
1213 "AEU: P0 AFTER_INVERT_1 is not 0",
1214 {NA, NA, ~0xCFFC, 0, NA, NA} },
1216 /*line 185*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0,
1217 NA, 1, 0, pneq,
1219 "AEU: P0 AFTER_INVERT_2 is not 0",
1220 {NA, NA, 0, NA, NA, NA} },
1222 /*line 186*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0,
1223 NA, 1, 0, pand_neq,
1225 "AEU: P0 AFTER_INVERT_3 is not 0",
1226 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1228 /*line 187*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0,
1229 NA, 1, 0, pand_neq,
1231 "AEU: P0 AFTER_INVERT_4 is not 0",
1232 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1234 /*line 188*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_1_FUNC_1,
1235 NA, 1, 0, pand_neq,
1237 "AEU: P1 AFTER_INVERT_1 is not 0",
1238 {NA, NA, ~0xCFFC, 0, NA, NA} },
1240 /*line 189*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_2_FUNC_1,
1241 NA, 1, 0, pneq,
1243 "AEU: P1 AFTER_INVERT_2 is not 0",
1244 {NA, NA, 0, NA, NA, NA} },
1246 /*line 190*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_3_FUNC_1,
1247 NA, 1, 0, pand_neq,
1249 "AEU: P1 AFTER_INVERT_3 is not 0",
1250 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1252 /*line 191*/{(0x3), 1, MISC_REG_AEU_AFTER_INVERT_4_FUNC_1,
1253 NA, 1, 0, pand_neq,
1255 "AEU: P1 AFTER_INVERT_4 is not 0",
1256 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1258 /*line 192*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_1_MCP,
1259 NA, 1, 0, pand_neq,
1261 "AEU: MCP AFTER_INVERT_1 is not 0",
1262 {NA, NA, ~0xCFFC, 0, NA, NA} },
1264 /*line 193*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_2_MCP,
1265 NA, 1, 0, pneq,
1267 "AEU: MCP AFTER_INVERT_2 is not 0",
1268 {NA, NA, 0, NA, NA, NA} },
1270 /*line 194*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_3_MCP,
1271 NA, 1, 0, pand_neq,
1273 "AEU: MCP AFTER_INVERT_3 is not 0",
1274 {NA, NA, ~0xFFFF0000, 0, NA, NA} },
1276 /*line 195*/{(0x1F), 1, MISC_REG_AEU_AFTER_INVERT_4_MCP,
1277 NA, 1, 0, pand_neq,
1279 "AEU: MCP AFTER_INVERT_4 is not 0",
1280 {NA, NA, ~0x801FFFFF, 0, NA, NA} },
1282 /*line 196*/{(0xF), 5, PBF_REG_P0_CREDIT,
1283 PBF_REG_P0_INIT_CRD, 1, 0, pneq_r2,
1288 /*line 197*/{(0xF), 5, PBF_REG_P1_CREDIT,
1289 PBF_REG_P1_INIT_CRD, 1, 0, pneq_r2,
1294 /*line 198*/{(0xF), 3, PBF_REG_P4_CREDIT,
1295 PBF_REG_P4_INIT_CRD, 1, 0, pneq_r2,
1300 /*line 199*/{(0x10), 5, PBF_REG_CREDIT_Q0,
1301 PBF_REG_INIT_CRD_Q0, 1, 0, pneq_r2,
1306 /*line 200*/{(0x10), 5, PBF_REG_CREDIT_Q1,
1307 PBF_REG_INIT_CRD_Q1, 1, 0, pneq_r2,
1312 /*line 201*/{(0x10), 5, PBF_REG_CREDIT_Q2,
1313 PBF_REG_INIT_CRD_Q2, 1, 0, pneq_r2,
1318 /*line 202*/{(0x10), 5, PBF_REG_CREDIT_Q3,
1319 PBF_REG_INIT_CRD_Q3, 1, 0, pneq_r2,
1324 /*line 203*/{(0x10), 5, PBF_REG_CREDIT_Q4,
1325 PBF_REG_INIT_CRD_Q4, 1, 0, pneq_r2,
1330 /*line 204*/{(0x10), 5, PBF_REG_CREDIT_Q5,
1331 PBF_REG_INIT_CRD_Q5, 1, 0, pneq_r2,
1336 /*line 205*/{(0x10), 3, PBF_REG_CREDIT_LB_Q,
1337 PBF_REG_INIT_CRD_LB_Q, 1, 0, pneq_r2,
1342 /*line 206*/{(0xF), 1, PBF_REG_P0_TASK_CNT,
1343 NA, 1, 0, pneq,
1345 "PBF: P0 task_cnt is not 0",
1346 {NA, NA, 0, NA, NA, NA} },
1348 /*line 207*/{(0xF), 1, PBF_REG_P1_TASK_CNT,
1349 NA, 1, 0, pneq,
1351 "PBF: P1 task_cnt is not 0",
1352 {NA, NA, 0, NA, NA, NA} },
1354 /*line 208*/{(0xF), 1, PBF_REG_P4_TASK_CNT,
1355 NA, 1, 0, pneq,
1357 "PBF: P4 task_cnt is not 0",
1358 {NA, NA, 0, NA, NA, NA} },
1360 /*line 209*/{(0x10), 1, PBF_REG_TASK_CNT_Q0,
1361 NA, 1, 0, pneq,
1363 "PBF: Q0 task_cnt is not 0",
1364 {NA, NA, 0, NA, NA, NA} },
1366 /*line 210*/{(0x10), 1, PBF_REG_TASK_CNT_Q1,
1367 NA, 1, 0, pneq,
1369 "PBF: Q1 task_cnt is not 0",
1370 {NA, NA, 0, NA, NA, NA} },
1372 /*line 211*/{(0x10), 1, PBF_REG_TASK_CNT_Q2,
1373 NA, 1, 0, pneq,
1375 "PBF: Q2 task_cnt is not 0",
1376 {NA, NA, 0, NA, NA, NA} },
1378 /*line 212*/{(0x10), 1, PBF_REG_TASK_CNT_Q3,
1379 NA, 1, 0, pneq,
1381 "PBF: Q3 task_cnt is not 0",
1382 {NA, NA, 0, NA, NA, NA} },
1384 /*line 213*/{(0x10), 1, PBF_REG_TASK_CNT_Q4,
1385 NA, 1, 0, pneq,
1387 "PBF: Q4 task_cnt is not 0",
1388 {NA, NA, 0, NA, NA, NA} },
1390 /*line 214*/{(0x10), 1, PBF_REG_TASK_CNT_Q5,
1391 NA, 1, 0, pneq,
1393 "PBF: Q5 task_cnt is not 0",
1394 {NA, NA, 0, NA, NA, NA} },
1396 /*line 215*/{(0x10), 1, PBF_REG_TASK_CNT_LB_Q,
1397 NA, 1, 0, pneq,
1399 "PBF: LB Q task_cnt is not 0",
1400 {NA, NA, 0, NA, NA, NA} },
1402 /*line 216*/{(0x1F), 1, XCM_REG_CFC_INIT_CRD,
1403 NA, 1, 0, pneq,
1408 /*line 217*/{(0x1F), 1, UCM_REG_CFC_INIT_CRD,
1409 NA, 1, 0, pneq,
1414 /*line 218*/{(0x1F), 1, TCM_REG_CFC_INIT_CRD,
1415 NA, 1, 0, pneq,
1420 /*line 219*/{(0x1F), 1, CCM_REG_CFC_INIT_CRD,
1421 NA, 1, 0, pneq,
1426 /*line 220*/{(0x1F), 1, XCM_REG_XQM_INIT_CRD,
1427 NA, 1, 0, pneq,
1432 /*line 221*/{(0x1F), 1, UCM_REG_UQM_INIT_CRD,
1433 NA, 1, 0, pneq,
1438 /*line 222*/{(0x1F), 1, TCM_REG_TQM_INIT_CRD,
1439 NA, 1, 0, pneq,
1444 /*line 223*/{(0x1F), 1, CCM_REG_CQM_INIT_CRD,
1445 NA, 1, 0, pneq,
1450 /*line 224*/{(0x1F), 1, XCM_REG_TM_INIT_CRD,
1451 NA, 1, 0, pneq,
1456 /*line 225*/{(0x1F), 1, UCM_REG_TM_INIT_CRD,
1457 NA, 1, 0, pneq,
1462 /*line 226*/{(0x1F), 1, XCM_REG_FIC0_INIT_CRD,
1463 NA, 1, 0, pneq,
1468 /*line 227*/{(0x1F), 1, UCM_REG_FIC0_INIT_CRD,
1469 NA, 1, 0, pneq,
1474 /*line 228*/{(0x1F), 1, TCM_REG_FIC0_INIT_CRD,
1475 NA, 1, 0, pneq,
1480 /*line 229*/{(0x1F), 1, CCM_REG_FIC0_INIT_CRD,
1481 NA, 1, 0, pneq,
1486 /*line 230*/{(0x1F), 1, XCM_REG_FIC1_INIT_CRD,
1487 NA, 1, 0, pneq,
1492 /*line 231*/{(0x1F), 1, UCM_REG_FIC1_INIT_CRD,
1493 NA, 1, 0, pneq,
1498 /*line 232*/{(0x1F), 1, TCM_REG_FIC1_INIT_CRD,
1499 NA, 1, 0, pneq,
1504 /*line 233*/{(0x1F), 1, CCM_REG_FIC1_INIT_CRD,
1505 NA, 1, 0, pneq,
1510 /*line 234*/{(0x1), 1, XCM_REG_XX_FREE,
1511 NA, 1, 0, pneq,
1516 /*line 235*/{(0x1E), 1, XCM_REG_XX_FREE,
1517 NA, 1, 0, pneq,
1522 /*line 236*/{(0x1F), 1, UCM_REG_XX_FREE,
1523 NA, 1, 0, pneq,
1528 /*line 237*/{(0x7), 1, TCM_REG_XX_FREE,
1529 NA, 1, 0, pneq,
1534 /*line 238*/{(0x18), 1, TCM_REG_XX_FREE,
1535 NA, 1, 0, pneq,
1540 /*line 239*/{(0x1F), 1, CCM_REG_XX_FREE,
1541 NA, 1, 0, pneq,
1546 /*line 240*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18000,
1547 NA, 1, 0, pneq,
1550 {NA, NA, 0, NA, NA, NA} },
1552 /*line 241*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18040,
1553 NA, 1, 0, pneq,
1558 /*line 242*/{(0x1F), 1, XSEM_REG_FAST_MEMORY + 0x18080,
1559 NA, 1, 0, pneq,
1564 /*line 243*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18000,
1565 NA, 1, 0, pneq,
1570 /*line 244*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18040,
1571 NA, 1, 0, pneq,
1576 /*line 245*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x18080,
1577 NA, 1, 0, pneq,
1582 /*line 246*/{(0x1F), 1, USEM_REG_FAST_MEMORY + 0x180C0,
1583 NA, 1, 0, pneq,
1588 /*line 247*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18000,
1589 NA, 1, 0, pneq,
1594 /*line 248*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18040,
1595 NA, 1, 0, pneq,
1600 /*line 249*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x18080,
1601 NA, 1, 0, pneq,
1606 /*line 250*/{(0x1F), 1, TSEM_REG_FAST_MEMORY + 0x180C0,
1607 NA, 1, 0, pneq,
1612 /*line 251*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18000,
1613 NA, 1, 0, pneq,
1618 /*line 252*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18040,
1619 NA, 1, 0, pneq,
1624 /*line 253*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x18080,
1625 NA, 1, 0, pneq,
1630 /*line 254*/{(0x1F), 1, CSEM_REG_FAST_MEMORY + 0x180C0,
1631 NA, 1, 0, pneq,
1636 /*line 255*/{(0x1F), 1, PRS_REG_TSDM_CURRENT_CREDIT,
1637 NA, 1, 0, pneq,
1639 "PRS: TSDM current credit is not 0",
1640 {NA, NA, 0, NA, NA, NA} },
1642 /*line 256*/{(0x1F), 1, PRS_REG_TCM_CURRENT_CREDIT,
1643 NA, 1, 0, pneq,
1645 "PRS: TCM current credit is not 0",
1646 {NA, NA, 0, NA, NA, NA} },
1648 /*line 257*/{(0x1F), 1, PRS_REG_CFC_LD_CURRENT_CREDIT,
1649 NA, 1, 0, pneq,
1651 "PRS: CFC_LD current credit is not 0",
1652 {NA, NA, 0, NA, NA, NA} },
1654 /*line 258*/{(0x1F), 1, PRS_REG_CFC_SEARCH_CURRENT_CREDIT,
1655 NA, 1, 0, pneq,
1657 "PRS: CFC_SEARCH current credit is not 0",
1658 {NA, NA, 0, NA, NA, NA} },
1660 /*line 259*/{(0x1F), 1, PRS_REG_SRC_CURRENT_CREDIT,
1661 NA, 1, 0, pneq,
1663 "PRS: SRCH current credit is not 0",
1664 {NA, NA, 0, NA, NA, NA} },
1666 /*line 260*/{(0x1F), 1, PRS_REG_PENDING_BRB_PRS_RQ,
1667 NA, 1, 0, pneq,
1669 "PRS: PENDING_BRB_PRS_RQ is not 0",
1670 {NA, NA, 0, NA, NA, NA} },
1672 /*line 261*/{(0x1F), 2, PRS_REG_PENDING_BRB_CAC0_RQ,
1675 "PRS: PENDING_BRB_CAC_RQ is not 0",
1676 {NA, NA, 0, NA, NA, NA} },
1678 /*line 262*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_LSB,
1679 NA, 1, 0, pneq,
1681 "PRS: SERIAL_NUM_STATUS_LSB is not 0",
1682 {NA, NA, 0, NA, NA, NA} },
1684 /*line 263*/{(0x1F), 1, PRS_REG_SERIAL_NUM_STATUS_MSB,
1685 NA, 1, 0, pneq,
1687 "PRS: SERIAL_NUM_STATUS_MSB is not 0",
1688 {NA, NA, 0, NA, NA, NA} },
1690 /*line 264*/{(0x1F), 1, CDU_REG_ERROR_DATA,
1691 NA, 1, 0, pneq,
1693 "CDU: ERROR_DATA is not 0",
1694 {NA, NA, 0, NA, NA, NA} },
1696 /*line 265*/{(0x1F), 1, CCM_REG_STORM_LENGTH_MIS,
1697 NA, 1, 0, pneq,
1700 {NA, NA, 0, NA, NA, NA} },
1702 /*line 266*/{(0x1F), 1, CCM_REG_CSDM_LENGTH_MIS,
1703 NA, 1, 0, pneq,
1706 {NA, NA, 0, NA, NA, NA} },
1708 /*line 267*/{(0x1F), 1, CCM_REG_TSEM_LENGTH_MIS,
1709 NA, 1, 0, pneq,
1712 {NA, NA, 0, NA, NA, NA} },
1714 /*line 268*/{(0x1F), 1, CCM_REG_XSEM_LENGTH_MIS,
1715 NA, 1, 0, pneq,
1718 {NA, NA, 0, NA, NA, NA} },
1720 /*line 269*/{(0x1F), 1, CCM_REG_USEM_LENGTH_MIS,
1721 NA, 1, 0, pneq,
1724 {NA, NA, 0, NA, NA, NA} },
1726 /*line 270*/{(0x1F), 1, CCM_REG_PBF_LENGTH_MIS,
1727 NA, 1, 0, pneq,
1730 {NA, NA, 0, NA, NA, NA} },
1732 /*line 271*/{(0x1F), 1, TCM_REG_STORM_LENGTH_MIS,
1733 NA, 1, 0, pneq,
1736 {NA, NA, 0, NA, NA, NA} },
1738 /*line 272*/{(0x1F), 1, TCM_REG_TSDM_LENGTH_MIS,
1739 NA, 1, 0, pneq,
1742 {NA, NA, 0, NA, NA, NA} },
1744 /*line 273*/{(0x1F), 1, TCM_REG_PRS_LENGTH_MIS,
1745 NA, 1, 0, pneq,
1748 {NA, NA, 0, NA, NA, NA} },
1750 /*line 274*/{(0x1F), 1, TCM_REG_PBF_LENGTH_MIS,
1751 NA, 1, 0, pneq,
1754 {NA, NA, 0, NA, NA, NA} },
1756 /*line 275*/{(0x1F), 1, TCM_REG_USEM_LENGTH_MIS,
1757 NA, 1, 0, pneq,
1760 {NA, NA, 0, NA, NA, NA} },
1762 /*line 276*/{(0x1F), 1, TCM_REG_CSEM_LENGTH_MIS,
1763 NA, 1, 0, pneq,
1766 {NA, NA, 0, NA, NA, NA} },
1768 /*line 277*/{(0x1F), 1, UCM_REG_STORM_LENGTH_MIS,
1769 NA, 1, 0, pneq,
1772 {NA, NA, 0, NA, NA, NA} },
1774 /*line 278*/{(0x1F), 1, UCM_REG_USDM_LENGTH_MIS,
1775 NA, 1, 0, pneq,
1778 {NA, NA, 0, NA, NA, NA} },
1780 /*line 279*/{(0x1F), 1, UCM_REG_TSEM_LENGTH_MIS,
1781 NA, 1, 0, pneq,
1784 {NA, NA, 0, NA, NA, NA} },
1786 /*line 280*/{(0x1F), 1, UCM_REG_CSEM_LENGTH_MIS,
1787 NA, 1, 0, pneq,
1790 {NA, NA, 0, NA, NA, NA} },
1792 /*line 281*/{(0x1F), 1, UCM_REG_XSEM_LENGTH_MIS,
1793 NA, 1, 0, pneq,
1796 {NA, NA, 0, NA, NA, NA} },
1798 /*line 282*/{(0x1F), 1, UCM_REG_DORQ_LENGTH_MIS,
1799 NA, 1, 0, pneq,
1802 {NA, NA, 0, NA, NA, NA} },
1804 /*line 283*/{(0x1F), 1, XCM_REG_STORM_LENGTH_MIS,
1805 NA, 1, 0, pneq,
1808 {NA, NA, 0, NA, NA, NA} },
1810 /*line 284*/{(0x1F), 1, XCM_REG_XSDM_LENGTH_MIS,
1811 NA, 1, 0, pneq,
1814 {NA, NA, 0, NA, NA, NA} },
1816 /*line 285*/{(0x1F), 1, XCM_REG_TSEM_LENGTH_MIS,
1817 NA, 1, 0, pneq,
1820 {NA, NA, 0, NA, NA, NA} },
1822 /*line 286*/{(0x1F), 1, XCM_REG_CSEM_LENGTH_MIS,
1823 NA, 1, 0, pneq,
1826 {NA, NA, 0, NA, NA, NA} },
1828 /*line 287*/{(0x1F), 1, XCM_REG_USEM_LENGTH_MIS,
1829 NA, 1, 0, pneq,
1832 {NA, NA, 0, NA, NA, NA} },
1834 /*line 288*/{(0x1F), 1, XCM_REG_DORQ_LENGTH_MIS,
1835 NA, 1, 0, pneq,
1838 {NA, NA, 0, NA, NA, NA} },
1840 /*line 289*/{(0x1F), 1, XCM_REG_PBF_LENGTH_MIS,
1841 NA, 1, 0, pneq,
1844 {NA, NA, 0, NA, NA, NA} },
1846 /*line 290*/{(0x1F), 1, XCM_REG_NIG0_LENGTH_MIS,
1847 NA, 1, 0, pneq,
1850 {NA, NA, 0, NA, NA, NA} },
1852 /*line 291*/{(0x1F), 1, XCM_REG_NIG1_LENGTH_MIS,
1853 NA, 1, 0, pneq,
1856 {NA, NA, 0, NA, NA, NA} },
1858 /*line 292*/{(0x1F), 1, QM_REG_XQM_WRC_FIFOLVL,
1859 NA, 1, 0, pneq,
1861 "QM: XQM wrc_fifolvl is not 0",
1862 {NA, NA, 0, NA, NA, NA} },
1864 /*line 293*/{(0x1F), 1, QM_REG_UQM_WRC_FIFOLVL,
1865 NA, 1, 0, pneq,
1867 "QM: UQM wrc_fifolvl is not 0",
1868 {NA, NA, 0, NA, NA, NA} },
1870 /*line 294*/{(0x1F), 1, QM_REG_TQM_WRC_FIFOLVL,
1871 NA, 1, 0, pneq,
1873 "QM: TQM wrc_fifolvl is not 0",
1874 {NA, NA, 0, NA, NA, NA} },
1876 /*line 295*/{(0x1F), 1, QM_REG_CQM_WRC_FIFOLVL,
1877 NA, 1, 0, pneq,
1879 "QM: CQM wrc_fifolvl is not 0",
1880 {NA, NA, 0, NA, NA, NA} },
1882 /*line 296*/{(0x1F), 1, QM_REG_QSTATUS_LOW,
1883 NA, 1, 0, pneq,
1885 "QM: QSTATUS_LOW is not 0",
1886 {NA, NA, 0, NA, NA, NA} },
1888 /*line 297*/{(0x1F), 1, QM_REG_QSTATUS_HIGH,
1889 NA, 1, 0, pneq,
1891 "QM: QSTATUS_HIGH is not 0",
1892 {NA, NA, 0, NA, NA, NA} },
1894 /*line 298*/{(0x1F), 1, QM_REG_PAUSESTATE0,
1895 NA, 1, 0, pneq,
1897 "QM: PAUSESTATE0 is not 0",
1898 {NA, NA, 0, NA, NA, NA} },
1900 /*line 299*/{(0x1F), 1, QM_REG_PAUSESTATE1,
1901 NA, 1, 0, pneq,
1903 "QM: PAUSESTATE1 is not 0",
1904 {NA, NA, 0, NA, NA, NA} },
1906 /*line 300*/{(0x1F), 1, QM_REG_OVFQNUM,
1907 NA, 1, 0, pneq,
1909 "QM: OVFQNUM is not 0",
1910 {NA, NA, 0, NA, NA, NA} },
1912 /*line 301*/{(0x1F), 1, QM_REG_OVFERROR,
1913 NA, 1, 0, pneq,
1915 "QM: OVFERROR is not 0",
1916 {NA, NA, 0, NA, NA, NA} },
1918 /*line 302*/{(0x1F), 6, QM_REG_PTRTBL,
1924 /*line 303*/{(0x1F), 1, BRB1_REG_BRB1_PRTY_STS,
1925 NA, 1, 0, pand_neq,
1927 "BRB1: parity status is not 0",
1928 {NA, NA, ~0x8, 0, NA, NA} },
1930 /*line 304*/{(0x1F), 1, CDU_REG_CDU_PRTY_STS,
1931 NA, 1, 0, pneq,
1933 "CDU: parity status is not 0",
1934 {NA, NA, 0, NA, NA, NA} },
1936 /*line 305*/{(0x1F), 1, CFC_REG_CFC_PRTY_STS,
1937 NA, 1, 0, pand_neq,
1939 "CFC: parity status is not 0",
1940 {NA, NA, ~0x2, 0, NA, NA} },
1942 /*line 306*/{(0x1F), 1, CSDM_REG_CSDM_PRTY_STS,
1943 NA, 1, 0, pneq,
1945 "CSDM: parity status is not 0",
1946 {NA, NA, 0, NA, NA, NA} },
1948 /*line 307*/{(0x3), 1, DBG_REG_DBG_PRTY_STS,
1949 NA, 1, 0, pneq,
1951 "DBG: parity status is not 0",
1952 {NA, NA, 0, NA, NA, NA} },
1954 /*line 308*/{(0x1F), 1, DMAE_REG_DMAE_PRTY_STS,
1955 NA, 1, 0, pneq,
1957 "DMAE: parity status is not 0",
1958 {NA, NA, 0, NA, NA, NA} },
1960 /*line 309*/{(0x1F), 1, DORQ_REG_DORQ_PRTY_STS,
1961 NA, 1, 0, pneq,
1963 "DORQ: parity status is not 0",
1964 {NA, NA, 0, NA, NA, NA} },
1966 /*line 310*/{(0x1), 1, TCM_REG_TCM_PRTY_STS,
1967 NA, 1, 0, pand_neq,
1969 "TCM: parity status is not 0",
1970 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1972 /*line 311*/{(0x1E), 1, TCM_REG_TCM_PRTY_STS,
1973 NA, 1, 0, pneq,
1975 "TCM: parity status is not 0",
1976 {NA, NA, 0, NA, NA, NA} },
1978 /*line 312*/{(0x1), 1, CCM_REG_CCM_PRTY_STS,
1979 NA, 1, 0, pand_neq,
1981 "CCM: parity status is not 0",
1982 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1984 /*line 313*/{(0x1E), 1, CCM_REG_CCM_PRTY_STS,
1985 NA, 1, 0, pneq,
1987 "CCM: parity status is not 0",
1988 {NA, NA, 0, NA, NA, NA} },
1990 /*line 314*/{(0x1), 1, UCM_REG_UCM_PRTY_STS,
1991 NA, 1, 0, pand_neq,
1993 "UCM: parity status is not 0",
1994 {NA, NA, ~0x3ffc0, 0, NA, NA} },
1996 /*line 315*/{(0x1E), 1, UCM_REG_UCM_PRTY_STS,
1997 NA, 1, 0, pneq,
1999 "UCM: parity status is not 0",
2000 {NA, NA, 0, NA, NA, NA} },
2002 /*line 316*/{(0x1), 1, XCM_REG_XCM_PRTY_STS,
2003 NA, 1, 0, pand_neq,
2005 "XCM: parity status is not 0",
2006 {NA, NA, ~0x3ffc0, 0, NA, NA} },
2008 /*line 317*/{(0x1E), 1, XCM_REG_XCM_PRTY_STS,
2009 NA, 1, 0, pneq,
2011 "XCM: parity status is not 0",
2012 {NA, NA, 0, NA, NA, NA} },
2014 /*line 318*/{(0x1), 1, HC_REG_HC_PRTY_STS,
2015 NA, 1, 0, pand_neq,
2017 "HC: parity status is not 0",
2018 {NA, NA, ~0x1, 0, NA, NA} },
2020 /*line 319*/{(0x1), 1, MISC_REG_MISC_PRTY_STS,
2021 NA, 1, 0, pand_neq,
2023 "MISC: parity status is not 0",
2024 {NA, NA, ~0x1, 0, NA, NA} },
2026 /*line 320*/{(0x1F), 1, PRS_REG_PRS_PRTY_STS,
2027 NA, 1, 0, pneq,
2029 "PRS: parity status is not 0",
2030 {NA, NA, 0, NA, NA, NA} },
2032 /*line 321*/{(0x1F), 1, PXP_REG_PXP_PRTY_STS,
2033 NA, 1, 0, pneq,
2035 "PXP: parity status is not 0",
2036 {NA, NA, 0, NA, NA, NA} },
2038 /*line 322*/{(0x1F), 1, QM_REG_QM_PRTY_STS,
2039 NA, 1, 0, pneq,
2041 "QM: parity status is not 0",
2042 {NA, NA, 0, NA, NA, NA} },
2044 /*line 323*/{(0x1), 1, SRC_REG_SRC_PRTY_STS,
2045 NA, 1, 0, pand_neq,
2047 "SRCH: parity status is not 0",
2048 {NA, NA, ~0x4, 0, NA, NA} },
2050 /*line 324*/{(0x1F), 1, TSDM_REG_TSDM_PRTY_STS,
2051 NA, 1, 0, pneq,
2053 "TSDM: parity status is not 0",
2054 {NA, NA, 0, NA, NA, NA} },
2056 /*line 325*/{(0x1F), 1, USDM_REG_USDM_PRTY_STS,
2057 NA, 1, 0, pand_neq,
2059 "USDM: parity status is not 0",
2060 {NA, NA, ~0x20, 0, NA, NA} },
2062 /*line 326*/{(0x1F), 1, XSDM_REG_XSDM_PRTY_STS,
2063 NA, 1, 0, pneq,
2065 "XSDM: parity status is not 0",
2066 {NA, NA, 0, NA, NA, NA} },
2068 /*line 327*/{(0x1F), 1, GRCBASE_XPB + PB_REG_PB_PRTY_STS,
2069 NA, 1, 0, pneq,
2071 "XPB: parity status is not 0",
2072 {NA, NA, 0, NA, NA, NA} },
2074 /*line 328*/{(0x1F), 1, GRCBASE_UPB + PB_REG_PB_PRTY_STS,
2075 NA, 1, 0, pneq,
2077 "UPB: parity status is not 0",
2078 {NA, NA, 0, NA, NA, NA} },
2080 /*line 329*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_0,
2081 NA, 1, 0, pneq,
2083 "CSEM: parity status 0 is not 0",
2084 {NA, NA, 0, NA, NA, NA} },
2086 /*line 330*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_0,
2087 NA, 1, 0, pand_neq,
2089 "PXP2: parity status 0 is not 0",
2090 {NA, NA, ~0xfff40020, 0, NA, NA} },
2092 /*line 331*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_0,
2093 NA, 1, 0, pand_neq,
2095 "PXP2: parity status 0 is not 0",
2096 {NA, NA, ~0x20, 0, NA, NA} },
2098 /*line 332*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_0,
2099 NA, 1, 0, pneq,
2101 "TSEM: parity status 0 is not 0",
2102 {NA, NA, 0, NA, NA, NA} },
2104 /*line 333*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_0,
2105 NA, 1, 0, pneq,
2107 "USEM: parity status 0 is not 0",
2108 {NA, NA, 0, NA, NA, NA} },
2110 /*line 334*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_0,
2111 NA, 1, 0, pneq,
2113 "XSEM: parity status 0 is not 0",
2114 {NA, NA, 0, NA, NA, NA} },
2116 /*line 335*/{(0x1F), 1, CSEM_REG_CSEM_PRTY_STS_1,
2117 NA, 1, 0, pneq,
2119 "CSEM: parity status 1 is not 0",
2120 {NA, NA, 0, NA, NA, NA} },
2122 /*line 336*/{(0x1), 1, PXP2_REG_PXP2_PRTY_STS_1,
2123 NA, 1, 0, pand_neq,
2125 "PXP2: parity status 1 is not 0",
2126 {NA, NA, ~0x20, 0, NA, NA} },
2128 /*line 337*/{(0x1E), 1, PXP2_REG_PXP2_PRTY_STS_1,
2129 NA, 1, 0, pneq,
2131 "PXP2: parity status 1 is not 0",
2132 {NA, NA, 0, NA, NA, NA} },
2134 /*line 338*/{(0x1F), 1, TSEM_REG_TSEM_PRTY_STS_1,
2135 NA, 1, 0, pneq,
2137 "TSEM: parity status 1 is not 0",
2138 {NA, NA, 0, NA, NA, NA} },
2140 /*line 339*/{(0x1F), 1, USEM_REG_USEM_PRTY_STS_1,
2141 NA, 1, 0, pneq,
2143 "USEM: parity status 1 is not 0",
2144 {NA, NA, 0, NA, NA, NA} },
2146 /*line 340*/{(0x1F), 1, XSEM_REG_XSEM_PRTY_STS_1,
2147 NA, 1, 0, pneq,
2149 "XSEM: parity status 1 is not 0",
2150 {NA, NA, 0, NA, NA, NA} },
2152 /*line 341*/{(0x1C), 1, PGLUE_B_REG_PGLUE_B_PRTY_STS,
2153 NA, 1, 0, pneq,
2155 "PGLUE_B: parity status is not 0",
2156 {NA, NA, 0, NA, NA, NA} },
2158 /*line 342*/{(0x2), 2, QM_REG_QTASKCTR_EXT_A_0,
2162 {NA, NA, 0, NA, NA, NA} },
2164 /*line 343*/{(0x2), 1, QM_REG_QSTATUS_LOW_EXT_A,
2165 NA, 1, 0, pneq,
2167 "QM: QSTATUS_LOW_EXT_A is not 0",
2168 {NA, NA, 0, NA, NA, NA} },
2170 /*line 344*/{(0x2), 1, QM_REG_QSTATUS_HIGH_EXT_A,
2171 NA, 1, 0, pneq,
2173 "QM: QSTATUS_HIGH_EXT_A is not 0",
2174 {NA, NA, 0, NA, NA, NA} },
2176 /*line 345*/{(0x1E), 1, QM_REG_PAUSESTATE2,
2177 NA, 1, 0, pneq,
2179 "QM: PAUSESTATE2 is not 0",
2180 {NA, NA, 0, NA, NA, NA} },
2182 /*line 346*/{(0x1E), 1, QM_REG_PAUSESTATE3,
2183 NA, 1, 0, pneq,
2185 "QM: PAUSESTATE3 is not 0",
2186 {NA, NA, 0, NA, NA, NA} },
2188 /*line 347*/{(0x2), 1, QM_REG_PAUSESTATE4,
2189 NA, 1, 0, pneq,
2191 "QM: PAUSESTATE4 is not 0",
2192 {NA, NA, 0, NA, NA, NA} },
2194 /*line 348*/{(0x2), 1, QM_REG_PAUSESTATE5,
2195 NA, 1, 0, pneq,
2197 "QM: PAUSESTATE5 is not 0",
2198 {NA, NA, 0, NA, NA, NA} },
2200 /*line 349*/{(0x2), 1, QM_REG_PAUSESTATE6,
2201 NA, 1, 0, pneq,
2203 "QM: PAUSESTATE6 is not 0",
2204 {NA, NA, 0, NA, NA, NA} },
2206 /*line 350*/{(0x2), 1, QM_REG_PAUSESTATE7,
2207 NA, 1, 0, pneq,
2209 "QM: PAUSESTATE7 is not 0",
2210 {NA, NA, 0, NA, NA, NA} },
2212 /*line 351*/{(0x2), 6, QM_REG_PTRTBL_EXT_A,
2218 /*line 352*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_OCCURRED,
2222 {NA, NA, 0, NA, NA, NA} },
2224 /*line 353*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_0,
2228 {NA, NA, 0, NA, NA, NA} },
2230 /*line 354*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_1,
2234 {NA, NA, 0, NA, NA, NA} },
2236 /*line 355*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_2,
2240 {NA, NA, 0, NA, NA, NA} },
2242 /*line 356*/{(0x1E), 1, MISC_REG_AEU_SYS_KILL_STATUS_3,
2246 {NA, NA, 0, NA, NA, NA} },
2248 /*line 357*/{(0x1E), 1, MISC_REG_PCIE_HOT_RESET,
2252 {NA, NA, 0, NA, NA, NA} },
2254 /*line 358*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2257 "NIG: interrupt 0 is active",
2258 {NA, NA, ~0x300, 0, NA, NA} },
2260 /*line 359*/{(0x1F), 1, NIG_REG_NIG_INT_STS_0,
2264 {NA, NA, 0x300, NA, NA, NA} },
2266 /*line 360*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2270 {NA, NA, 0x783FF03, 0, NA, NA} },
2272 /*line 361*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2276 {NA, NA, ~0x783FF0F, 0, NA, NA} },
2278 /*line 362*/{(0x1F), 1, NIG_REG_NIG_INT_STS_1,
2282 {NA, NA, 0xC, 0, NA, NA} },
2284 /*line 363*/{(0x2), 1, NIG_REG_NIG_PRTY_STS,
2288 {NA, NA, ~0xFFC00000, 0, NA, NA} },
2290 /*line 364*/{(0x1C), 1, NIG_REG_NIG_PRTY_STS_0,
2293 "NIG: parity 0 interrupt is active",
2294 {NA, NA, ~0xFFC00000, 0, NA, NA} },
2296 /*line 365*/{(0x4), 1, NIG_REG_NIG_PRTY_STS_1,
2300 {NA, NA, 0xff, 0, NA, NA} },
2302 /*line 366*/{(0x18), 1, NIG_REG_NIG_PRTY_STS_1,
2306 {NA, NA, 0, NA, NA, NA} },
2308 /*line 367*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2311 "TSEM: interrupt 0 is active",
2312 {NA, NA, ~0x10000000, 0, NA, NA} },
2314 /*line 368*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_0,
2317 "TSEM: interrupt 0 is active",
2318 {NA, NA, 0x10000000, NA, NA, NA} },
2320 /*line 369*/{(0x1F), 1, TSEM_REG_TSEM_INT_STS_1,
2324 {NA, NA, 0, NA, NA, NA} },
2326 /*line 370*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2329 "CSEM: interrupt 0 is active",
2330 {NA, NA, ~0x10000000, 0, NA, NA} },
2332 /*line 371*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_0,
2335 "CSEM: interrupt 0 is active",
2336 {NA, NA, 0x10000000, NA, NA, NA} },
2338 /*line 372*/{(0x1F), 1, CSEM_REG_CSEM_INT_STS_1,
2342 {NA, NA, 0, NA, NA, NA} },
2344 /*line 373*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2347 "USEM: interrupt 0 is active",
2348 {NA, NA, ~0x10000000, 0, NA, NA} },
2350 /*line 374*/{(0x1F), 1, USEM_REG_USEM_INT_STS_0,
2353 "USEM: interrupt 0 is active",
2354 {NA, NA, 0x10000000, NA, NA, NA} },
2356 /*line 375*/{(0x1F), 1, USEM_REG_USEM_INT_STS_1,
2360 {NA, NA, 0, NA, NA, NA} },
2362 /*line 376*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2365 "XSEM: interrupt 0 is active",
2366 {NA, NA, ~0x10000000, 0, NA, NA} },
2368 /*line 377*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_0,
2371 "XSEM: interrupt 0 is active",
2372 {NA, NA, 0x10000000, NA, NA, NA} },
2374 /*line 378*/{(0x1F), 1, XSEM_REG_XSEM_INT_STS_1,
2378 {NA, NA, 0, NA, NA, NA} },
2380 /*line 379*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_0,
2383 "TSDM: interrupt 0 is active",
2384 {NA, NA, 0, NA, NA, NA} },
2386 /*line 380*/{(0x1F), 1, TSDM_REG_TSDM_INT_STS_1,
2389 "TSDM: interrupt 0 is active",
2390 {NA, NA, 0, NA, NA, NA} },
2392 /*line 381*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_0,
2395 "CSDM: interrupt 0 is active",
2396 {NA, NA, 0, NA, NA, NA} },
2398 /*line 382*/{(0x1F), 1, CSDM_REG_CSDM_INT_STS_1,
2401 "CSDM: interrupt 0 is active",
2402 {NA, NA, 0, NA, NA, NA} },
2404 /*line 383*/{(0x1F), 1, USDM_REG_USDM_INT_STS_0,
2407 "USDM: interrupt 0 is active",
2408 {NA, NA, 0, NA, NA, NA} },
2410 /*line 384*/{(0x1F), 1, USDM_REG_USDM_INT_STS_1,
2413 "USDM: interrupt 0 is active",
2414 {NA, NA, 0, NA, NA, NA} },
2416 /*line 385*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_0,
2419 "XSDM: interrupt 0 is active",
2420 {NA, NA, 0, NA, NA, NA} },
2422 /*line 386*/{(0x1F), 1, XSDM_REG_XSDM_INT_STS_1,
2425 "XSDM: interrupt 0 is active",
2426 {NA, NA, 0, NA, NA, NA} },
2428 /*line 387*/{(0x2), 1, HC_REG_HC_PRTY_STS,
2429 NA, 1, 0, pneq,
2431 "HC: parity status is not 0",
2432 {NA, NA, 0, NA, NA, NA} },
2434 /*line 388*/{(0x1E), 1, MISC_REG_MISC_PRTY_STS,
2435 NA, 1, 0, pneq,
2437 "MISC: parity status is not 0",
2438 {NA, NA, 0, NA, NA, NA} },
2440 /*line 389*/{(0x1E), 1, SRC_REG_SRC_PRTY_STS,
2441 NA, 1, 0, pneq,
2443 "SRCH: parity status is not 0",
2444 {NA, NA, 0, NA, NA, NA} },
2446 /*line 390*/{(0xC), 3, QM_REG_BYTECRD0,
2447 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2449 "QM: Byte credit 0 is not equal to initial credit",
2452 /*line 391*/{(0xC), 3, QM_REG_BYTECRD1,
2453 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2458 /*line 392*/{(0xC), 3, QM_REG_BYTECRD2,
2459 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2464 /*line 393*/{(0x1C), 1, QM_REG_VOQCRDERRREG,
2465 NA, 1, 0, pand_neq,
2467 "QM: VOQ credit error register is not 0 (VOQ credit overflow/underflow)",
2468 {NA, NA, 0xFFFF, 0, NA, NA} },
2470 /*line 394*/{(0x1C), 1, QM_REG_BYTECRDERRREG,
2471 NA, 1, 0, pand_neq,
2473 "QM: Byte credit error register is not 0 (Byte credit overflow/underflow)",
2474 {NA, NA, 0xFFF, 0, NA, NA} },
2476 /*line 395*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_31_0,
2477 NA, 1, 0, pneq,
2479 "PGL: FLR request is set for VF addresses 31-0",
2480 {NA, NA, 0, NA, NA, NA} },
2482 /*line 396*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_63_32,
2483 NA, 1, 0, pneq,
2486 {NA, NA, 0, NA, NA, NA} },
2488 /*line 397*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_95_64,
2489 NA, 1, 0, pneq,
2492 {NA, NA, 0, NA, NA, NA} },
2494 /*line 398*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_VF_127_96,
2495 NA, 1, 0, pneq,
2498 {NA, NA, 0, NA, NA, NA} },
2500 /*line 399*/{(0x1C), 1, PGLUE_B_REG_FLR_REQUEST_PF_7_0,
2501 NA, 1, 0, pneq,
2503 "PGL: FLR request is set for PF addresses 7-0",
2504 {NA, NA, 0, NA, NA, NA} },
2506 /*line 400*/{(0x1C), 1, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST,
2507 NA, 1, 0, pneq,
2510 {NA, NA, 0, NA, NA, NA} },
2512 /*line 401*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_A_REQUEST,
2513 NA, 1, 0, pneq,
2516 {NA, NA, 0, NA, NA, NA} },
2518 /*line 402*/{(0x1C), 1, PGLUE_B_REG_CFG_SPACE_B_REQUEST,
2519 NA, 1, 0, pneq,
2522 {NA, NA, 0, NA, NA, NA} },
2524 /*line 403*/{(0x1C), 1, IGU_REG_ERROR_HANDLING_DATA_VALID,
2525 NA, NA, 0, pneq,
2528 {NA, NA, 0, NA, NA, NA} },
2530 /*line 404*/{(0x1C), 1, IGU_REG_ATTN_WRITE_DONE_PENDING,
2534 {NA, NA, 0, NA, NA, NA} },
2536 /*line 405*/{(0x1C), 1, IGU_REG_WRITE_DONE_PENDING,
2540 {NA, NA, 0, NA, NA, NA} },
2542 /*line 406*/{(0x1C), 1, IGU_REG_IGU_PRTY_STS,
2543 NA, 1, 0, pneq,
2545 "IGU: parity status is not 0",
2546 {NA, NA, 0, NA, NA, NA} },
2548 /*line 407*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2549 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2552 {NA, NA, 0x4000000, 0, NA, NA} },
2554 /*line 408*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2555 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0, 1, 0, pand_neq,
2558 {NA, NA, 0x4000000, 0, NA, NA} },
2560 /*line 409*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2561 MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2564 {NA, NA, 0x4000000, 0, NA, NA} },
2566 /*line 410*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2567 MISC_REG_AEU_AFTER_INVERT_4_FUNC_1, 1, 0, pand_neq,
2570 {NA, NA, 0x4000000, 0, NA, NA} },
2572 /*line 411*/{(0x1E), 3, MISC_REG_GRC_TIMEOUT_ATTN,
2573 MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2576 {NA, NA, 0x4000000, 0, NA, NA} },
2578 /*line 412*/{(0x1C), 3, MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID,
2579 MISC_REG_AEU_AFTER_INVERT_4_MCP, 1, 0, pand_neq,
2582 {NA, NA, 0x4000000, 0, NA, NA} },
2584 /*line 413*/{(0x1C), 1, IGU_REG_SILENT_DROP,
2585 NA, 1, 0, pneq,
2588 {NA, NA, 0, NA, NA, NA} },
2590 /*line 414*/{(0x1C), 1, PXP2_REG_PSWRQ_BW_CREDIT,
2591 NA, 1, 0, pneq,
2594 {NA, NA, 0x2D, NA, NA, NA} },
2596 /*line 415*/{(0x1C), 1, IGU_REG_SB_CTRL_FSM,
2597 NA, 1, 0, pneq,
2600 {NA, NA, 0, NA, NA, NA} },
2602 /*line 416*/{(0x1C), 1, IGU_REG_INT_HANDLE_FSM,
2603 NA, 1, 0, pneq,
2606 {NA, NA, 0, NA, NA, NA} },
2608 /*line 417*/{(0x1C), 1, IGU_REG_ATTN_FSM,
2609 NA, 1, 0, pand_neq,
2612 {NA, NA, ~0x2, 0, NA, NA} },
2614 /*line 418*/{(0x1C), 1, IGU_REG_CTRL_FSM,
2615 NA, 1, 0, pand_neq,
2618 {NA, NA, ~0x1, 0, NA, NA} },
2620 /*line 419*/{(0x1C), 1, IGU_REG_PXP_ARB_FSM,
2621 NA, 1, 0, pand_neq,
2624 {NA, NA, ~0x1, 0, NA, NA} },
2626 /*line 420*/{(0x1C), 1, IGU_REG_PENDING_BITS_STATUS,
2630 {NA, NA, 0, NA, NA, NA} },
2632 /*line 421*/{(0x10), 3, QM_REG_VOQCREDIT_0,
2633 QM_REG_VOQINITCREDIT_0, 1, 0, pneq_r2,
2638 /*line 422*/{(0x10), 3, QM_REG_VOQCREDIT_1,
2639 QM_REG_VOQINITCREDIT_1, 1, 0, pneq_r2,
2644 /*line 423*/{(0x10), 3, QM_REG_VOQCREDIT_2,
2645 QM_REG_VOQINITCREDIT_2, 1, 0, pneq_r2,
2650 /*line 424*/{(0x10), 3, QM_REG_VOQCREDIT_3,
2651 QM_REG_VOQINITCREDIT_3, 1, 0, pneq_r2,
2656 /*line 425*/{(0x10), 3, QM_REG_VOQCREDIT_4,
2657 QM_REG_VOQINITCREDIT_4, 1, 0, pneq_r2,
2662 /*line 426*/{(0x10), 3, QM_REG_VOQCREDIT_5,
2663 QM_REG_VOQINITCREDIT_5, 1, 0, pneq_r2,
2668 /*line 427*/{(0x10), 3, QM_REG_VOQCREDIT_6,
2669 QM_REG_VOQINITCREDIT_6, 1, 0, pneq_r2,
2674 /*line 428*/{(0x10), 3, QM_REG_BYTECRD0,
2675 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2677 "QM: Byte credit 0 is not equal to initial credit",
2680 /*line 429*/{(0x10), 3, QM_REG_BYTECRD1,
2681 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2686 /*line 430*/{(0x10), 3, QM_REG_BYTECRD2,
2687 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2692 /*line 431*/{(0x10), 3, QM_REG_BYTECRD3,
2693 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2698 /*line 432*/{(0x10), 3, QM_REG_BYTECRD4,
2699 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2704 /*line 433*/{(0x10), 3, QM_REG_BYTECRD5,
2705 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2710 /*line 434*/{(0x10), 3, QM_REG_BYTECRD6,
2711 QM_REG_BYTECRDINITVAL, 1, 0, pneq_r2,
2716 /*line 435*/{(0x10), 1, QM_REG_FWVOQ0TOHWVOQ,
2717 NA, 1, 0, peq,
2720 {NA, NA, 0x7, NA, NA, NA} },
2722 /*line 436*/{(0x10), 1, QM_REG_FWVOQ1TOHWVOQ,
2723 NA, 1, 0, peq,
2726 {NA, NA, 0x7, NA, NA, NA} },
2728 /*line 437*/{(0x10), 1, QM_REG_FWVOQ2TOHWVOQ,
2729 NA, 1, 0, peq,
2732 {NA, NA, 0x7, NA, NA, NA} },
2734 /*line 438*/{(0x10), 1, QM_REG_FWVOQ3TOHWVOQ,
2735 NA, 1, 0, peq,
2738 {NA, NA, 0x7, NA, NA, NA} },
2740 /*line 439*/{(0x10), 1, QM_REG_FWVOQ4TOHWVOQ,
2741 NA, 1, 0, peq,
2744 {NA, NA, 0x7, NA, NA, NA} },
2746 /*line 440*/{(0x10), 1, QM_REG_FWVOQ5TOHWVOQ,
2747 NA, 1, 0, peq,
2750 {NA, NA, 0x7, NA, NA, NA} },
2752 /*line 441*/{(0x10), 1, QM_REG_FWVOQ6TOHWVOQ,
2753 NA, 1, 0, peq,
2756 {NA, NA, 0x7, NA, NA, NA} },
2758 /*line 442*/{(0x10), 1, QM_REG_FWVOQ7TOHWVOQ,
2759 NA, 1, 0, peq,
2762 {NA, NA, 0x7, NA, NA, NA} },
2764 /*line 443*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT0_EMPTY,
2765 NA, 1, 0, pneq,
2767 "NIG: Port 0 EOP FIFO is not empty",
2770 /*line 444*/{(0x1F), 1, NIG_REG_INGRESS_EOP_PORT1_EMPTY,
2771 NA, 1, 0, pneq,
2776 /*line 445*/{(0x1F), 1, NIG_REG_INGRESS_EOP_LB_EMPTY,
2777 NA, 1, 0, pneq,
2782 /*line 446*/{(0x1F), 1, NIG_REG_INGRESS_RMP0_DSCR_EMPTY,
2783 NA, 1, 0, pneq,
2785 "NIG: Port 0 RX MCP descriptor FIFO is not empty",
2788 /*line 447*/{(0x1F), 1, NIG_REG_INGRESS_RMP1_DSCR_EMPTY,
2789 NA, 1, 0, pneq,
2794 /*line 448*/{(0x1F), 1, NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY,
2795 NA, 1, 0, pneq,
2800 /*line 449*/{(0x1F), 1, NIG_REG_EGRESS_MNG0_FIFO_EMPTY,
2801 NA, 1, 0, pneq,
2803 "NIG: Port 0 TX MCP FIFO is not empty",
2806 /*line 450*/{(0x1F), 1, NIG_REG_EGRESS_MNG1_FIFO_EMPTY,
2807 NA, 1, 0, pneq,
2812 /*line 451*/{(0x1F), 1, NIG_REG_EGRESS_DEBUG_FIFO_EMPTY,
2813 NA, 1, 0, pneq,
2818 /*line 452*/{(0x1F), 1, NIG_REG_EGRESS_DELAY0_EMPTY,
2819 NA, 1, 0, pneq,
2824 /*line 453*/{(0x1F), 1, NIG_REG_EGRESS_DELAY1_EMPTY,
2825 NA, 1, 0, pneq,
2830 /*line 454*/{(0x1F), 1, NIG_REG_LLH0_FIFO_EMPTY,
2831 NA, 1, 0, pneq,
2833 "NIG: Port 0 RX LLH FIFO is not empty",
2836 /*line 455*/{(0x1F), 1, NIG_REG_LLH1_FIFO_EMPTY,
2837 NA, 1, 0, pneq,
2842 /*line 456*/{(0x1C), 1, NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY,
2843 NA, 1, 0, pneq,
2845 "NIG: Port 0 TX MCP FIFO for traffic going to the host is not empty",
2848 /*line 457*/{(0x1C), 1, NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY,
2849 NA, 1, 0, pneq,
2854 /*line 458*/{(0x1C), 1, NIG_REG_P0_TLLH_FIFO_EMPTY,
2855 NA, 1, 0, pneq,
2857 "NIG: Port 0 TX LLH FIFO is not empty",
2860 /*line 459*/{(0x1C), 1, NIG_REG_P1_TLLH_FIFO_EMPTY,
2861 NA, 1, 0, pneq,
2866 /*line 460*/{(0x1C), 1, NIG_REG_P0_HBUF_DSCR_EMPTY,
2867 NA, 1, 0, pneq,
2869 "NIG: Port 0 RX MCP descriptor FIFO for traffic from the host is not empty",
2872 /*line 461*/{(0x1C), 1, NIG_REG_P1_HBUF_DSCR_EMPTY,
2873 NA, 1, 0, pneq,
2878 /*line 462*/{(0x18), 1, NIG_REG_P0_RX_MACFIFO_EMPTY,
2879 NA, 1, 0, pneq,
2881 "NIG: Port 0 RX MAC interface FIFO is not empty",
2884 /*line 463*/{(0x18), 1, NIG_REG_P1_RX_MACFIFO_EMPTY,
2885 NA, 1, 0, pneq,
2890 /*line 464*/{(0x18), 1, NIG_REG_P0_TX_MACFIFO_EMPTY,
2891 NA, 1, 0, pneq,
2893 "NIG: Port 0 TX MAC interface FIFO is not empty",
2896 /*line 465*/{(0x18), 1, NIG_REG_P1_TX_MACFIFO_EMPTY,
2897 NA, 1, 0, pneq,
2902 /*line 466*/{(0x10), 1, NIG_REG_EGRESS_DELAY2_EMPTY,
2903 NA, 1, 0, pneq,
2908 /*line 467*/{(0x10), 1, NIG_REG_EGRESS_DELAY3_EMPTY,
2909 NA, 1, 0, pneq,
2914 /*line 468*/{(0x10), 1, NIG_REG_EGRESS_DELAY4_EMPTY,
2915 NA, 1, 0, pneq,
2920 /*line 469*/{(0x10), 1, NIG_REG_EGRESS_DELAY5_EMPTY,
2921 NA, 1, 0, pneq,
2952 for (i = 0; i < rec->loop; i++) { in bnx2x_idle_chk6()
2960 rd_ptr = ((rec->pred_args.val1 & 0x3FFFFFC0) >> 6); in bnx2x_idle_chk6()
2961 wr_ptr = ((((rec->pred_args.val1 & 0xC0000000) >> 30) & 0x3) | in bnx2x_idle_chk6()
2962 ((rec->pred_args.val2 & 0x3FFFFF) << 2)); in bnx2x_idle_chk6()
2967 "QM: PTRTBL entry %d- rd_ptr is not equal to wr_ptr. Values are 0x%x and 0x%x\n", in bnx2x_idle_chk6()
2973 rd_bank = ((rec->pred_args.val1 & 0x30) >> 4); in bnx2x_idle_chk6()
2974 wr_bank = (rec->pred_args.val1 & 0x03); in bnx2x_idle_chk6()
2979 "QM: PTRTBL entry %d - rd_bank is not equal to wr_bank. Values are 0x%x 0x%x\n", in bnx2x_idle_chk6()
2993 for (i = 0; i < rec->loop; i++) { in bnx2x_idle_chk7()
2994 /* make sure cam entry is valid (bit 0) */ in bnx2x_idle_chk7()
2995 if ((REG_RD(bp, (rec->reg2 + i * 4)) & 0x1) != 0x1) in bnx2x_idle_chk7()
3008 rec->pred_args.val1 &= 0x78; in bnx2x_idle_chk7()
3012 rec->pred_args.val1 &= 0x1E000000; in bnx2x_idle_chk7()
3022 "%s. Values are 0x%x 0x%x\n", rec->fail_msg, in bnx2x_idle_chk7()
3046 idle_chk_errors = 0; in bnx2x_idle_chk()
3047 idle_chk_warnings = 0; in bnx2x_idle_chk()
3057 for (st_ind = 0; st_ind < ST_DB_LINES; st_ind++) { in bnx2x_idle_chk()
3076 "%s.Value is 0x%x\n", rec.fail_msg, in bnx2x_idle_chk()
3085 for (i = 0; i < rec.loop; i++) { in bnx2x_idle_chk()
3091 "%s. Value is 0x%x in loop %d\n", in bnx2x_idle_chk()
3107 "%s. Values are 0x%x 0x%x\n", in bnx2x_idle_chk()
3115 for (i = 0; i < rec.loop; i++) { in bnx2x_idle_chk()
3123 "%s. Values are 0x%x 0x%x in loop %d\n", in bnx2x_idle_chk()
3140 if (REG_RD(bp, rec.reg3) != 0) { in bnx2x_idle_chk()
3143 "%s. Values are 0x%x 0x%x\n", in bnx2x_idle_chk()
3174 if (idle_chk_errors == 0) { in bnx2x_idle_chk()