Lines Matching +full:bp +full:- +full:disabled +full:- +full:ports
3 * Copyright (c) 2007-2013 Broadcom Corporation
21 #include <linux/dma-mapping.h>
37 * to break this driver due to amount of abuse of in-kernel interfaces
42 #define DRV_MODULE_VERSION "1.713.36-0"
53 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) argument
94 bp->dev ? (bp->dev->name) : "?", \
99 if (unlikely(bp->msg_enable & (__mask))) \
105 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
111 if (unlikely(bp->msg_enable & (__mask))) \
118 if (unlikely(netif_msg_probe(bp))) \
121 bp->dev ? (bp->dev->name) : "?", \
130 bp->dev ? (bp->dev->name) : "?", \
137 /* before we have a dev->name use dev_info() */
140 if (unlikely(netif_msg_probe(bp))) \
141 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
145 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
149 bp->panic = 1; \
151 bnx2x_panic_dump(bp, true); \
156 bp->panic = 1; \
158 bnx2x_panic_dump(bp, false); \
162 #define bnx2x_mc_addr(ha) ((ha)->addr)
163 #define bnx2x_uc_addr(ha) ((ha)->addr)
169 #define REG_ADDR(bp, offset) ((bp->regview) + (offset)) argument
171 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) argument
172 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) argument
173 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) argument
175 #define REG_WR_RELAXED(bp, offset, val) \ argument
176 writel_relaxed((u32)val, REG_ADDR(bp, offset))
178 #define REG_WR16_RELAXED(bp, offset, val) \ argument
179 writew_relaxed((u16)val, REG_ADDR(bp, offset))
181 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) argument
182 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) argument
183 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) argument
185 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) argument
186 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) argument
188 #define REG_RD_DMAE(bp, offset, valp, len32) \ argument
190 bnx2x_read_dmae(bp, offset, len32);\
191 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
194 #define REG_WR_DMAE(bp, offset, valp, len32) \ argument
196 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
197 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
201 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ argument
202 REG_WR_DMAE(bp, offset, valp, len32)
204 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ argument
206 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
207 bnx2x_write_big_buf_wb(bp, addr, len32); \
210 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ argument
212 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) argument
213 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) argument
215 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ argument
217 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) argument
218 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) argument
219 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ argument
221 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ argument
224 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) argument
225 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\ argument
226 MF_CFG_ADDR(bp, field), (val))
227 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) argument
229 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ argument
230 (SHMEM2_RD((bp), size) > \
233 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) argument
234 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) argument
238 /* General SP events - stats query, cfc delete, etc */
256 (&bp->def_status_blk->sp_sb.\
260 (&bp->def_status_blk->sp_sb.\
287 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ argument
288 (bp)->max_cos)
292 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ argument
295 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ argument
297 /* add offset to rounded-up cid to get a value which could be used with UIO */
298 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) argument
299 /* but wait - avoid UIO special case for cid 0 */
300 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ argument
301 (UIO_DPM_ALIGN(bp) == UIO_DPM))
303 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ argument
304 (UIO_DPM_CID0_OFFSET(bp)))
305 /* how many cids were wasted - need this value for cid allocation */
306 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ argument
307 BNX2X_1st_NON_L2_ETH_CID(bp))
309 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) argument
311 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) argument
313 #define CNIC_SUPPORT(bp) ((bp)->cnic_support) argument
314 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled) argument
315 #define CNIC_LOADED(bp) ((bp)->cnic_loaded) argument
316 #define FCOE_INIT(bp) ((bp)->fcoe_init) argument
328 /* rules for calculating the cids of tx-only connections */
329 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) argument
330 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ argument
331 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
334 #define FP_COS_TO_TXQ(fp, cos, bp) \ argument
335 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
348 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) argument
349 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) argument
383 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) argument
384 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ argument
387 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) argument
394 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
395 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
401 #define SGE_PAGE_MASK (~(SGE_PAGE_SIZE - 1))
402 #define SGE_PAGE_ALIGN(addr) (((addr) + SGE_PAGE_SIZE - 1) & SGE_PAGE_MASK)
411 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
413 #define RX_SGE_MASK (RX_SGE_CNT - 1)
415 #define MAX_RX_SGE (NUM_RX_SGE - 1)
417 (MAX_RX_SGE_CNT - 1)) ? \
431 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
432 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
433 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
435 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \ argument
437 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
444 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
469 idx - index of the most significant bit in the created mask */
471 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
478 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
490 * First aggregation buffer is a data buffer, the following - are pages.
551 struct bnx2x *bp; /* parent */ member
613 4 ('-Xx-' string) +
615 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
621 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) argument
622 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) argument
623 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) argument
624 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) argument
626 /* Use 2500 as a mini-jumbo MTU for FCoE */
631 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ argument
633 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) argument
634 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) argument
635 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) argument
636 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) argument
637 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ argument
639 ->var)
641 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
642 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
643 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
652 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
654 #define MAX_TX_BD (NUM_TX_BD - 1)
655 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
657 (MAX_TX_DESC_CNT - 1)) ? \
665 (((bds) + MAX_TX_DESC_CNT - 1) / \
668 * START_BD - describes packed
669 * START_BD(splitted) - includes unpaged data segment for GSO
670 * PARSING_BD - for TSO and CSUM data
671 * PARSING_BD2 - for encapsulation data
672 * Frag BDs - describes pages for frags
684 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
685 #define RX_DESC_MASK (RX_DESC_CNT - 1)
687 #define MAX_RX_BD (NUM_RX_BD - 1)
688 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
696 #define NUM_BD_REQ BRB_SIZE(bp)
697 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
699 #define BD_TH_LO(bp) (NUM_BD_REQ + \ argument
701 FW_DROP_LEVEL(bp))
702 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
704 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
706 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
715 (MAX_RX_DESC_CNT - 1)) ? \
728 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
730 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
731 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
733 (MAX_RCQ_DESC_CNT - 1)) ? \
744 #define NUM_RCQ_REQ BRB_SIZE(bp)
745 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
747 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ argument
749 FW_DROP_LEVEL(bp))
750 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) argument
753 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
754 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
757 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
764 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
765 le32_to_cpu((bd)->addr_lo))
766 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
773 #define DOORBELL_RELAXED(bp, cid, val) \ argument
774 writel_relaxed((u32)(val), (bp)->doorbells + ((bp)->db_size * (cid)))
777 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
778 skb->csum_offset)
780 skb->csum_offset))
816 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
836 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
841 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
850 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
851 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) argument
853 #define CHIP_NUM(bp) (bp->common.chip_id >> 16) argument
877 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) argument
878 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) argument
879 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) argument
880 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) argument
881 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) argument
882 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) argument
883 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) argument
884 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) argument
885 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) argument
886 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) argument
887 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) argument
888 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) argument
889 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) argument
890 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) argument
891 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) argument
892 #define CHIP_IS_57840(bp) \ argument
893 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
894 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
895 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
896 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ argument
897 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
898 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) argument
899 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ argument
900 CHIP_IS_57711E(bp))
901 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ argument
902 CHIP_IS_57811_MF(bp) || \
903 CHIP_IS_57811_VF(bp))
904 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ argument
905 CHIP_IS_57712_MF(bp) || \
906 CHIP_IS_57712_VF(bp))
907 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ argument
908 CHIP_IS_57800_MF(bp) || \
909 CHIP_IS_57800_VF(bp) || \
910 CHIP_IS_57810(bp) || \
911 CHIP_IS_57810_MF(bp) || \
912 CHIP_IS_57810_VF(bp) || \
913 CHIP_IS_57811xx(bp) || \
914 CHIP_IS_57840(bp) || \
915 CHIP_IS_57840_MF(bp) || \
916 CHIP_IS_57840_VF(bp))
917 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) argument
918 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) argument
919 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
923 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) argument
927 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) argument
929 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ argument
930 !(CHIP_REV_VAL(bp) & 0x00001000))
932 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ argument
933 (CHIP_REV_VAL(bp) & 0x00001000))
935 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ argument
936 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
938 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) argument
939 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) argument
940 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ argument
943 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ argument
944 CHIP_REV_SIM(bp) :\
945 CHIP_REV_VAL(bp))
946 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ argument
947 (CHIP_REV(bp) == CHIP_REV_Bx))
948 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ argument
949 (CHIP_REV(bp) == CHIP_REV_Ax))
952 * to nic-only mode or to offload mode. Offload mode is configured if either the
955 * 2. During cnic-related load, to know if offload mode is already configured in
957 * Since the transition from nic-mode to offload-mode in HW causes traffic
958 * corruption, nic-mode is configured only in ports on which storage services
961 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) argument
982 #define CHIP_INT_MODE_IS_NBC(bp) \ argument
983 (!CHIP_IS_E1x(bp) && \
984 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
985 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) argument
991 #define CHIP_MODE(bp) (bp->common.chip_port_mode) argument
992 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) argument
1055 * control by the number of fast-path status blocks supported by the
1056 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1059 * as the FCoE queue do not require a FP-SB and other components like
1060 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1062 * If the maximum number of FP-SB available is X then:
1063 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1064 * regular L2 queues is Y=X-1
1065 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1069 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1075 /* fast-path interrupt contexts E1x */
1077 /* fast-path interrupt contexts E2 */
1180 #define bnx2x_sp(bp, var) (&bp->slowpath->var) argument
1181 #define bnx2x_sp_mapping(bp, var) \ argument
1182 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1224 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1226 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1227 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1231 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1237 (&bp->def_status_blk->sp_sb.\
1358 u8 pfid; /* per-path PF number */
1360 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) argument
1361 #define BP_PORT(bp) (bp->pfid & 1) argument
1362 #define BP_FUNC(bp) (bp->pfid) argument
1363 #define BP_ABS_FUNC(bp) (bp->pf_num) argument
1364 #define BP_VN(bp) ((bp)->pfid >> 1) argument
1365 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) argument
1366 #define BP_L_ID(bp) (BP_VN(bp) << 2) argument
1367 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ argument
1368 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1369 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) argument
1395 #define IRO (bp->iro_arr)
1405 #define ETH_MIN_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
1419 * at the end of skb->data, to avoid wasting a full cache line.
1420 * This reduces memory use (skb->truesize).
1428 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1492 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) argument
1495 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) argument
1496 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) argument
1498 #define IS_VF(bp) false argument
1499 #define IS_PF(bp) true argument
1502 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) argument
1503 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) argument
1504 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) argument
1552 #define IS_MF(bp) (bp->mf_mode != 0) argument
1553 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) argument
1554 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) argument
1555 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) argument
1557 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \ argument
1558 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1559 #define IS_MF_BD(bp) (IS_MF_SD(bp) && \ argument
1560 bp->mf_sub_mode == SUB_MF_MODE_BD)
1652 #define BP_ILT(bp) ((bp)->ilt) argument
1658 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) argument
1665 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ argument
1666 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1667 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ argument
1668 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1669 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ argument
1727 #define GUNZIP_BUF(bp) (bp->gunzip_buf) argument
1728 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping) argument
1729 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) argument
1734 /* Data blob - has 32 bit granularity */
1737 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) argument
1738 /* Zipped PRAM blobs - raw data */
1747 #define INIT_OPS(bp) (bp->init_ops) argument
1748 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) argument
1749 #define INIT_DATA(bp) (bp->init_data) argument
1750 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) argument
1751 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) argument
1752 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) argument
1753 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) argument
1754 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) argument
1755 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) argument
1756 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) argument
1757 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) argument
1764 #define IS_SRIOV(bp) ((bp)->vfdb) argument
1776 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1866 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues) argument
1867 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) argument
1868 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ argument
1869 (bp)->num_cnic_queues)
1870 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) argument
1872 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) argument
1874 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) argument
1875 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1899 #define for_each_cnic_queue(bp, var) \ argument
1900 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1902 if (skip_queue(bp, var)) \
1906 #define for_each_eth_queue(bp, var) \ argument
1907 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1909 #define for_each_nondefault_eth_queue(bp, var) \ argument
1910 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1912 #define for_each_queue(bp, var) \ argument
1913 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1914 if (skip_queue(bp, var)) \
1919 #define for_each_valid_rx_queue(bp, var) \ argument
1921 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1922 BNX2X_NUM_ETH_QUEUES(bp)); \
1924 if (skip_rx_queue(bp, var)) \
1928 #define for_each_rx_queue_cnic(bp, var) \ argument
1929 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1931 if (skip_rx_queue(bp, var)) \
1935 #define for_each_rx_queue(bp, var) \ argument
1936 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1937 if (skip_rx_queue(bp, var)) \
1942 #define for_each_valid_tx_queue(bp, var) \ argument
1944 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1945 BNX2X_NUM_ETH_QUEUES(bp)); \
1947 if (skip_tx_queue(bp, var)) \
1951 #define for_each_tx_queue_cnic(bp, var) \ argument
1952 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1954 if (skip_tx_queue(bp, var)) \
1958 #define for_each_tx_queue(bp, var) \ argument
1959 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1960 if (skip_tx_queue(bp, var)) \
1964 #define for_each_nondefault_queue(bp, var) \ argument
1965 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1966 if (skip_queue(bp, var)) \
1971 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1974 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1976 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
1979 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1981 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
1983 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) argument
1986 int bnx2x_idle_chk(struct bnx2x *bp);
1989 * bnx2x_set_mac_one - configure a single MAC address
1991 * @bp: driver handle
1994 * @set: if 'true' add a new MAC, otherwise - delete
2003 * operation has been successfully scheduled and a negative - if a requested
2006 int bnx2x_set_mac_one(struct bnx2x *bp, const u8 *mac,
2010 int bnx2x_set_vlan_one(struct bnx2x *bp, u16 vlan,
2015 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2017 * @bp: driver handle
2025 * operation has been successfully scheduled and a negative - if a requested
2028 int bnx2x_del_all_macs(struct bnx2x *bp,
2033 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2034 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2036 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2037 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2038 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2039 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2040 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2042 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2045 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2046 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2048 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2051 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2054 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2056 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2060 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2061 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2062 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2064 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2067 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2068 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2070 void bnx2x_update_coalesce(struct bnx2x *bp);
2071 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2073 bool bnx2x_port_after_undi(struct bnx2x *bp);
2075 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, in reg_poll() argument
2081 val = REG_RD(bp, reg); in reg_poll()
2084 ms -= wait; in reg_poll()
2092 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2096 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2101 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2136 #define DMAE_TIMEOUT -1
2137 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2138 #define DMAE_NOT_RDY -3
2151 /* E2 and onward - PCI error handling in the completion */
2195 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) argument
2197 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2202 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ argument
2203 BP_VN(bp))
2204 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ argument
2209 * Driver: 0-3 and 8-11 (for PF dmae operations)
2222 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ argument
2223 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2237 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ argument
2238 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2242 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2248 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2250 /* resolution of the rate shaping timer - 400 usec */
2252 /* number of bytes in single QM arbitration cycle -
2259 /* Fairness algorithm integration time coefficient -
2280 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \ argument
2281 IS_MF_FCOE_AFEX(bp))
2286 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2398 (&bp->def_status_blk->sp_sb.\
2408 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ argument
2409 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2428 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2434 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2436 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2438 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2439 void bnx2x_notify_link_changed(struct bnx2x *bp);
2441 #define BNX2X_MF_SD_PROTOCOL(bp) \ argument
2442 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2444 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ argument
2445 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2447 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ argument
2448 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2450 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) argument
2451 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) argument
2452 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp)) argument
2454 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp)) argument
2461 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \ argument
2464 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \ argument
2465 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2467 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \ argument
2468 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2470 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \ argument
2471 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2473 #define IS_MF_FCOE_AFEX(bp) \ argument
2474 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2476 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \ argument
2477 (IS_MF_SD(bp) && \
2478 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2479 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2481 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \ argument
2482 (IS_MF_SI(bp) && \
2483 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2484 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2486 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \ argument
2487 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2488 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2493 #define IS_MF_PERCENT_BW(bp) (IS_MF_SI(bp) || IS_MF_UFP(bp) || IS_MF_BD(bp)) argument
2514 void bnx2x_set_local_cmng(struct bnx2x *bp);
2516 void bnx2x_update_mng_version(struct bnx2x *bp);
2518 void bnx2x_update_mfw_dump(struct bnx2x *bp);
2520 #define MCPR_SCRATCH_BASE(bp) \ argument
2521 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2525 void bnx2x_init_ptp(struct bnx2x *bp);
2526 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2527 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2528 void bnx2x_register_phc(struct bnx2x *bp);
2533 /* Re-configure all previously configured vlan filters.
2534 * Meant for implicit re-load flows.
2536 int bnx2x_vlan_reconfigure_vid(struct bnx2x *bp);