Lines Matching refs:bnx2_write_phy
543 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) in bnx2_write_phy() function
1112 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS); in bnx2_5709s_linkup()
1114 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_5709s_linkup()
1386 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_bmsr1()
1395 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_bmsr1()
1412 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_enable_2g5()
1417 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_enable_2g5()
1422 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_enable_2g5()
1438 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_test_and_disable_2g5()
1443 bnx2_write_phy(bp, bp->mii_up1, up1); in bnx2_test_and_disable_2g5()
1448 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_test_and_disable_2g5()
1466 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1472 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_enable_forced_2g5()
1475 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_enable_forced_2g5()
1495 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_enable_forced_2g5()
1510 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1514 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val); in bnx2_disable_forced_2g5()
1517 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, in bnx2_disable_forced_2g5()
1534 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_disable_forced_2g5()
1542 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL); in bnx2_5706s_force_link_dn()
1545 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f); in bnx2_5706s_force_link_dn()
1547 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0); in bnx2_5706s_force_link_dn()
1581 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_set_link()
1618 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_set_link()
1640 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET); in bnx2_reset_phy()
1808 bnx2_write_phy(bp, bp->mii_adv, adv & in bnx2_setup_serdes_phy()
1811 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | in bnx2_setup_serdes_phy()
1816 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1819 bnx2_write_phy(bp, bp->mii_adv, adv); in bnx2_setup_serdes_phy()
1820 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_serdes_phy()
1842 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_serdes_phy()
1848 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_serdes_phy()
1849 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | in bnx2_setup_serdes_phy()
2101 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2102 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000); in bnx2_setup_copper_phy()
2103 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART | in bnx2_setup_copper_phy()
2118 bnx2_write_phy(bp, bp->mii_adv, new_adv); in bnx2_setup_copper_phy()
2135 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_setup_copper_phy()
2144 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr); in bnx2_setup_copper_phy()
2191 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER); in bnx2_init_5709s_phy()
2192 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD); in bnx2_init_5709s_phy()
2194 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2198 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG); in bnx2_init_5709s_phy()
2203 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val); in bnx2_init_5709s_phy()
2205 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); in bnx2_init_5709s_phy()
2211 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val); in bnx2_init_5709s_phy()
2213 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG); in bnx2_init_5709s_phy()
2216 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val); in bnx2_init_5709s_phy()
2218 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0); in bnx2_init_5709s_phy()
2222 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val); in bnx2_init_5709s_phy()
2224 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0); in bnx2_init_5709s_phy()
2239 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); in bnx2_init_5708s_phy()
2240 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); in bnx2_init_5708s_phy()
2241 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2245 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val); in bnx2_init_5708s_phy()
2249 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); in bnx2_init_5708s_phy()
2254 bnx2_write_phy(bp, BCM5708S_UP1, val); in bnx2_init_5708s_phy()
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2265 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val); in bnx2_init_5708s_phy()
2266 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); in bnx2_init_5708s_phy()
2277 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2279 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val); in bnx2_init_5708s_phy()
2280 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, in bnx2_init_5708s_phy()
2302 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2304 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000); in bnx2_init_5706s_phy()
2306 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2308 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02); in bnx2_init_5706s_phy()
2313 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_5706s_phy()
2315 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_5706s_phy()
2317 bnx2_write_phy(bp, 0x1c, 0x6c00); in bnx2_init_5706s_phy()
2319 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00); in bnx2_init_5706s_phy()
2334 bnx2_write_phy(bp, 0x18, 0x0c00); in bnx2_init_copper_phy()
2335 bnx2_write_phy(bp, 0x17, 0x000a); in bnx2_init_copper_phy()
2336 bnx2_write_phy(bp, 0x15, 0x310b); in bnx2_init_copper_phy()
2337 bnx2_write_phy(bp, 0x17, 0x201f); in bnx2_init_copper_phy()
2338 bnx2_write_phy(bp, 0x15, 0x9506); in bnx2_init_copper_phy()
2339 bnx2_write_phy(bp, 0x17, 0x401f); in bnx2_init_copper_phy()
2340 bnx2_write_phy(bp, 0x15, 0x14e2); in bnx2_init_copper_phy()
2341 bnx2_write_phy(bp, 0x18, 0x0400); in bnx2_init_copper_phy()
2345 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, in bnx2_init_copper_phy()
2349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val); in bnx2_init_copper_phy()
2354 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2356 bnx2_write_phy(bp, 0x18, val | 0x4000); in bnx2_init_copper_phy()
2359 bnx2_write_phy(bp, 0x10, val | 0x1); in bnx2_init_copper_phy()
2362 bnx2_write_phy(bp, 0x18, 0x7); in bnx2_init_copper_phy()
2364 bnx2_write_phy(bp, 0x18, val & ~0x4007); in bnx2_init_copper_phy()
2367 bnx2_write_phy(bp, 0x10, val & ~0x1); in bnx2_init_copper_phy()
2371 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, AUX_CTL_MISC_CTL); in bnx2_init_copper_phy()
2379 bnx2_write_phy(bp, MII_BNX2_AUX_CTL, val); in bnx2_init_copper_phy()
2452 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX | in bnx2_set_phy_loopback()
6044 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL); in bnx2_5706_serdes_has_link()
6050 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_has_link()
6057 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1); in bnx2_5706_serdes_has_link()
6087 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6096 bnx2_write_phy(bp, 0x17, 0x0f01); in bnx2_5706_serdes_timer()
6103 bnx2_write_phy(bp, bp->mii_bmcr, bmcr); in bnx2_5706_serdes_timer()
6113 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG); in bnx2_5706_serdes_timer()
7161 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); in bnx2_nway_reset()
7175 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE); in bnx2_nway_reset()
7879 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in); in bnx2_ioctl()