164 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)  in br32()  function
181 		u32 val = br32(bp, reg);  in b44_wait_bit()
228 	br32(bp, B44_IMASK);  in b44_disable_ints()
247 	*val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;  in __b44_readphy()
344 	val = br32(bp, B44_RXCONFIG);  in __b44_set_flow_ctrl()
351 	val = br32(bp, B44_MAC_FLOW);  in __b44_set_flow_ctrl()
488 		*val++ += br32(bp, reg);  in b44_stats_update()
492 		*val++ += br32(bp, reg);  in b44_stats_update()
520 			u32 val = br32(bp, B44_TX_CTRL);  in b44_check_phy()
546 			u32 val = br32(bp, B44_TX_CTRL);  in b44_check_phy()
596 	cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;  in b44_tx()
759 	prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;  in b44_rx()
895 	istat = br32(bp, B44_ISTAT);  in b44_interrupt()
896 	imask = br32(bp, B44_IMASK);  in b44_interrupt()
922 		br32(bp, B44_ISTAT);  in b44_interrupt()
1020 		br32(bp, B44_DMATX_PTR);  in b44_start_xmit()
1249 		br32(bp, reg);  in b44_clear_stats()
1251 		br32(bp, reg);  in b44_clear_stats()
1271 		if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {  in b44_chip_reset()
1305 	br32(bp, B44_MDIO_CTRL);  in b44_chip_reset()
1307 	if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {  in b44_chip_reset()
1309 		br32(bp, B44_ENET_CTRL);  in b44_chip_reset()
1312 		u32 val = br32(bp, B44_DEVCTRL);  in b44_chip_reset()
1316 			br32(bp, B44_DEVCTRL);  in b44_chip_reset()
1348 		val = br32(bp, B44_CAM_CTRL);  in __b44_set_mac_addr()
1369 	val = br32(bp, B44_RXCONFIG);  in b44_set_mac_addr()
1420 	val = br32(bp, B44_ENET_CTRL);  in b44_init_hw()
1571 	val = br32(bp, B44_DEVCTRL);  in b44_setup_pseudo_magicp()
1582 		bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);  in b44_setup_wol_pci()
1611 		val = br32(bp, B44_DEVCTRL);  in b44_setup_wol()
1719 	val = br32(bp, B44_RXCONFIG);  in __b44_set_rx_mode()
1740 		val = br32(bp, B44_CAM_CTRL);  in __b44_set_rx_mode()
2218 		u32 val = br32(bp, B44_TX_CTRL);  in b44_adjust_link()