Lines Matching full:duplex
228 /* MAC Half-Duplex Control Register */
303 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
327 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
328 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
329 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
330 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
331 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
332 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
337 #define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
338 #define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
339 #define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
340 #define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
350 #define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
351 #define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
352 #define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
353 #define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
437 #define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
438 #define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */