39 #define N_TX_BUFF_ORDER	0
46 #define MACE_BUFF_SIZE	0x800
49 #define BROKEN_ADDRCHG_REV	0x0941
53 #define MACE_BASE	(void *)(0x50F1C000)
54 #define MACE_PROM	(void *)(0x50F08001)
105 	psc_write_word(PSC_ENETRD_CMD + set, 0x0100);  in mace_load_rxdma_base()
108 	psc_write_word(PSC_ENETRD_CMD + set, 0x9800);  in mace_load_rxdma_base()
109 	mp->rx_tail = 0;  in mace_load_rxdma_base()
124 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
125 	mace_load_rxdma_base(dev, 0x00);  in mace_rxdma_reset()
126 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
128 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
129 	mace_load_rxdma_base(dev, 0x10);  in mace_rxdma_reset()
130 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
133 	mp->rx_slot = 0;  in mace_rxdma_reset()
135 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);  in mace_rxdma_reset()
136 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);  in mace_rxdma_reset()
149 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_txdma_reset()
154 	mp->tx_slot = mp->tx_sloti = 0;  in mace_txdma_reset()
157 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_txdma_reset()
167 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_dma_off()
168 	psc_write_word(PSC_ENETRD_CTL, 0x1000);  in mace_dma_off()
169 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
170 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
172 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_dma_off()
173 	psc_write_word(PSC_ENETWR_CTL, 0x1000);  in mace_dma_off()
174 	psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
175 	psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
199 	unsigned char checksum = 0;  in mace_probe()
222 	 * The PROM contains 8 bytes which total 0xFF when XOR'd  in mace_probe()
230 	for (j = 0; j < 6; ++j) {  in mace_probe()
240 	if (checksum != 0xFF) {  in mace_probe()
248 	pr_info("Onboard MACE, hardware address %pM, chip revision 0x%04X\n",  in mace_probe()
253 		return 0;  in mace_probe()
284 	mb->maccc = 0;	/* turn off tx, rx */  in mace_reset()
285 	mb->imr = 0xFF;	/* disable all intrs for now */  in mace_reset()
293 	mb->rcvfc = 0;  in mace_reset()
303 		while ((mb->iac & ADDRCHG) != 0)  in mace_reset()
306 	for (i = 0; i < 8; ++i)  in mace_reset()
307 		mb->ladrf = 0;  in mace_reset()
311 		mb->iac = 0;  in mace_reset()
333 		while ((mb->iac & ADDRCHG) != 0)  in __mace_set_address()
336 	for (i = 0; i < 6; ++i)  in __mace_set_address()
340 		mb->iac = 0;  in __mace_set_address()
360 	return 0;  in mace_set_address()
376 	if (request_irq(dev->irq, mace_interrupt, 0, dev->name, dev)) {  in mace_open()
380 	if (request_irq(mp->dma_intr, mace_dma_intr, 0, dev->name, dev)) {  in mace_open()
404 	psc_write_word(PSC_ENETWR_CTL, 0x9000);  in mace_open()
405 	psc_write_word(PSC_ENETRD_CTL, 0x9000);  in mace_open()
406 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_open()
407 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_open()
416 	return 0;  in mace_open()
436 	mb->maccc = 0;		/* disable rx and tx	 */  in mace_close()
437 	mb->imr = 0xFF;		/* disable all irqs	 */  in mace_close()
440 	return 0;  in mace_close()
474 	psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);  in mace_xmit_start()
476 	mp->tx_slot ^= 0x10;  in mace_xmit_start()
503 			for (i = 0; i < 8; i++) {  in mace_set_multicast()
504 				multicast_filter[i] = 0xFF;  in mace_set_multicast()
507 			for (i = 0; i < 8; i++)  in mace_set_multicast()
508 				multicast_filter[i] = 0;  in mace_set_multicast()
521 			while ((mb->iac & ADDRCHG) != 0)  in mace_set_multicast()
524 		for (i = 0; i < 8; ++i)  in mace_set_multicast()
527 			mb->iac = 0;  in mace_set_multicast()
572 		if ((fs & XMTSV) == 0) {  in mace_interrupt()
616 	mb->maccc = 0;  in mace_tx_timeout()
655 		unsigned int frame_length = mf->rcvcnt + ((frame_status & 0x0F) << 8 );  in mace_dma_rx_frame()
687 	if (!(baka & 0x60000000)) return IRQ_NONE;  in mace_dma_intr()
695 	if (status & 0x2000) {  in mace_dma_intr()
697 	} else if (status & 0x0100) {  in mace_dma_intr()
698 		psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);  in mace_dma_intr()
716 			mp->rx_slot ^= 0x10;  in mace_dma_intr()
718 			psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);  in mace_dma_intr()
728 	if (status & 0x2000) {  in mace_dma_intr()
730 	} else if (status & 0x0100) {  in mace_dma_intr()
731 		psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);  in mace_dma_intr()
732 		mp->tx_sloti ^= 0x10;  in mace_dma_intr()
759 	return 0;  in mac_mace_device_remove()