209 void bmwrite(struct net_device *dev, unsigned long reg_offset, unsigned data )  in bmwrite()  function
244 		bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
248 		bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
251 	bmwrite(dev, MIFCSR, 0);  in bmac_mif_readbits()
253 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_readbits()
265 		bmwrite(dev, MIFCSR, b);  in bmac_mif_writebits()
267 		bmwrite(dev, MIFCSR, b|1);  in bmac_mif_writebits()
277 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
282 	bmwrite(dev, MIFCSR, 2);  in bmac_mif_read()
284 	bmwrite(dev, MIFCSR, 1);  in bmac_mif_read()
287 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_read()
295 	bmwrite(dev, MIFCSR, 4);  in bmac_mif_write()
315 	bmwrite(dev, RXRST, RxResetValue);  in bmac_init_registers()
316 	bmwrite(dev, TXRST, TxResetBit);  in bmac_init_registers()
328 		bmwrite(dev, XCVRIF, regValue);  in bmac_init_registers()
332 	bmwrite(dev, RSEED, (unsigned short)0x1968);  in bmac_init_registers()
336 	bmwrite(dev, XIFC, regValue);  in bmac_init_registers()
341 	bmwrite(dev, NCCNT, 0);  in bmac_init_registers()
342 	bmwrite(dev, NTCNT, 0);  in bmac_init_registers()
343 	bmwrite(dev, EXCNT, 0);  in bmac_init_registers()
344 	bmwrite(dev, LTCNT, 0);  in bmac_init_registers()
347 	bmwrite(dev, FRCNT, 0);  in bmac_init_registers()
348 	bmwrite(dev, LECNT, 0);  in bmac_init_registers()
349 	bmwrite(dev, AECNT, 0);  in bmac_init_registers()
350 	bmwrite(dev, FECNT, 0);  in bmac_init_registers()
351 	bmwrite(dev, RXCV, 0);  in bmac_init_registers()
354 	bmwrite(dev, TXTH, 4);	/* 4 octets before tx starts */  in bmac_init_registers()
356 	bmwrite(dev, TXFIFOCSR, 0);	/* first disable txFIFO */  in bmac_init_registers()
357 	bmwrite(dev, TXFIFOCSR, TxFIFOEnable );  in bmac_init_registers()
360 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_init_registers()
361 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_init_registers()
368 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); 	/* bits 15 - 0 */  in bmac_init_registers()
369 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); 	/* bits 31 - 16 */  in bmac_init_registers()
370 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); 	/* bits 47 - 32 */  in bmac_init_registers()
371 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); 	/* bits 63 - 48 */  in bmac_init_registers()
374 	bmwrite(dev, MADD0, *pWord16++);  in bmac_init_registers()
375 	bmwrite(dev, MADD1, *pWord16++);  in bmac_init_registers()
376 	bmwrite(dev, MADD2, *pWord16);  in bmac_init_registers()
378 	bmwrite(dev, RXCFG, RxCRCNoStrip | RxHashFilterEnable | RxRejectOwnPackets);  in bmac_init_registers()
380 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_init_registers()
387 	bmwrite(dev, INTDISABLE, DisableAll);
393 	bmwrite(dev, INTDISABLE, EnableNormal);
409 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_start_chip()
413 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_start_chip()
477 		bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_suspend()
479 		bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_suspend()
480 		bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_suspend()
533 	bmwrite(dev, MADD0, *pWord16++);  in bmac_set_address()
534 	bmwrite(dev, MADD1, *pWord16++);  in bmac_set_address()
535 	bmwrite(dev, MADD2, *pWord16);  in bmac_set_address()
900 	bmwrite(dev, RXCFG, rx_cfg);  in bmac_rx_off()
917 	bmwrite(dev, RXRST, RxResetValue);  in bmac_rx_on()
918 	bmwrite(dev, RXFIFOCSR, 0);	/* first disable rxFIFO */  in bmac_rx_on()
919 	bmwrite(dev, RXFIFOCSR, RxFIFOEnable );  in bmac_rx_on()
920 	bmwrite(dev, RXCFG, rx_cfg );  in bmac_rx_on()
927 	bmwrite(dev, BHASH3, bp->hash_table_mask[0]); /* bits 15 - 0 */  in bmac_update_hash_table_mask()
928 	bmwrite(dev, BHASH2, bp->hash_table_mask[1]); /* bits 31 - 16 */  in bmac_update_hash_table_mask()
929 	bmwrite(dev, BHASH1, bp->hash_table_mask[2]); /* bits 47 - 32 */  in bmac_update_hash_table_mask()
930 	bmwrite(dev, BHASH0, bp->hash_table_mask[3]); /* bits 63 - 48 */  in bmac_update_hash_table_mask()
984 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1014 		bmwrite(dev, BHASH0, 0xffff);  in bmac_set_multicast()
1015 		bmwrite(dev, BHASH1, 0xffff);  in bmac_set_multicast()
1016 		bmwrite(dev, BHASH2, 0xffff);  in bmac_set_multicast()
1017 		bmwrite(dev, BHASH3, 0xffff);  in bmac_set_multicast()
1021 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1027 		bmwrite(dev, RXCFG, rx_cfg);  in bmac_set_multicast()
1034 		bmwrite(dev, BHASH0, hash_table[0]);  in bmac_set_multicast()
1035 		bmwrite(dev, BHASH1, hash_table[1]);  in bmac_set_multicast()
1036 		bmwrite(dev, BHASH2, hash_table[2]);  in bmac_set_multicast()
1037 		bmwrite(dev, BHASH3, hash_table[3]);  in bmac_set_multicast()
1089 	bmwrite(dev, SROMCSR, ChipSelect | Clk);  in bmac_clock_out_bit()
1096 	bmwrite(dev, SROMCSR, ChipSelect);  in bmac_clock_out_bit()
1110 	bmwrite(dev, SROMCSR, data | ChipSelect  );  in bmac_clock_in_bit()
1113 	bmwrite(dev, SROMCSR, data | ChipSelect | Clk );  in bmac_clock_in_bit()
1116 	bmwrite(dev, SROMCSR, data | ChipSelect);  in bmac_clock_in_bit()
1124 	bmwrite(dev, SROMCSR, 0);  in reset_and_select_srom()
1152 	bmwrite(dev, SROMCSR, 0);  in read_srom()
1203 	bmwrite(dev, INTDISABLE, EnableNormal);  in bmac_reset_and_enable()
1283 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1293 	bmwrite(dev, INTDISABLE, DisableAll);  in bmac_probe()
1398 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_close()
1401 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_close()
1403 	bmwrite(dev, INTDISABLE, DisableAll); /* disable all intrs */  in bmac_close()
1493 	bmwrite(dev, RXCFG, (config & ~RxMACEnable));  in bmac_tx_timeout()
1495 	bmwrite(dev, TXCFG, (config & ~TxMACEnable));  in bmac_tx_timeout()
1532 	bmwrite(dev, RXCFG, oldConfig | RxMACEnable );  in bmac_tx_timeout()
1534 	bmwrite(dev, TXCFG, oldConfig | TxMACEnable );  in bmac_tx_timeout()