Lines Matching refs:pdata
127 static inline unsigned int xgbe_get_max_frame(struct xgbe_prv_data *pdata) in xgbe_get_max_frame() argument
129 return pdata->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; in xgbe_get_max_frame()
132 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata, in xgbe_usec_to_riwt() argument
140 rate = pdata->sysclk_rate; in xgbe_usec_to_riwt()
155 static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata, in xgbe_riwt_to_usec() argument
163 rate = pdata->sysclk_rate; in xgbe_riwt_to_usec()
178 static int xgbe_config_pbl_val(struct xgbe_prv_data *pdata) in xgbe_config_pbl_val() argument
184 pbl = pdata->pbl; in xgbe_config_pbl_val()
186 if (pdata->pbl > 32) { in xgbe_config_pbl_val()
191 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_pbl_val()
192 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, PBLX8, in xgbe_config_pbl_val()
195 if (pdata->channel[i]->tx_ring) in xgbe_config_pbl_val()
196 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, in xgbe_config_pbl_val()
199 if (pdata->channel[i]->rx_ring) in xgbe_config_pbl_val()
200 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, in xgbe_config_pbl_val()
207 static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata) in xgbe_config_osp_mode() argument
211 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_osp_mode()
212 if (!pdata->channel[i]->tx_ring) in xgbe_config_osp_mode()
215 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, OSP, in xgbe_config_osp_mode()
216 pdata->tx_osp_mode); in xgbe_config_osp_mode()
222 static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_rsf_mode() argument
226 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rsf_mode()
227 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val); in xgbe_config_rsf_mode()
232 static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val) in xgbe_config_tsf_mode() argument
236 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tsf_mode()
237 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val); in xgbe_config_tsf_mode()
242 static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_rx_threshold() argument
247 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_threshold()
248 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val); in xgbe_config_rx_threshold()
253 static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata, in xgbe_config_tx_threshold() argument
258 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_threshold()
259 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val); in xgbe_config_tx_threshold()
264 static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_rx_coalesce() argument
268 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_coalesce()
269 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_coalesce()
272 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RIWT, RWT, in xgbe_config_rx_coalesce()
273 pdata->rx_riwt); in xgbe_config_rx_coalesce()
279 static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata) in xgbe_config_tx_coalesce() argument
284 static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_buffer_size() argument
288 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_rx_buffer_size()
289 if (!pdata->channel[i]->rx_ring) in xgbe_config_rx_buffer_size()
292 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, RBSZ, in xgbe_config_rx_buffer_size()
293 pdata->rx_buf_size); in xgbe_config_rx_buffer_size()
297 static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata) in xgbe_config_tso_mode() argument
301 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_tso_mode()
302 if (!pdata->channel[i]->tx_ring) in xgbe_config_tso_mode()
305 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, TSE, 1); in xgbe_config_tso_mode()
309 static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata) in xgbe_config_sph_mode() argument
313 for (i = 0; i < pdata->channel_count; i++) { in xgbe_config_sph_mode()
314 if (!pdata->channel[i]->rx_ring) in xgbe_config_sph_mode()
317 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_CR, SPH, 1); in xgbe_config_sph_mode()
320 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE); in xgbe_config_sph_mode()
323 static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type, in xgbe_write_rss_reg() argument
329 mutex_lock(&pdata->rss_mutex); in xgbe_write_rss_reg()
331 if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) { in xgbe_write_rss_reg()
336 XGMAC_IOWRITE(pdata, MAC_RSSDR, val); in xgbe_write_rss_reg()
338 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index); in xgbe_write_rss_reg()
339 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type); in xgbe_write_rss_reg()
340 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0); in xgbe_write_rss_reg()
341 XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1); in xgbe_write_rss_reg()
345 if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) in xgbe_write_rss_reg()
354 mutex_unlock(&pdata->rss_mutex); in xgbe_write_rss_reg()
359 static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata) in xgbe_write_rss_hash_key() argument
361 unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32); in xgbe_write_rss_hash_key()
362 unsigned int *key = (unsigned int *)&pdata->rss_key; in xgbe_write_rss_hash_key()
366 ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE, in xgbe_write_rss_hash_key()
375 static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata) in xgbe_write_rss_lookup_table() argument
380 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) { in xgbe_write_rss_lookup_table()
381 ret = xgbe_write_rss_reg(pdata, in xgbe_write_rss_lookup_table()
383 pdata->rss_table[i]); in xgbe_write_rss_lookup_table()
391 static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key) in xgbe_set_rss_hash_key() argument
393 memcpy(pdata->rss_key, key, sizeof(pdata->rss_key)); in xgbe_set_rss_hash_key()
395 return xgbe_write_rss_hash_key(pdata); in xgbe_set_rss_hash_key()
398 static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata, in xgbe_set_rss_lookup_table() argument
403 for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) in xgbe_set_rss_lookup_table()
404 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]); in xgbe_set_rss_lookup_table()
406 return xgbe_write_rss_lookup_table(pdata); in xgbe_set_rss_lookup_table()
409 static int xgbe_enable_rss(struct xgbe_prv_data *pdata) in xgbe_enable_rss() argument
413 if (!pdata->hw_feat.rss) in xgbe_enable_rss()
417 ret = xgbe_write_rss_hash_key(pdata); in xgbe_enable_rss()
422 ret = xgbe_write_rss_lookup_table(pdata); in xgbe_enable_rss()
427 XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options); in xgbe_enable_rss()
430 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1); in xgbe_enable_rss()
435 static int xgbe_disable_rss(struct xgbe_prv_data *pdata) in xgbe_disable_rss() argument
437 if (!pdata->hw_feat.rss) in xgbe_disable_rss()
440 XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0); in xgbe_disable_rss()
445 static void xgbe_config_rss(struct xgbe_prv_data *pdata) in xgbe_config_rss() argument
449 if (!pdata->hw_feat.rss) in xgbe_config_rss()
452 if (pdata->netdev->features & NETIF_F_RXHASH) in xgbe_config_rss()
453 ret = xgbe_enable_rss(pdata); in xgbe_config_rss()
455 ret = xgbe_disable_rss(pdata); in xgbe_config_rss()
458 netdev_err(pdata->netdev, in xgbe_config_rss()
462 static bool xgbe_is_pfc_queue(struct xgbe_prv_data *pdata, in xgbe_is_pfc_queue() argument
469 if (pdata->prio2q_map[prio] != queue) in xgbe_is_pfc_queue()
473 tc = pdata->ets->prio_tc[prio]; in xgbe_is_pfc_queue()
476 if (pdata->pfc->pfc_en & (1 << tc)) in xgbe_is_pfc_queue()
483 static void xgbe_set_vxlan_id(struct xgbe_prv_data *pdata) in xgbe_set_vxlan_id() argument
486 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, pdata->vxlan_port); in xgbe_set_vxlan_id()
488 netif_dbg(pdata, drv, pdata->netdev, "VXLAN tunnel id set to %hx\n", in xgbe_set_vxlan_id()
489 pdata->vxlan_port); in xgbe_set_vxlan_id()
492 static void xgbe_enable_vxlan(struct xgbe_prv_data *pdata) in xgbe_enable_vxlan() argument
494 if (!pdata->hw_feat.vxn) in xgbe_enable_vxlan()
498 xgbe_set_vxlan_id(pdata); in xgbe_enable_vxlan()
501 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 1); in xgbe_enable_vxlan()
504 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNM, 0); in xgbe_enable_vxlan()
505 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 1); in xgbe_enable_vxlan()
507 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration enabled\n"); in xgbe_enable_vxlan()
510 static void xgbe_disable_vxlan(struct xgbe_prv_data *pdata) in xgbe_disable_vxlan() argument
512 if (!pdata->hw_feat.vxn) in xgbe_disable_vxlan()
516 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, VNE, 0); in xgbe_disable_vxlan()
519 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VUCC, 0); in xgbe_disable_vxlan()
522 XGMAC_IOWRITE_BITS(pdata, MAC_TIR, TNID, 0); in xgbe_disable_vxlan()
524 netif_dbg(pdata, drv, pdata->netdev, "VXLAN acceleration disabled\n"); in xgbe_disable_vxlan()
527 static unsigned int xgbe_get_fc_queue_count(struct xgbe_prv_data *pdata) in xgbe_get_fc_queue_count() argument
532 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) >= 0x30) in xgbe_get_fc_queue_count()
535 return min_t(unsigned int, pdata->tx_q_count, max_q_count); in xgbe_get_fc_queue_count()
538 static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_tx_flow_control() argument
544 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_tx_flow_control()
545 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0); in xgbe_disable_tx_flow_control()
548 q_count = xgbe_get_fc_queue_count(pdata); in xgbe_disable_tx_flow_control()
551 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_disable_tx_flow_control()
553 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_disable_tx_flow_control()
561 static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_tx_flow_control() argument
563 struct ieee_pfc *pfc = pdata->pfc; in xgbe_enable_tx_flow_control()
564 struct ieee_ets *ets = pdata->ets; in xgbe_enable_tx_flow_control()
569 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_enable_tx_flow_control()
572 if (pdata->rx_rfd[i]) { in xgbe_enable_tx_flow_control()
575 if (xgbe_is_pfc_queue(pdata, i)) in xgbe_enable_tx_flow_control()
582 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, ehfc); in xgbe_enable_tx_flow_control()
584 netif_dbg(pdata, drv, pdata->netdev, in xgbe_enable_tx_flow_control()
590 q_count = xgbe_get_fc_queue_count(pdata); in xgbe_enable_tx_flow_control()
593 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_enable_tx_flow_control()
600 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_enable_tx_flow_control()
608 static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_disable_rx_flow_control() argument
610 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0); in xgbe_disable_rx_flow_control()
615 static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_enable_rx_flow_control() argument
617 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1); in xgbe_enable_rx_flow_control()
622 static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_tx_flow_control() argument
624 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_tx_flow_control()
626 if (pdata->tx_pause || (pfc && pfc->pfc_en)) in xgbe_config_tx_flow_control()
627 xgbe_enable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
629 xgbe_disable_tx_flow_control(pdata); in xgbe_config_tx_flow_control()
634 static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_rx_flow_control() argument
636 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_rx_flow_control()
638 if (pdata->rx_pause || (pfc && pfc->pfc_en)) in xgbe_config_rx_flow_control()
639 xgbe_enable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
641 xgbe_disable_rx_flow_control(pdata); in xgbe_config_rx_flow_control()
646 static void xgbe_config_flow_control(struct xgbe_prv_data *pdata) in xgbe_config_flow_control() argument
648 struct ieee_pfc *pfc = pdata->pfc; in xgbe_config_flow_control()
650 xgbe_config_tx_flow_control(pdata); in xgbe_config_flow_control()
651 xgbe_config_rx_flow_control(pdata); in xgbe_config_flow_control()
653 XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, in xgbe_config_flow_control()
657 static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_dma_interrupts() argument
663 if (pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
664 XGMAC_IOWRITE_BITS(pdata, DMA_MR, INTM, in xgbe_enable_dma_interrupts()
665 pdata->channel_irq_mode); in xgbe_enable_dma_interrupts()
667 ver = XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); in xgbe_enable_dma_interrupts()
669 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_dma_interrupts()
670 channel = pdata->channel[i]; in xgbe_enable_dma_interrupts()
699 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
711 if (!pdata->per_channel_irq || pdata->channel_irq_mode) in xgbe_enable_dma_interrupts()
720 static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mtl_interrupts() argument
725 q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt); in xgbe_enable_mtl_interrupts()
728 mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR); in xgbe_enable_mtl_interrupts()
729 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr); in xgbe_enable_mtl_interrupts()
732 XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0); in xgbe_enable_mtl_interrupts()
736 static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_mac_interrupts() argument
743 XGMAC_IOWRITE(pdata, MAC_IER, mac_ier); in xgbe_enable_mac_interrupts()
746 XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
747 XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff); in xgbe_enable_mac_interrupts()
750 XGMAC_IOWRITE_BITS(pdata, MAC_MDIOIER, SNGLCOMPIE, 1); in xgbe_enable_mac_interrupts()
753 static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata) in xgbe_enable_ecc_interrupts() argument
757 if (!pdata->vdata->ecc_support) in xgbe_enable_ecc_interrupts()
761 ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR); in xgbe_enable_ecc_interrupts()
762 XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr); in xgbe_enable_ecc_interrupts()
772 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_enable_ecc_interrupts()
775 static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata) in xgbe_disable_ecc_ded() argument
779 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_ded()
786 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_ded()
789 static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata, in xgbe_disable_ecc_sec() argument
794 ecc_ier = XP_IOREAD(pdata, XP_ECC_IER); in xgbe_disable_ecc_sec()
809 XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier); in xgbe_disable_ecc_sec()
812 static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_set_speed() argument
833 if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) != ss) in xgbe_set_speed()
834 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, ss); in xgbe_set_speed()
839 static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_stripping() argument
842 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1); in xgbe_enable_rx_vlan_stripping()
845 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1); in xgbe_enable_rx_vlan_stripping()
848 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0); in xgbe_enable_rx_vlan_stripping()
851 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0); in xgbe_enable_rx_vlan_stripping()
854 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3); in xgbe_enable_rx_vlan_stripping()
859 static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_stripping() argument
861 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0); in xgbe_disable_rx_vlan_stripping()
866 static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_enable_rx_vlan_filtering() argument
869 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1); in xgbe_enable_rx_vlan_filtering()
872 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1); in xgbe_enable_rx_vlan_filtering()
875 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0); in xgbe_enable_rx_vlan_filtering()
878 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1); in xgbe_enable_rx_vlan_filtering()
886 XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1); in xgbe_enable_rx_vlan_filtering()
891 static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata) in xgbe_disable_rx_vlan_filtering() argument
894 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0); in xgbe_disable_rx_vlan_filtering()
923 static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata) in xgbe_update_vlan_hash_table() argument
931 for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) { in xgbe_update_vlan_hash_table()
940 XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table); in xgbe_update_vlan_hash_table()
945 static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata, in xgbe_set_promiscuous_mode() argument
950 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val) in xgbe_set_promiscuous_mode()
953 netif_dbg(pdata, drv, pdata->netdev, "%s promiscuous mode\n", in xgbe_set_promiscuous_mode()
955 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val); in xgbe_set_promiscuous_mode()
959 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
961 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_set_promiscuous_mode()
962 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_set_promiscuous_mode()
968 static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata, in xgbe_set_all_multicast_mode() argument
973 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val) in xgbe_set_all_multicast_mode()
976 netif_dbg(pdata, drv, pdata->netdev, "%s allmulti mode\n", in xgbe_set_all_multicast_mode()
978 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val); in xgbe_set_all_multicast_mode()
983 static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata, in xgbe_set_mac_reg() argument
1002 netif_dbg(pdata, drv, pdata->netdev, in xgbe_set_mac_reg()
1009 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi); in xgbe_set_mac_reg()
1011 XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo); in xgbe_set_mac_reg()
1015 static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata) in xgbe_set_mac_addn_addrs() argument
1017 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_addn_addrs()
1023 addn_macs = pdata->hw_feat.addn_mac; in xgbe_set_mac_addn_addrs()
1026 xgbe_set_promiscuous_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
1029 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
1034 xgbe_set_all_multicast_mode(pdata, 1); in xgbe_set_mac_addn_addrs()
1037 xgbe_set_mac_reg(pdata, ha, &mac_reg); in xgbe_set_mac_addn_addrs()
1045 xgbe_set_mac_reg(pdata, NULL, &mac_reg); in xgbe_set_mac_addn_addrs()
1048 static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata) in xgbe_set_mac_hash_table() argument
1050 struct net_device *netdev = pdata->netdev; in xgbe_set_mac_hash_table()
1058 hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7); in xgbe_set_mac_hash_table()
1059 hash_table_count = pdata->hw_feat.hash_table_size / 32; in xgbe_set_mac_hash_table()
1078 XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]); in xgbe_set_mac_hash_table()
1083 static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata) in xgbe_add_mac_addresses() argument
1085 if (pdata->hw_feat.hash_table_size) in xgbe_add_mac_addresses()
1086 xgbe_set_mac_hash_table(pdata); in xgbe_add_mac_addresses()
1088 xgbe_set_mac_addn_addrs(pdata); in xgbe_add_mac_addresses()
1093 static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, const u8 *addr) in xgbe_set_mac_address() argument
1101 XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi); in xgbe_set_mac_address()
1102 XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo); in xgbe_set_mac_address()
1107 static int xgbe_config_rx_mode(struct xgbe_prv_data *pdata) in xgbe_config_rx_mode() argument
1109 struct net_device *netdev = pdata->netdev; in xgbe_config_rx_mode()
1115 xgbe_set_promiscuous_mode(pdata, pr_mode); in xgbe_config_rx_mode()
1116 xgbe_set_all_multicast_mode(pdata, am_mode); in xgbe_config_rx_mode()
1118 xgbe_add_mac_addresses(pdata); in xgbe_config_rx_mode()
1123 static int xgbe_clr_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_clr_gpio() argument
1130 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_clr_gpio()
1133 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_clr_gpio()
1138 static int xgbe_set_gpio(struct xgbe_prv_data *pdata, unsigned int gpio) in xgbe_set_gpio() argument
1145 reg = XGMAC_IOREAD(pdata, MAC_GPIOSR); in xgbe_set_gpio()
1148 XGMAC_IOWRITE(pdata, MAC_GPIOSR, reg); in xgbe_set_gpio()
1153 static int xgbe_read_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v2() argument
1163 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v2()
1175 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_read_mmd_regs_v2()
1176 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_read_mmd_regs_v2()
1178 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1179 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_read_mmd_regs_v2()
1180 mmd_data = XPCS16_IOREAD(pdata, offset); in xgbe_read_mmd_regs_v2()
1181 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v2()
1186 static void xgbe_write_mmd_regs_v2(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v2() argument
1195 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v2()
1207 index = mmd_address & ~pdata->xpcs_window_mask; in xgbe_write_mmd_regs_v2()
1208 offset = pdata->xpcs_window + (mmd_address & pdata->xpcs_window_mask); in xgbe_write_mmd_regs_v2()
1210 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1211 XPCS32_IOWRITE(pdata, pdata->xpcs_window_sel_reg, index); in xgbe_write_mmd_regs_v2()
1212 XPCS16_IOWRITE(pdata, offset, mmd_data); in xgbe_write_mmd_regs_v2()
1213 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v2()
1216 static int xgbe_read_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs_v1() argument
1226 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_read_mmd_regs_v1()
1237 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1238 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_read_mmd_regs_v1()
1239 mmd_data = XPCS32_IOREAD(pdata, (mmd_address & 0xff) << 2); in xgbe_read_mmd_regs_v1()
1240 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_read_mmd_regs_v1()
1245 static void xgbe_write_mmd_regs_v1(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs_v1() argument
1254 mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff); in xgbe_write_mmd_regs_v1()
1265 spin_lock_irqsave(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1266 XPCS32_IOWRITE(pdata, PCS_V1_WINDOW_SELECT, mmd_address >> 8); in xgbe_write_mmd_regs_v1()
1267 XPCS32_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data); in xgbe_write_mmd_regs_v1()
1268 spin_unlock_irqrestore(&pdata->xpcs_lock, flags); in xgbe_write_mmd_regs_v1()
1271 static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_read_mmd_regs() argument
1274 switch (pdata->vdata->xpcs_access) { in xgbe_read_mmd_regs()
1276 return xgbe_read_mmd_regs_v1(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1280 return xgbe_read_mmd_regs_v2(pdata, prtad, mmd_reg); in xgbe_read_mmd_regs()
1284 static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad, in xgbe_write_mmd_regs() argument
1287 switch (pdata->vdata->xpcs_access) { in xgbe_write_mmd_regs()
1289 return xgbe_write_mmd_regs_v1(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1293 return xgbe_write_mmd_regs_v2(pdata, prtad, mmd_reg, mmd_data); in xgbe_write_mmd_regs()
1320 static int xgbe_write_ext_mii_regs(struct xgbe_prv_data *pdata, in xgbe_write_ext_mii_regs() argument
1325 reinit_completion(&pdata->mdio_complete); in xgbe_write_ext_mii_regs()
1327 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_write_ext_mii_regs()
1333 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_write_ext_mii_regs()
1335 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_write_ext_mii_regs()
1336 netdev_err(pdata->netdev, "mdio write operation timed out\n"); in xgbe_write_ext_mii_regs()
1343 static int xgbe_write_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, in xgbe_write_ext_mii_regs_c22() argument
1350 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); in xgbe_write_ext_mii_regs_c22()
1353 static int xgbe_write_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, in xgbe_write_ext_mii_regs_c45() argument
1360 return xgbe_write_ext_mii_regs(pdata, mdio_sca, val); in xgbe_write_ext_mii_regs_c45()
1363 static int xgbe_read_ext_mii_regs(struct xgbe_prv_data *pdata, in xgbe_read_ext_mii_regs() argument
1368 reinit_completion(&pdata->mdio_complete); in xgbe_read_ext_mii_regs()
1370 XGMAC_IOWRITE(pdata, MAC_MDIOSCAR, mdio_sca); in xgbe_read_ext_mii_regs()
1375 XGMAC_IOWRITE(pdata, MAC_MDIOSCCDR, mdio_sccd); in xgbe_read_ext_mii_regs()
1377 if (!wait_for_completion_timeout(&pdata->mdio_complete, HZ)) { in xgbe_read_ext_mii_regs()
1378 netdev_err(pdata->netdev, "mdio read operation timed out\n"); in xgbe_read_ext_mii_regs()
1382 return XGMAC_IOREAD_BITS(pdata, MAC_MDIOSCCDR, DATA); in xgbe_read_ext_mii_regs()
1385 static int xgbe_read_ext_mii_regs_c22(struct xgbe_prv_data *pdata, int addr, in xgbe_read_ext_mii_regs_c22() argument
1392 return xgbe_read_ext_mii_regs(pdata, mdio_sca); in xgbe_read_ext_mii_regs_c22()
1395 static int xgbe_read_ext_mii_regs_c45(struct xgbe_prv_data *pdata, int addr, in xgbe_read_ext_mii_regs_c45() argument
1402 return xgbe_read_ext_mii_regs(pdata, mdio_sca); in xgbe_read_ext_mii_regs_c45()
1405 static int xgbe_set_ext_mii_mode(struct xgbe_prv_data *pdata, unsigned int port, in xgbe_set_ext_mii_mode() argument
1408 unsigned int reg_val = XGMAC_IOREAD(pdata, MAC_MDIOCL22R); in xgbe_set_ext_mii_mode()
1422 XGMAC_IOWRITE(pdata, MAC_MDIOCL22R, reg_val); in xgbe_set_ext_mii_mode()
1432 static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_disable_rx_csum() argument
1434 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0); in xgbe_disable_rx_csum()
1439 static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata) in xgbe_enable_rx_csum() argument
1441 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1); in xgbe_enable_rx_csum()
1495 static void xgbe_rx_desc_reset(struct xgbe_prv_data *pdata, in xgbe_rx_desc_reset() argument
1499 unsigned int rx_usecs = pdata->rx_usecs; in xgbe_rx_desc_reset()
1500 unsigned int rx_frames = pdata->rx_frames; in xgbe_rx_desc_reset()
1545 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_rx_desc_init() local
1558 xgbe_rx_desc_reset(pdata, rdata, i); in xgbe_rx_desc_init()
1579 static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata, in xgbe_update_tstamp_addend() argument
1585 XGMAC_IOWRITE(pdata, MAC_TSAR, addend); in xgbe_update_tstamp_addend()
1586 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1); in xgbe_update_tstamp_addend()
1589 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG)) in xgbe_update_tstamp_addend()
1593 netdev_err(pdata->netdev, in xgbe_update_tstamp_addend()
1597 static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec, in xgbe_set_tstamp_time() argument
1603 XGMAC_IOWRITE(pdata, MAC_STSUR, sec); in xgbe_set_tstamp_time()
1604 XGMAC_IOWRITE(pdata, MAC_STNUR, nsec); in xgbe_set_tstamp_time()
1605 XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1); in xgbe_set_tstamp_time()
1608 while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT)) in xgbe_set_tstamp_time()
1612 netdev_err(pdata->netdev, "timed out initializing timestamp\n"); in xgbe_set_tstamp_time()
1615 static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata) in xgbe_get_tstamp_time() argument
1619 nsec = XGMAC_IOREAD(pdata, MAC_STSR); in xgbe_get_tstamp_time()
1621 nsec += XGMAC_IOREAD(pdata, MAC_STNR); in xgbe_get_tstamp_time()
1626 static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata) in xgbe_get_tx_tstamp() argument
1631 if (pdata->vdata->tx_tstamp_workaround) { in xgbe_get_tx_tstamp()
1632 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); in xgbe_get_tx_tstamp()
1633 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); in xgbe_get_tx_tstamp()
1635 tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR); in xgbe_get_tx_tstamp()
1636 tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR); in xgbe_get_tx_tstamp()
1667 static int xgbe_config_tstamp(struct xgbe_prv_data *pdata, in xgbe_config_tstamp() argument
1679 XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr); in xgbe_config_tstamp()
1686 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC); in xgbe_config_tstamp()
1687 XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC); in xgbe_config_tstamp()
1688 xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend); in xgbe_config_tstamp()
1689 xgbe_set_tstamp_time(pdata, 0, 0); in xgbe_config_tstamp()
1692 timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, in xgbe_config_tstamp()
1701 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_tx_start_xmit() local
1714 if (pdata->tx_usecs && !channel->tx_timer_active) { in xgbe_tx_start_xmit()
1717 jiffies + usecs_to_jiffies(pdata->tx_usecs)); in xgbe_tx_start_xmit()
1725 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_xmit() local
1773 if (!pdata->tx_frames) in xgbe_dev_xmit()
1775 else if (tx_packets > pdata->tx_frames) in xgbe_dev_xmit()
1777 else if ((ring->coalesce_count % pdata->tx_frames) < tx_packets) in xgbe_dev_xmit()
1788 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1808 netif_dbg(pdata, tx_queued, pdata->netdev, in xgbe_dev_xmit()
1867 pdata->ext_stats.tx_tso_packets += tx_packets; in xgbe_dev_xmit()
1886 pdata->ext_stats.tx_vxlan_packets += packet->tx_packets; in xgbe_dev_xmit()
1925 pdata->ext_stats.txq_packets[channel->queue_index] += tx_packets; in xgbe_dev_xmit()
1926 pdata->ext_stats.txq_bytes[channel->queue_index] += tx_bytes; in xgbe_dev_xmit()
1939 if (netif_msg_tx_queued(pdata)) in xgbe_dev_xmit()
1940 xgbe_dump_tx_desc(pdata, ring, start_index, in xgbe_dev_xmit()
1948 netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev, in xgbe_dev_xmit()
1963 struct xgbe_prv_data *pdata = channel->pdata; in xgbe_dev_read() local
1968 struct net_device *netdev = pdata->netdev; in xgbe_dev_read()
1983 if (netif_msg_rx_status(pdata)) in xgbe_dev_read()
1984 xgbe_dump_rx_desc(pdata, ring, ring->cur); in xgbe_dev_read()
2012 pdata->ext_stats.rx_split_header_packets++; in xgbe_dev_read()
2061 pdata->ext_stats.rx_vxlan_packets++; in xgbe_dev_read()
2076 netif_dbg(pdata, rx_status, netdev, "err=%u, etlt=%#x\n", err, etlt); in xgbe_dev_read()
2087 netif_dbg(pdata, rx_status, netdev, "vlan-ctag=%#06x\n", in xgbe_dev_read()
2099 pdata->ext_stats.rx_csum_errors++; in xgbe_dev_read()
2105 pdata->ext_stats.rx_vxlan_csum_errors++; in xgbe_dev_read()
2112 pdata->ext_stats.rxq_packets[channel->queue_index]++; in xgbe_dev_read()
2113 pdata->ext_stats.rxq_bytes[channel->queue_index] += rdata->rx.len; in xgbe_dev_read()
2216 static int __xgbe_exit(struct xgbe_prv_data *pdata) in __xgbe_exit() argument
2223 XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1); in __xgbe_exit()
2227 while (--count && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR)) in __xgbe_exit()
2238 static int xgbe_exit(struct xgbe_prv_data *pdata) in xgbe_exit() argument
2245 ret = __xgbe_exit(pdata); in xgbe_exit()
2249 return __xgbe_exit(pdata); in xgbe_exit()
2252 static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata) in xgbe_flush_tx_queues() argument
2256 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21) in xgbe_flush_tx_queues()
2259 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_flush_tx_queues()
2260 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1); in xgbe_flush_tx_queues()
2263 for (i = 0; i < pdata->tx_q_count; i++) { in xgbe_flush_tx_queues()
2265 while (--count && XGMAC_MTL_IOREAD_BITS(pdata, i, in xgbe_flush_tx_queues()
2276 static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata) in xgbe_config_dma_bus() argument
2280 sbmr = XGMAC_IOREAD(pdata, DMA_SBMR); in xgbe_config_dma_bus()
2287 XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2); in xgbe_config_dma_bus()
2288 XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal); in xgbe_config_dma_bus()
2289 XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1); in xgbe_config_dma_bus()
2290 XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1); in xgbe_config_dma_bus()
2292 XGMAC_IOWRITE(pdata, DMA_SBMR, sbmr); in xgbe_config_dma_bus()
2295 if (pdata->vdata->tx_desc_prefetch) in xgbe_config_dma_bus()
2296 XGMAC_IOWRITE_BITS(pdata, DMA_TXEDMACR, TDPS, in xgbe_config_dma_bus()
2297 pdata->vdata->tx_desc_prefetch); in xgbe_config_dma_bus()
2299 if (pdata->vdata->rx_desc_prefetch) in xgbe_config_dma_bus()
2300 XGMAC_IOWRITE_BITS(pdata, DMA_RXEDMACR, RDPS, in xgbe_config_dma_bus()
2301 pdata->vdata->rx_desc_prefetch); in xgbe_config_dma_bus()
2304 static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata) in xgbe_config_dma_cache() argument
2306 XGMAC_IOWRITE(pdata, DMA_AXIARCR, pdata->arcr); in xgbe_config_dma_cache()
2307 XGMAC_IOWRITE(pdata, DMA_AXIAWCR, pdata->awcr); in xgbe_config_dma_cache()
2308 if (pdata->awarcr) in xgbe_config_dma_cache()
2309 XGMAC_IOWRITE(pdata, DMA_AXIAWARCR, pdata->awarcr); in xgbe_config_dma_cache()
2312 static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata) in xgbe_config_mtl_mode() argument
2317 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR); in xgbe_config_mtl_mode()
2320 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_mtl_mode()
2321 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_mtl_mode()
2323 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1); in xgbe_config_mtl_mode()
2327 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP); in xgbe_config_mtl_mode()
2330 static void xgbe_queue_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_queue_flow_control_threshold() argument
2337 frame_fifo_size = XGMAC_FLOW_CONTROL_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_queue_flow_control_threshold()
2339 if (pdata->pfcq[queue] && (q_fifo_size > pdata->pfc_rfa)) { in xgbe_queue_flow_control_threshold()
2341 rfa = pdata->pfc_rfa; in xgbe_queue_flow_control_threshold()
2355 pdata->rx_rfa[queue] = 0; in xgbe_queue_flow_control_threshold()
2356 pdata->rx_rfd[queue] = 0; in xgbe_queue_flow_control_threshold()
2362 pdata->rx_rfa[queue] = 0; /* Full - 1024 bytes */ in xgbe_queue_flow_control_threshold()
2363 pdata->rx_rfd[queue] = 1; /* Full - 1536 bytes */ in xgbe_queue_flow_control_threshold()
2369 pdata->rx_rfa[queue] = 2; /* Full - 2048 bytes */ in xgbe_queue_flow_control_threshold()
2370 pdata->rx_rfd[queue] = 5; /* Full - 3584 bytes */ in xgbe_queue_flow_control_threshold()
2391 pdata->rx_rfa[queue] = XGMAC_FLOW_CONTROL_VALUE(rfa); in xgbe_queue_flow_control_threshold()
2392 pdata->rx_rfd[queue] = XGMAC_FLOW_CONTROL_VALUE(rfd); in xgbe_queue_flow_control_threshold()
2395 static void xgbe_calculate_flow_control_threshold(struct xgbe_prv_data *pdata, in xgbe_calculate_flow_control_threshold() argument
2401 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_calculate_flow_control_threshold()
2404 xgbe_queue_flow_control_threshold(pdata, i, q_fifo_size); in xgbe_calculate_flow_control_threshold()
2408 static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata) in xgbe_config_flow_control_threshold() argument
2412 for (i = 0; i < pdata->rx_q_count; i++) { in xgbe_config_flow_control_threshold()
2413 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFA, in xgbe_config_flow_control_threshold()
2414 pdata->rx_rfa[i]); in xgbe_config_flow_control_threshold()
2415 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQFCR, RFD, in xgbe_config_flow_control_threshold()
2416 pdata->rx_rfd[i]); in xgbe_config_flow_control_threshold()
2420 static unsigned int xgbe_get_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_tx_fifo_size() argument
2423 return min_t(unsigned int, pdata->tx_max_fifo_size, in xgbe_get_tx_fifo_size()
2424 pdata->hw_feat.tx_fifo_size); in xgbe_get_tx_fifo_size()
2427 static unsigned int xgbe_get_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_get_rx_fifo_size() argument
2430 return min_t(unsigned int, pdata->rx_max_fifo_size, in xgbe_get_rx_fifo_size()
2431 pdata->hw_feat.rx_fifo_size); in xgbe_get_rx_fifo_size()
2480 static unsigned int xgbe_get_pfc_delay(struct xgbe_prv_data *pdata) in xgbe_get_pfc_delay() argument
2485 if (pdata->pfc->delay) in xgbe_get_pfc_delay()
2486 return pdata->pfc->delay / 8; in xgbe_get_pfc_delay()
2489 delay = xgbe_get_max_frame(pdata); in xgbe_get_pfc_delay()
2504 static unsigned int xgbe_get_pfc_queues(struct xgbe_prv_data *pdata) in xgbe_get_pfc_queues() argument
2509 if (!pdata->pfc->pfc_en) in xgbe_get_pfc_queues()
2513 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_get_pfc_queues()
2515 if (!xgbe_is_pfc_queue(pdata, i)) in xgbe_get_pfc_queues()
2518 pdata->pfcq[i] = 1; in xgbe_get_pfc_queues()
2525 static void xgbe_calculate_dcb_fifo(struct xgbe_prv_data *pdata, in xgbe_calculate_dcb_fifo() argument
2534 q_fifo_size = XGMAC_FIFO_ALIGN(xgbe_get_max_frame(pdata)); in xgbe_calculate_dcb_fifo()
2535 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_calculate_dcb_fifo()
2536 pfc_count = xgbe_get_pfc_queues(pdata); in xgbe_calculate_dcb_fifo()
2550 pdata->pfc_rfa = xgbe_get_pfc_delay(pdata); in xgbe_calculate_dcb_fifo()
2551 pdata->pfc_rfa = XGMAC_FLOW_CONTROL_ALIGN(pdata->pfc_rfa); in xgbe_calculate_dcb_fifo()
2553 if (pdata->pfc_rfa > q_fifo_size) { in xgbe_calculate_dcb_fifo()
2554 addn_fifo = pdata->pfc_rfa - q_fifo_size; in xgbe_calculate_dcb_fifo()
2571 if (!pdata->pfcq[i] || !addn_fifo) in xgbe_calculate_dcb_fifo()
2575 netdev_warn(pdata->netdev, in xgbe_calculate_dcb_fifo()
2596 static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_tx_fifo_size() argument
2602 fifo_size = xgbe_get_tx_fifo_size(pdata); in xgbe_config_tx_fifo_size()
2604 xgbe_calculate_equal_fifo(fifo_size, pdata->tx_q_count, fifo); in xgbe_config_tx_fifo_size()
2606 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_config_tx_fifo_size()
2607 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo[i]); in xgbe_config_tx_fifo_size()
2609 netif_info(pdata, drv, pdata->netdev, in xgbe_config_tx_fifo_size()
2611 pdata->tx_q_count, ((fifo[0] + 1) * XGMAC_FIFO_UNIT)); in xgbe_config_tx_fifo_size()
2614 static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata) in xgbe_config_rx_fifo_size() argument
2622 memset(pdata->pfcq, 0, sizeof(pdata->pfcq)); in xgbe_config_rx_fifo_size()
2623 pdata->pfc_rfa = 0; in xgbe_config_rx_fifo_size()
2625 fifo_size = xgbe_get_rx_fifo_size(pdata); in xgbe_config_rx_fifo_size()
2626 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2629 fifo_size = xgbe_set_nonprio_fifos(fifo_size, pdata->rx_q_count, fifo); in xgbe_config_rx_fifo_size()
2631 if (pdata->pfc && pdata->ets) in xgbe_config_rx_fifo_size()
2632 xgbe_calculate_dcb_fifo(pdata, fifo_size, fifo); in xgbe_config_rx_fifo_size()
2636 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2637 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo[i]); in xgbe_config_rx_fifo_size()
2639 xgbe_calculate_flow_control_threshold(pdata, fifo); in xgbe_config_rx_fifo_size()
2640 xgbe_config_flow_control_threshold(pdata); in xgbe_config_rx_fifo_size()
2642 if (pdata->pfc && pdata->ets && pdata->pfc->pfc_en) { in xgbe_config_rx_fifo_size()
2643 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2644 "%u Rx hardware queues\n", pdata->rx_q_count); in xgbe_config_rx_fifo_size()
2645 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_config_rx_fifo_size()
2646 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2650 netif_info(pdata, drv, pdata->netdev, in xgbe_config_rx_fifo_size()
2652 pdata->rx_q_count, in xgbe_config_rx_fifo_size()
2657 static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata) in xgbe_config_queue_mapping() argument
2668 qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2669 qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt; in xgbe_config_queue_mapping()
2671 for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_queue_mapping()
2673 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2675 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2677 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2681 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2683 XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, in xgbe_config_queue_mapping()
2685 pdata->q2tc_map[queue++] = i; in xgbe_config_queue_mapping()
2690 prio_queues = XGMAC_PRIO_QUEUES(pdata->rx_q_count); in xgbe_config_queue_mapping()
2699 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2702 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2706 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_queue_mapping()
2709 pdata->prio2q_map[prio++] = i; in xgbe_config_queue_mapping()
2717 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2725 for (i = 0; i < pdata->rx_q_count;) { in xgbe_config_queue_mapping()
2728 if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count)) in xgbe_config_queue_mapping()
2731 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_queue_mapping()
2738 static void xgbe_config_tc(struct xgbe_prv_data *pdata) in xgbe_config_tc() argument
2743 netdev_reset_tc(pdata->netdev); in xgbe_config_tc()
2744 if (!pdata->num_tcs) in xgbe_config_tc()
2747 netdev_set_num_tc(pdata->netdev, pdata->num_tcs); in xgbe_config_tc()
2749 for (i = 0, queue = 0, offset = 0; i < pdata->num_tcs; i++) { in xgbe_config_tc()
2750 while ((queue < pdata->tx_q_count) && in xgbe_config_tc()
2751 (pdata->q2tc_map[queue] == i)) in xgbe_config_tc()
2754 netif_dbg(pdata, drv, pdata->netdev, "TC%u using TXq%u-%u\n", in xgbe_config_tc()
2756 netdev_set_tc_queue(pdata->netdev, i, queue - offset, offset); in xgbe_config_tc()
2760 if (!pdata->ets) in xgbe_config_tc()
2764 netdev_set_prio_tc_map(pdata->netdev, prio, in xgbe_config_tc()
2765 pdata->ets->prio_tc[prio]); in xgbe_config_tc()
2768 static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_tc() argument
2770 struct ieee_ets *ets = pdata->ets; in xgbe_config_dcb_tc()
2781 XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR); in xgbe_config_dcb_tc()
2784 total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt; in xgbe_config_dcb_tc()
2789 for (i = 0; i < pdata->hw_feat.tc_cnt; i++) { in xgbe_config_dcb_tc()
2798 netif_dbg(pdata, drv, pdata->netdev, "TC%u PRIO mask=%#x\n", in xgbe_config_dcb_tc()
2801 reg_val = XGMAC_IOREAD(pdata, reg); in xgbe_config_dcb_tc()
2806 XGMAC_IOWRITE(pdata, reg, reg_val); in xgbe_config_dcb_tc()
2811 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2813 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2820 netif_dbg(pdata, drv, pdata->netdev, in xgbe_config_dcb_tc()
2822 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA, in xgbe_config_dcb_tc()
2824 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, in xgbe_config_dcb_tc()
2830 xgbe_config_tc(pdata); in xgbe_config_dcb_tc()
2833 static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata) in xgbe_config_dcb_pfc() argument
2835 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2837 netif_tx_stop_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2840 pdata->hw_if.disable_rx(pdata); in xgbe_config_dcb_pfc()
2843 xgbe_config_rx_fifo_size(pdata); in xgbe_config_dcb_pfc()
2844 xgbe_config_flow_control(pdata); in xgbe_config_dcb_pfc()
2846 if (!test_bit(XGBE_DOWN, &pdata->dev_state)) { in xgbe_config_dcb_pfc()
2848 pdata->hw_if.enable_rx(pdata); in xgbe_config_dcb_pfc()
2851 netif_tx_start_all_queues(pdata->netdev); in xgbe_config_dcb_pfc()
2855 static void xgbe_config_mac_address(struct xgbe_prv_data *pdata) in xgbe_config_mac_address() argument
2857 xgbe_set_mac_address(pdata, pdata->netdev->dev_addr); in xgbe_config_mac_address()
2860 if (pdata->hw_feat.hash_table_size) { in xgbe_config_mac_address()
2861 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1); in xgbe_config_mac_address()
2862 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1); in xgbe_config_mac_address()
2863 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1); in xgbe_config_mac_address()
2867 static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata) in xgbe_config_jumbo_enable() argument
2871 val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0; in xgbe_config_jumbo_enable()
2873 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val); in xgbe_config_jumbo_enable()
2876 static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata) in xgbe_config_mac_speed() argument
2878 xgbe_set_speed(pdata, pdata->phy_speed); in xgbe_config_mac_speed()
2881 static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata) in xgbe_config_checksum_offload() argument
2883 if (pdata->netdev->features & NETIF_F_RXCSUM) in xgbe_config_checksum_offload()
2884 xgbe_enable_rx_csum(pdata); in xgbe_config_checksum_offload()
2886 xgbe_disable_rx_csum(pdata); in xgbe_config_checksum_offload()
2889 static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata) in xgbe_config_vlan_support() argument
2892 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0); in xgbe_config_vlan_support()
2893 XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1); in xgbe_config_vlan_support()
2896 xgbe_update_vlan_hash_table(pdata); in xgbe_config_vlan_support()
2898 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER) in xgbe_config_vlan_support()
2899 xgbe_enable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2901 xgbe_disable_rx_vlan_filtering(pdata); in xgbe_config_vlan_support()
2903 if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) in xgbe_config_vlan_support()
2904 xgbe_enable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2906 xgbe_disable_rx_vlan_stripping(pdata); in xgbe_config_vlan_support()
2909 static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo) in xgbe_mmc_read() argument
2914 if (pdata->vdata->mmc_64bit) { in xgbe_mmc_read()
2943 val = XGMAC_IOREAD(pdata, reg_lo); in xgbe_mmc_read()
2946 val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32); in xgbe_mmc_read()
2951 static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_tx_mmc_int() argument
2953 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_tx_mmc_int()
2954 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR); in xgbe_tx_mmc_int()
2958 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_tx_mmc_int()
2962 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_tx_mmc_int()
2966 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2970 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_tx_mmc_int()
2974 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_tx_mmc_int()
2978 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_tx_mmc_int()
2982 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_tx_mmc_int()
2986 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_tx_mmc_int()
2990 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_tx_mmc_int()
2994 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_tx_mmc_int()
2998 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
3002 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
3006 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_tx_mmc_int()
3010 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_tx_mmc_int()
3014 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_tx_mmc_int()
3018 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_tx_mmc_int()
3022 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_tx_mmc_int()
3026 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_tx_mmc_int()
3029 static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata) in xgbe_rx_mmc_int() argument
3031 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_rx_mmc_int()
3032 unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR); in xgbe_rx_mmc_int()
3036 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_rx_mmc_int()
3040 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_rx_mmc_int()
3044 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_rx_mmc_int()
3048 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_rx_mmc_int()
3052 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
3056 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_rx_mmc_int()
3060 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_rx_mmc_int()
3064 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_rx_mmc_int()
3068 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_rx_mmc_int()
3072 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_rx_mmc_int()
3076 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_rx_mmc_int()
3080 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_rx_mmc_int()
3084 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_rx_mmc_int()
3088 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_rx_mmc_int()
3092 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_rx_mmc_int()
3096 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_rx_mmc_int()
3100 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_rx_mmc_int()
3104 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_rx_mmc_int()
3108 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_rx_mmc_int()
3112 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_rx_mmc_int()
3116 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_rx_mmc_int()
3120 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_rx_mmc_int()
3124 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_rx_mmc_int()
3127 static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata) in xgbe_read_mmc_stats() argument
3129 struct xgbe_mmc_stats *stats = &pdata->mmc_stats; in xgbe_read_mmc_stats()
3132 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1); in xgbe_read_mmc_stats()
3135 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3138 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3141 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3144 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3147 xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3150 xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3153 xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3156 xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3159 xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3162 xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3165 xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3168 xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3171 xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO); in xgbe_read_mmc_stats()
3174 xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO); in xgbe_read_mmc_stats()
3177 xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3180 xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO); in xgbe_read_mmc_stats()
3183 xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3186 xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO); in xgbe_read_mmc_stats()
3189 xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO); in xgbe_read_mmc_stats()
3192 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO); in xgbe_read_mmc_stats()
3195 xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO); in xgbe_read_mmc_stats()
3198 xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3201 xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3204 xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO); in xgbe_read_mmc_stats()
3207 xgbe_mmc_read(pdata, MMC_RXRUNTERROR); in xgbe_read_mmc_stats()
3210 xgbe_mmc_read(pdata, MMC_RXJABBERERROR); in xgbe_read_mmc_stats()
3213 xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G); in xgbe_read_mmc_stats()
3216 xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G); in xgbe_read_mmc_stats()
3219 xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO); in xgbe_read_mmc_stats()
3222 xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO); in xgbe_read_mmc_stats()
3225 xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO); in xgbe_read_mmc_stats()
3228 xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO); in xgbe_read_mmc_stats()
3231 xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO); in xgbe_read_mmc_stats()
3234 xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO); in xgbe_read_mmc_stats()
3237 xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO); in xgbe_read_mmc_stats()
3240 xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO); in xgbe_read_mmc_stats()
3243 xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO); in xgbe_read_mmc_stats()
3246 xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO); in xgbe_read_mmc_stats()
3249 xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO); in xgbe_read_mmc_stats()
3252 xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO); in xgbe_read_mmc_stats()
3255 xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR); in xgbe_read_mmc_stats()
3258 XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0); in xgbe_read_mmc_stats()
3261 static void xgbe_config_mmc(struct xgbe_prv_data *pdata) in xgbe_config_mmc() argument
3264 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
3267 XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1); in xgbe_config_mmc()
3270 static void xgbe_txq_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_txq_prepare_tx_stop() argument
3282 tx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); in xgbe_txq_prepare_tx_stop()
3291 netdev_info(pdata->netdev, in xgbe_txq_prepare_tx_stop()
3296 static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_tx_stop() argument
3303 if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) in xgbe_prepare_tx_stop()
3304 return xgbe_txq_prepare_tx_stop(pdata, queue); in xgbe_prepare_tx_stop()
3324 tx_status = XGMAC_IOREAD(pdata, tx_dsr); in xgbe_prepare_tx_stop()
3334 netdev_info(pdata->netdev, in xgbe_prepare_tx_stop()
3339 static void xgbe_enable_tx(struct xgbe_prv_data *pdata) in xgbe_enable_tx() argument
3344 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_tx()
3345 if (!pdata->channel[i]->tx_ring) in xgbe_enable_tx()
3348 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_enable_tx()
3352 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_enable_tx()
3353 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, in xgbe_enable_tx()
3357 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_enable_tx()
3360 static void xgbe_disable_tx(struct xgbe_prv_data *pdata) in xgbe_disable_tx() argument
3365 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3366 xgbe_prepare_tx_stop(pdata, i); in xgbe_disable_tx()
3369 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_disable_tx()
3372 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_disable_tx()
3373 XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0); in xgbe_disable_tx()
3376 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_tx()
3377 if (!pdata->channel[i]->tx_ring) in xgbe_disable_tx()
3380 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_disable_tx()
3384 static void xgbe_prepare_rx_stop(struct xgbe_prv_data *pdata, in xgbe_prepare_rx_stop() argument
3396 rx_status = XGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); in xgbe_prepare_rx_stop()
3405 netdev_info(pdata->netdev, in xgbe_prepare_rx_stop()
3410 static void xgbe_enable_rx(struct xgbe_prv_data *pdata) in xgbe_enable_rx() argument
3415 for (i = 0; i < pdata->channel_count; i++) { in xgbe_enable_rx()
3416 if (!pdata->channel[i]->rx_ring) in xgbe_enable_rx()
3419 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_enable_rx()
3424 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_enable_rx()
3426 XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); in xgbe_enable_rx()
3429 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); in xgbe_enable_rx()
3430 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); in xgbe_enable_rx()
3431 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); in xgbe_enable_rx()
3432 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); in xgbe_enable_rx()
3435 static void xgbe_disable_rx(struct xgbe_prv_data *pdata) in xgbe_disable_rx() argument
3440 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); in xgbe_disable_rx()
3441 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); in xgbe_disable_rx()
3442 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); in xgbe_disable_rx()
3443 XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); in xgbe_disable_rx()
3446 for (i = 0; i < pdata->rx_q_count; i++) in xgbe_disable_rx()
3447 xgbe_prepare_rx_stop(pdata, i); in xgbe_disable_rx()
3450 XGMAC_IOWRITE(pdata, MAC_RQC0R, 0); in xgbe_disable_rx()
3453 for (i = 0; i < pdata->channel_count; i++) { in xgbe_disable_rx()
3454 if (!pdata->channel[i]->rx_ring) in xgbe_disable_rx()
3457 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_disable_rx()
3461 static void xgbe_powerup_tx(struct xgbe_prv_data *pdata) in xgbe_powerup_tx() argument
3466 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_tx()
3467 if (!pdata->channel[i]->tx_ring) in xgbe_powerup_tx()
3470 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 1); in xgbe_powerup_tx()
3474 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); in xgbe_powerup_tx()
3477 static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata) in xgbe_powerdown_tx() argument
3482 for (i = 0; i < pdata->tx_q_count; i++) in xgbe_powerdown_tx()
3483 xgbe_prepare_tx_stop(pdata, i); in xgbe_powerdown_tx()
3486 XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); in xgbe_powerdown_tx()
3489 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_tx()
3490 if (!pdata->channel[i]->tx_ring) in xgbe_powerdown_tx()
3493 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_TCR, ST, 0); in xgbe_powerdown_tx()
3497 static void xgbe_powerup_rx(struct xgbe_prv_data *pdata) in xgbe_powerup_rx() argument
3502 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerup_rx()
3503 if (!pdata->channel[i]->rx_ring) in xgbe_powerup_rx()
3506 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 1); in xgbe_powerup_rx()
3510 static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata) in xgbe_powerdown_rx() argument
3515 for (i = 0; i < pdata->channel_count; i++) { in xgbe_powerdown_rx()
3516 if (!pdata->channel[i]->rx_ring) in xgbe_powerdown_rx()
3519 XGMAC_DMA_IOWRITE_BITS(pdata->channel[i], DMA_CH_RCR, SR, 0); in xgbe_powerdown_rx()
3523 static int xgbe_init(struct xgbe_prv_data *pdata) in xgbe_init() argument
3525 struct xgbe_desc_if *desc_if = &pdata->desc_if; in xgbe_init()
3531 ret = xgbe_flush_tx_queues(pdata); in xgbe_init()
3533 netdev_err(pdata->netdev, "error flushing TX queues\n"); in xgbe_init()
3540 xgbe_config_dma_bus(pdata); in xgbe_init()
3541 xgbe_config_dma_cache(pdata); in xgbe_init()
3542 xgbe_config_osp_mode(pdata); in xgbe_init()
3543 xgbe_config_pbl_val(pdata); in xgbe_init()
3544 xgbe_config_rx_coalesce(pdata); in xgbe_init()
3545 xgbe_config_tx_coalesce(pdata); in xgbe_init()
3546 xgbe_config_rx_buffer_size(pdata); in xgbe_init()
3547 xgbe_config_tso_mode(pdata); in xgbe_init()
3548 xgbe_config_sph_mode(pdata); in xgbe_init()
3549 xgbe_config_rss(pdata); in xgbe_init()
3550 desc_if->wrapper_tx_desc_init(pdata); in xgbe_init()
3551 desc_if->wrapper_rx_desc_init(pdata); in xgbe_init()
3552 xgbe_enable_dma_interrupts(pdata); in xgbe_init()
3557 xgbe_config_mtl_mode(pdata); in xgbe_init()
3558 xgbe_config_queue_mapping(pdata); in xgbe_init()
3559 xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode); in xgbe_init()
3560 xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode); in xgbe_init()
3561 xgbe_config_tx_threshold(pdata, pdata->tx_threshold); in xgbe_init()
3562 xgbe_config_rx_threshold(pdata, pdata->rx_threshold); in xgbe_init()
3563 xgbe_config_tx_fifo_size(pdata); in xgbe_init()
3564 xgbe_config_rx_fifo_size(pdata); in xgbe_init()
3568 xgbe_config_dcb_tc(pdata); in xgbe_init()
3569 xgbe_enable_mtl_interrupts(pdata); in xgbe_init()
3574 xgbe_config_mac_address(pdata); in xgbe_init()
3575 xgbe_config_rx_mode(pdata); in xgbe_init()
3576 xgbe_config_jumbo_enable(pdata); in xgbe_init()
3577 xgbe_config_flow_control(pdata); in xgbe_init()
3578 xgbe_config_mac_speed(pdata); in xgbe_init()
3579 xgbe_config_checksum_offload(pdata); in xgbe_init()
3580 xgbe_config_vlan_support(pdata); in xgbe_init()
3581 xgbe_config_mmc(pdata); in xgbe_init()
3582 xgbe_enable_mac_interrupts(pdata); in xgbe_init()
3587 xgbe_enable_ecc_interrupts(pdata); in xgbe_init()