1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4  * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5  * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7  * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9  * can be connected to the CPU - or another PHY - via either MII, RMII, or
10  * RGMII. The switch is configured via the Realtek Simple Management Interface
11  * (SMI), which uses the MDIO/MDC lines.
15  *                          .-----------------------------------.
17  *         UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC   |
18  *         UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC   |
19  *         UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC   |
20  *         UTP <---------------> Giga PHY <-> PCS <-> P3 GMAC   |
22  *     CPU/PHY <-MII/RMII/RGMII--->  Extension  <---> Extension |
25  *     SMI driver/ <-MDC/SCL---> Management    ~~~~~~~~~~~~~~   |
26  *        EEPROM   <-MDIO/SDA--> interface     ~REALTEK ~~~~~   |
29  *        GPIO <--------------> Reset          ~~~~~~~~~~~~~~   |
31  *      Interrupt  <----------> Link UP/DOWN events             |
33  *                          '-----------------------------------'
38  * partner of the extension port - either via a fixed-link or other phy-handle.
40  * driver has only been tested with a fixed-link, but in principle it should not
47  * the status registers via SMI. Interrupts are then propagated to the relevant
55  * This Linux driver is written based on an OS-agnostic vendor driver from
56  * Realtek. The reference GPL-licensed sources can be found in the OpenWrt
58  * number of similar switch controllers from Realtek, but the only hardware we
59  * have is the RTL8365MB-VC. Moreover, there does not seem to be any chip under
61  * common hardware revision, there exist examples of chips with the suffix -VC
70  * documentation from Realtek, the family should include the following chips:
72  *  - RTL8363NB
73  *  - RTL8363NB-VB
74  *  - RTL8363SC
75  *  - RTL8363SC-VB
76  *  - RTL8364NB
77  *  - RTL8364NB-VB
78  *  - RTL8365MB-VC
79  *  - RTL8366SC
80  *  - RTL8367RB-VB
81  *  - RTL8367SB
82  *  - RTL8367S
83  *  - RTL8370MB
84  *  - RTL8310SR
88  * things will work out-of-the-box for other chips, and a careful review of the
89  * vendor driver may be needed to expand support. The RTL8365MB-VC seems to be
103 #include "realtek.h"
105 /* Family-specific data and limits */
108 #define RTL8365MB_PHYREGMAX		(RTL8365MB_NUM_PHYREGS - 1)
132 /* Interrupt control/status register - enable/check specific interrupt types */
161 /* Per-port interrupt type status registers */
192 /* External interface port mode values - used in DIGITAL_INTERFACE_SELECT */
232 /* External interface port speed values - used in DIGITAL_INTERFACE_FORCE */
254 /* CPU port mask register - controls which ports are treated as CPU ports */
284 /* MSTP port state registers - indexed by tree instance */
482  * struct rtl8365mb_extint - external interface info
487  * Represents a mapping: port -> { id, supported_interfaces }. To be embedded
497  * struct rtl8365mb_chip_info - static chip-specific info
498  * @name: human-readable chip name
502  * @jam_table: chip-specific initialization jam table
522 		.name = "RTL8365MB-VC",
545 		.name = "RTL8367RB-VB",
588  * struct rtl8365mb_cpu - CPU port configuration
589  * @enable: enable/disable hardware insertion of CPU tag in switch->CPU frames
592  * @insert: CPU tag insertion mode in switch->CPU frames
611  * struct rtl8365mb_port - private per-port data
628  * struct rtl8365mb - driver private data
631  * @chip_info: chip-specific info about the attached switch
634  * @ports: per-port data
651 	return regmap_read_poll_timeout(priv->map_nolock,  in rtl8365mb_phy_poll_busy()
665 		priv->map_nolock, RTL8365MB_GPHY_OCP_MSB_0_REG,  in rtl8365mb_phy_ocp_prepare()
678 	ret = regmap_write(priv->map_nolock,  in rtl8365mb_phy_ocp_prepare()
692 	mutex_lock(&priv->map_lock);  in rtl8365mb_phy_ocp_read()
707 	ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,  in rtl8365mb_phy_ocp_read()
717 	ret = regmap_read(priv->map_nolock,  in rtl8365mb_phy_ocp_read()
725 	mutex_unlock(&priv->map_lock);  in rtl8365mb_phy_ocp_read()
736 	mutex_lock(&priv->map_lock);  in rtl8365mb_phy_ocp_write()
747 	ret = regmap_write(priv->map_nolock,  in rtl8365mb_phy_ocp_write()
757 	ret = regmap_write(priv->map_nolock, RTL8365MB_INDIRECT_ACCESS_CTRL_REG,  in rtl8365mb_phy_ocp_write()
767 	mutex_unlock(&priv->map_lock);  in rtl8365mb_phy_ocp_write()
779 		return -EINVAL;  in rtl8365mb_phy_read()
782 		return -EINVAL;  in rtl8365mb_phy_read()
788 		dev_err(priv->dev,  in rtl8365mb_phy_read()
794 	dev_dbg(priv->dev, "read PHY%d register 0x%02x @ %04x, val <- %04x\n",  in rtl8365mb_phy_read()
807 		return -EINVAL;  in rtl8365mb_phy_write()
810 		return -EINVAL;  in rtl8365mb_phy_write()
816 		dev_err(priv->dev,  in rtl8365mb_phy_write()
822 	dev_dbg(priv->dev, "write PHY%d register 0x%02x @ %04x, val -> %04x\n",  in rtl8365mb_phy_write()
830 	return rtl8365mb_phy_read(ds->priv, phy, regnum);  in rtl8365mb_dsa_phy_read()
836 	return rtl8365mb_phy_write(ds->priv, phy, regnum, val);  in rtl8365mb_dsa_phy_write()
842 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_get_port_extint()
847 			&mb->chip_info->extints[i];  in rtl8365mb_get_port_extint()
849 		if (!extint->supported_interfaces)  in rtl8365mb_get_port_extint()
852 		if (extint->port == port)  in rtl8365mb_get_port_extint()
863 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_tag_protocol()
867 	mb = priv->chip_data;  in rtl8365mb_get_tag_protocol()
868 	cpu = &mb->cpu;  in rtl8365mb_get_tag_protocol()
870 	if (cpu->position == RTL8365MB_CPU_POS_BEFORE_CRC)  in rtl8365mb_get_tag_protocol()
889 		return -ENODEV;  in rtl8365mb_ext_config_rgmii()
891 	dp = dsa_to_port(priv->ds, port);  in rtl8365mb_ext_config_rgmii()
892 	dn = dp->dn;  in rtl8365mb_ext_config_rgmii()
896 	 * The Realtek vendor driver indicates the following possible  in rtl8365mb_ext_config_rgmii()
911 	 * tx-internal-delay-ps (resp. rx-internal-delay-ps) OF property is  in rtl8365mb_ext_config_rgmii()
913 	 * (RGMII_{RXID, TXID, etc.}), as this is considered to be a PHY-only  in rtl8365mb_ext_config_rgmii()
916 	if (!of_property_read_u32(dn, "tx-internal-delay-ps", &val)) {  in rtl8365mb_ext_config_rgmii()
922 			dev_warn(priv->dev,  in rtl8365mb_ext_config_rgmii()
926 	if (!of_property_read_u32(dn, "rx-internal-delay-ps", &val)) {  in rtl8365mb_ext_config_rgmii()
932 			dev_warn(priv->dev,  in rtl8365mb_ext_config_rgmii()
937 		priv->map, RTL8365MB_EXT_RGMXF_REG(extint->id),  in rtl8365mb_ext_config_rgmii()
946 		priv->map, RTL8365MB_DIGITAL_INTERFACE_SELECT_REG(extint->id),  in rtl8365mb_ext_config_rgmii()
947 		RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(extint->id),  in rtl8365mb_ext_config_rgmii()
950 				   extint->id));  in rtl8365mb_ext_config_rgmii()
972 		return -ENODEV;  in rtl8365mb_ext_config_forcemode()
987 			dev_err(priv->dev, "unsupported port speed %s\n",  in rtl8365mb_ext_config_forcemode()
989 			return -EINVAL;  in rtl8365mb_ext_config_forcemode()
997 			dev_err(priv->dev, "unsupported duplex %s\n",  in rtl8365mb_ext_config_forcemode()
999 			return -EINVAL;  in rtl8365mb_ext_config_forcemode()
1019 	ret = regmap_write(priv->map,  in rtl8365mb_ext_config_forcemode()
1020 			   RTL8365MB_DIGITAL_INTERFACE_FORCE_REG(extint->id),  in rtl8365mb_ext_config_forcemode()
1032 		rtl8365mb_get_port_extint(ds->priv, port);  in rtl8365mb_phylink_get_caps()
1034 	config->mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |  in rtl8365mb_phylink_get_caps()
1039 			  config->supported_interfaces);  in rtl8365mb_phylink_get_caps()
1045 			  config->supported_interfaces);  in rtl8365mb_phylink_get_caps()
1054 	if (extint->supported_interfaces & RTL8365MB_PHY_INTERFACE_MODE_RGMII)  in rtl8365mb_phylink_get_caps()
1055 		phy_interface_set_rgmii(config->supported_interfaces);  in rtl8365mb_phylink_get_caps()
1062 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_phylink_mac_config()
1066 		dev_err(priv->dev,  in rtl8365mb_phylink_mac_config()
1067 			"port %d supports only conventional PHY or fixed-link\n",  in rtl8365mb_phylink_mac_config()
1072 	if (phy_interface_mode_is_rgmii(state->interface)) {  in rtl8365mb_phylink_mac_config()
1073 		ret = rtl8365mb_ext_config_rgmii(priv, port, state->interface);  in rtl8365mb_phylink_mac_config()
1075 			dev_err(priv->dev,  in rtl8365mb_phylink_mac_config()
1081 	/* TODO: Implement MII and RMII modes, which the RTL8365MB-VC also  in rtl8365mb_phylink_mac_config()
1090 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_phylink_mac_link_down()
1095 	mb = priv->chip_data;  in rtl8365mb_phylink_mac_link_down()
1096 	p = &mb->ports[port];  in rtl8365mb_phylink_mac_link_down()
1097 	cancel_delayed_work_sync(&p->mib_work);  in rtl8365mb_phylink_mac_link_down()
1103 			dev_err(priv->dev,  in rtl8365mb_phylink_mac_link_down()
1118 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_phylink_mac_link_up()
1123 	mb = priv->chip_data;  in rtl8365mb_phylink_mac_link_up()
1124 	p = &mb->ports[port];  in rtl8365mb_phylink_mac_link_up()
1125 	schedule_delayed_work(&p->mib_work, 0);  in rtl8365mb_phylink_mac_link_up()
1132 			dev_err(priv->dev,  in rtl8365mb_phylink_mac_link_up()
1143 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_port_change_mtu()
1155 	dev_dbg(priv->dev, "changing mtu to %d (frame size: %d)\n",  in rtl8365mb_port_change_mtu()
1158 	return regmap_update_bits(priv->map, RTL8365MB_CFG0_MAX_LEN_REG,  in rtl8365mb_port_change_mtu()
1166 	return RTL8365MB_CFG0_MAX_LEN_MAX - VLAN_ETH_HLEN - ETH_FCS_LEN;  in rtl8365mb_port_max_mtu()
1172 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_port_stp_state_set()
1191 		dev_err(priv->dev, "invalid STP state: %u\n", state);  in rtl8365mb_port_stp_state_set()
1195 	regmap_update_bits(priv->map, RTL8365MB_MSTI_CTRL_REG(msti, port),  in rtl8365mb_port_stp_state_set()
1204 	 * port can learn. Realtek documentation states that a limit of zero  in rtl8365mb_port_set_learning()
1208 	return regmap_write(priv->map, RTL8365MB_LUT_PORT_LEARN_LIMIT_REG(port),  in rtl8365mb_port_set_learning()
1215 	return regmap_write(priv->map, RTL8365MB_PORT_ISOLATION_REG(port), mask);  in rtl8365mb_port_set_isolation()
1230 	ret = regmap_write(priv->map, RTL8365MB_MIB_ADDRESS_REG,  in rtl8365mb_mib_counter_read()
1236 	ret = regmap_read_poll_timeout(priv->map, RTL8365MB_MIB_CTRL0_REG, val,  in rtl8365mb_mib_counter_read()
1244 		return -EIO;  in rtl8365mb_mib_counter_read()
1258 		ret = regmap_read(priv->map,  in rtl8365mb_mib_counter_read()
1259 				  RTL8365MB_MIB_COUNTER_REG(offset - i), &val);  in rtl8365mb_mib_counter_read()
1274 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_ethtool_stats()
1279 	mb = priv->chip_data;  in rtl8365mb_get_ethtool_stats()
1281 	mutex_lock(&mb->mib_lock);  in rtl8365mb_get_ethtool_stats()
1285 		ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,  in rtl8365mb_get_ethtool_stats()
1286 						 mib->length, &data[i]);  in rtl8365mb_get_ethtool_stats()
1288 			dev_err(priv->dev,  in rtl8365mb_get_ethtool_stats()
1294 	mutex_unlock(&mb->mib_lock);  in rtl8365mb_get_ethtool_stats()
1307 		strncpy(data + i * ETH_GSTRING_LEN, mib->name, ETH_GSTRING_LEN);  in rtl8365mb_get_strings()
1314 		return -EOPNOTSUPP;  in rtl8365mb_get_sset_count()
1322 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_phy_stats()
1326 	mb = priv->chip_data;  in rtl8365mb_get_phy_stats()
1329 	mutex_lock(&mb->mib_lock);  in rtl8365mb_get_phy_stats()
1330 	rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,  in rtl8365mb_get_phy_stats()
1331 				   &phy_stats->SymbolErrorDuringCarrier);  in rtl8365mb_get_phy_stats()
1332 	mutex_unlock(&mb->mib_lock);  in rtl8365mb_get_phy_stats()
1358 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_mac_stats()
1363 	mb = priv->chip_data;  in rtl8365mb_get_mac_stats()
1365 	mutex_lock(&mb->mib_lock);  in rtl8365mb_get_mac_stats()
1373 		ret = rtl8365mb_mib_counter_read(priv, port, mib->offset,  in rtl8365mb_get_mac_stats()
1374 						 mib->length, &cnt[i]);  in rtl8365mb_get_mac_stats()
1378 	mutex_unlock(&mb->mib_lock);  in rtl8365mb_get_mac_stats()
1380 	/* The RTL8365MB-VC exposes MIB objects, which we have to translate into  in rtl8365mb_get_mac_stats()
1386 	mac_stats->FramesTransmittedOK = cnt[RTL8365MB_MIB_ifOutUcastPkts] +  in rtl8365mb_get_mac_stats()
1389 					 cnt[RTL8365MB_MIB_dot3OutPauseFrames] -  in rtl8365mb_get_mac_stats()
1391 	mac_stats->SingleCollisionFrames =  in rtl8365mb_get_mac_stats()
1393 	mac_stats->MultipleCollisionFrames =  in rtl8365mb_get_mac_stats()
1395 	mac_stats->FramesReceivedOK = cnt[RTL8365MB_MIB_ifInUcastPkts] +  in rtl8365mb_get_mac_stats()
1399 	mac_stats->FrameCheckSequenceErrors =  in rtl8365mb_get_mac_stats()
1401 	mac_stats->OctetsTransmittedOK = cnt[RTL8365MB_MIB_ifOutOctets] -  in rtl8365mb_get_mac_stats()
1402 					 18 * mac_stats->FramesTransmittedOK;  in rtl8365mb_get_mac_stats()
1403 	mac_stats->FramesWithDeferredXmissions =  in rtl8365mb_get_mac_stats()
1405 	mac_stats->LateCollisions = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];  in rtl8365mb_get_mac_stats()
1406 	mac_stats->FramesAbortedDueToXSColls =  in rtl8365mb_get_mac_stats()
1408 	mac_stats->OctetsReceivedOK = cnt[RTL8365MB_MIB_ifInOctets] -  in rtl8365mb_get_mac_stats()
1409 				      18 * mac_stats->FramesReceivedOK;  in rtl8365mb_get_mac_stats()
1410 	mac_stats->MulticastFramesXmittedOK =  in rtl8365mb_get_mac_stats()
1412 	mac_stats->BroadcastFramesXmittedOK =  in rtl8365mb_get_mac_stats()
1414 	mac_stats->MulticastFramesReceivedOK =  in rtl8365mb_get_mac_stats()
1416 	mac_stats->BroadcastFramesReceivedOK =  in rtl8365mb_get_mac_stats()
1423 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_ctrl_stats()
1427 	mb = priv->chip_data;  in rtl8365mb_get_ctrl_stats()
1430 	mutex_lock(&mb->mib_lock);  in rtl8365mb_get_ctrl_stats()
1431 	rtl8365mb_mib_counter_read(priv, port, mib->offset, mib->length,  in rtl8365mb_get_ctrl_stats()
1432 				   &ctrl_stats->UnsupportedOpcodesReceived);  in rtl8365mb_get_ctrl_stats()
1433 	mutex_unlock(&mb->mib_lock);  in rtl8365mb_get_ctrl_stats()
1455 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_stats_update()
1460 	stats = &mb->ports[port].stats;  in rtl8365mb_stats_update()
1462 	mutex_lock(&mb->mib_lock);  in rtl8365mb_stats_update()
1470 		ret = rtl8365mb_mib_counter_read(priv, port, c->offset,  in rtl8365mb_stats_update()
1471 						 c->length, &cnt[i]);  in rtl8365mb_stats_update()
1475 	mutex_unlock(&mb->mib_lock);  in rtl8365mb_stats_update()
1481 	spin_lock(&mb->ports[port].stats_lock);  in rtl8365mb_stats_update()
1483 	stats->rx_packets = cnt[RTL8365MB_MIB_ifInUcastPkts] +  in rtl8365mb_stats_update()
1485 			    cnt[RTL8365MB_MIB_ifInBroadcastPkts] -  in rtl8365mb_stats_update()
1488 	stats->tx_packets = cnt[RTL8365MB_MIB_ifOutUcastPkts] +  in rtl8365mb_stats_update()
1492 	/* if{In,Out}Octets includes FCS - remove it */  in rtl8365mb_stats_update()
1493 	stats->rx_bytes = cnt[RTL8365MB_MIB_ifInOctets] - 4 * stats->rx_packets;  in rtl8365mb_stats_update()
1494 	stats->tx_bytes =  in rtl8365mb_stats_update()
1495 		cnt[RTL8365MB_MIB_ifOutOctets] - 4 * stats->tx_packets;  in rtl8365mb_stats_update()
1497 	stats->rx_dropped = cnt[RTL8365MB_MIB_etherStatsDropEvents];  in rtl8365mb_stats_update()
1498 	stats->tx_dropped = cnt[RTL8365MB_MIB_ifOutDiscards];  in rtl8365mb_stats_update()
1500 	stats->multicast = cnt[RTL8365MB_MIB_ifInMulticastPkts];  in rtl8365mb_stats_update()
1501 	stats->collisions = cnt[RTL8365MB_MIB_etherStatsCollisions];  in rtl8365mb_stats_update()
1503 	stats->rx_length_errors = cnt[RTL8365MB_MIB_etherStatsFragments] +  in rtl8365mb_stats_update()
1505 	stats->rx_crc_errors = cnt[RTL8365MB_MIB_dot3StatsFCSErrors];  in rtl8365mb_stats_update()
1506 	stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors;  in rtl8365mb_stats_update()
1508 	stats->tx_aborted_errors = cnt[RTL8365MB_MIB_ifOutDiscards];  in rtl8365mb_stats_update()
1509 	stats->tx_window_errors = cnt[RTL8365MB_MIB_dot3StatsLateCollisions];  in rtl8365mb_stats_update()
1510 	stats->tx_errors = stats->tx_aborted_errors + stats->tx_window_errors;  in rtl8365mb_stats_update()
1512 	spin_unlock(&mb->ports[port].stats_lock);  in rtl8365mb_stats_update()
1520 	struct realtek_priv *priv = p->priv;  in rtl8365mb_stats_poll()
1522 	rtl8365mb_stats_update(priv, p->index);  in rtl8365mb_stats_poll()
1524 	schedule_delayed_work(&p->mib_work, RTL8365MB_STATS_INTERVAL_JIFFIES);  in rtl8365mb_stats_poll()
1530 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_get_stats64()
1534 	mb = priv->chip_data;  in rtl8365mb_get_stats64()
1535 	p = &mb->ports[port];  in rtl8365mb_get_stats64()
1537 	spin_lock(&p->stats_lock);  in rtl8365mb_get_stats64()
1538 	memcpy(s, &p->stats, sizeof(*s));  in rtl8365mb_get_stats64()
1539 	spin_unlock(&p->stats_lock);  in rtl8365mb_get_stats64()
1544 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_stats_setup()
1547 	/* Per-chip global mutex to protect MIB counter access, since doing  in rtl8365mb_stats_setup()
1550 	mutex_init(&mb->mib_lock);  in rtl8365mb_stats_setup()
1552 	for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_stats_setup()
1553 		struct rtl8365mb_port *p = &mb->ports[i];  in rtl8365mb_stats_setup()
1555 		if (dsa_is_unused_port(priv->ds, i))  in rtl8365mb_stats_setup()
1558 		/* Per-port spinlock to protect the stats64 data */  in rtl8365mb_stats_setup()
1559 		spin_lock_init(&p->stats_lock);  in rtl8365mb_stats_setup()
1562 		 * up-to-date.  in rtl8365mb_stats_setup()
1564 		INIT_DELAYED_WORK(&p->mib_work, rtl8365mb_stats_poll);  in rtl8365mb_stats_setup()
1570 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_stats_teardown()
1573 	for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_stats_teardown()
1574 		struct rtl8365mb_port *p = &mb->ports[i];  in rtl8365mb_stats_teardown()
1576 		if (dsa_is_unused_port(priv->ds, i))  in rtl8365mb_stats_teardown()
1579 		cancel_delayed_work_sync(&p->mib_work);  in rtl8365mb_stats_teardown()
1588 	ret = regmap_read(priv->map, reg, val);  in rtl8365mb_get_and_clear_status_reg()
1592 	return regmap_write(priv->map, reg, *val);  in rtl8365mb_get_and_clear_status_reg()
1633 	for_each_set_bit(line, &line_changes, priv->num_ports) {  in rtl8365mb_irq()
1634 		int child_irq = irq_find_mapping(priv->irqdomain, line);  in rtl8365mb_irq()
1642 	dev_err(priv->dev, "failed to read interrupt status: %d\n", ret);  in rtl8365mb_irq()
1650 	/* The hardware doesn't support masking IRQs on a per-port basis */
1656 	irq_set_chip_data(irq, domain->host_data);  in rtl8365mb_irq_map()
1679 	return regmap_update_bits(priv->map, RTL8365MB_INTR_CTRL_REG,  in rtl8365mb_set_irq_enable()
1697 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_irq_setup()
1706 	intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller");  in rtl8365mb_irq_setup()
1708 		dev_err(priv->dev, "missing child interrupt-controller node\n");  in rtl8365mb_irq_setup()
1709 		return -EINVAL;  in rtl8365mb_irq_setup()
1715 		if (irq != -EPROBE_DEFER)  in rtl8365mb_irq_setup()
1716 			dev_err(priv->dev, "failed to get parent irq: %d\n",  in rtl8365mb_irq_setup()
1718 		ret = irq ? irq : -EINVAL;  in rtl8365mb_irq_setup()
1722 	priv->irqdomain = irq_domain_add_linear(intc, priv->num_ports,  in rtl8365mb_irq_setup()
1724 	if (!priv->irqdomain) {  in rtl8365mb_irq_setup()
1725 		dev_err(priv->dev, "failed to add irq domain\n");  in rtl8365mb_irq_setup()
1726 		ret = -ENOMEM;  in rtl8365mb_irq_setup()
1730 	for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_irq_setup()
1731 		virq = irq_create_mapping(priv->irqdomain, i);  in rtl8365mb_irq_setup()
1733 			dev_err(priv->dev,  in rtl8365mb_irq_setup()
1735 			ret = -EINVAL;  in rtl8365mb_irq_setup()
1754 		dev_err(priv->dev, "unsupported irq trigger type %u\n",  in rtl8365mb_irq_setup()
1756 		ret = -EINVAL;  in rtl8365mb_irq_setup()
1760 	ret = regmap_update_bits(priv->map, RTL8365MB_INTR_POLARITY_REG,  in rtl8365mb_irq_setup()
1772 	ret = regmap_write(priv->map, RTL8365MB_INTR_STATUS_REG,  in rtl8365mb_irq_setup()
1780 		dev_err(priv->dev, "failed to request irq: %d\n", ret);  in rtl8365mb_irq_setup()
1785 	mb->irq = irq;  in rtl8365mb_irq_setup()
1796 	free_irq(mb->irq, priv);  in rtl8365mb_irq_setup()
1797 	mb->irq = 0;  in rtl8365mb_irq_setup()
1800 	for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_irq_setup()
1801 		virq = irq_find_mapping(priv->irqdomain, i);  in rtl8365mb_irq_setup()
1805 	irq_domain_remove(priv->irqdomain);  in rtl8365mb_irq_setup()
1806 	priv->irqdomain = NULL;  in rtl8365mb_irq_setup()
1816 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_irq_teardown()
1820 	if (mb->irq) {  in rtl8365mb_irq_teardown()
1821 		free_irq(mb->irq, priv);  in rtl8365mb_irq_teardown()
1822 		mb->irq = 0;  in rtl8365mb_irq_teardown()
1825 	if (priv->irqdomain) {  in rtl8365mb_irq_teardown()
1826 		for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_irq_teardown()
1827 			virq = irq_find_mapping(priv->irqdomain, i);  in rtl8365mb_irq_teardown()
1831 		irq_domain_remove(priv->irqdomain);  in rtl8365mb_irq_teardown()
1832 		priv->irqdomain = NULL;  in rtl8365mb_irq_teardown()
1838 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_cpu_config()
1839 	struct rtl8365mb_cpu *cpu = &mb->cpu;  in rtl8365mb_cpu_config()
1843 	ret = regmap_update_bits(priv->map, RTL8365MB_CPU_PORT_MASK_REG,  in rtl8365mb_cpu_config()
1846 					    cpu->mask));  in rtl8365mb_cpu_config()
1850 	val = FIELD_PREP(RTL8365MB_CPU_CTRL_EN_MASK, cpu->enable ? 1 : 0) |  in rtl8365mb_cpu_config()
1851 	      FIELD_PREP(RTL8365MB_CPU_CTRL_INSERTMODE_MASK, cpu->insert) |  in rtl8365mb_cpu_config()
1852 	      FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_POSITION_MASK, cpu->position) |  in rtl8365mb_cpu_config()
1853 	      FIELD_PREP(RTL8365MB_CPU_CTRL_RXBYTECOUNT_MASK, cpu->rx_length) |  in rtl8365mb_cpu_config()
1854 	      FIELD_PREP(RTL8365MB_CPU_CTRL_TAG_FORMAT_MASK, cpu->format) |  in rtl8365mb_cpu_config()
1855 	      FIELD_PREP(RTL8365MB_CPU_CTRL_TRAP_PORT_MASK, cpu->trap_port & 0x7) |  in rtl8365mb_cpu_config()
1857 			 cpu->trap_port >> 3 & 0x1);  in rtl8365mb_cpu_config()
1858 	ret = regmap_write(priv->map, RTL8365MB_CPU_CTRL_REG, val);  in rtl8365mb_cpu_config()
1868 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_change_tag_protocol()
1872 	mb = priv->chip_data;  in rtl8365mb_change_tag_protocol()
1873 	cpu = &mb->cpu;  in rtl8365mb_change_tag_protocol()
1877 		cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;  in rtl8365mb_change_tag_protocol()
1878 		cpu->position = RTL8365MB_CPU_POS_AFTER_SA;  in rtl8365mb_change_tag_protocol()
1881 		cpu->format = RTL8365MB_CPU_FORMAT_8BYTES;  in rtl8365mb_change_tag_protocol()
1882 		cpu->position = RTL8365MB_CPU_POS_BEFORE_CRC;  in rtl8365mb_change_tag_protocol()
1884 	/* The switch also supports a 4-byte format, similar to rtl4a but with  in rtl8365mb_change_tag_protocol()
1885 	 * the same 0x04 8-bit version and probably 8-bit port source/dest.  in rtl8365mb_change_tag_protocol()
1890 		return -EPROTONOSUPPORT;  in rtl8365mb_change_tag_protocol()
1898 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_switch_init()
1903 	ci = mb->chip_info;  in rtl8365mb_switch_init()
1905 	/* Do any chip-specific init jam before getting to the common stuff */  in rtl8365mb_switch_init()
1906 	if (ci->jam_table) {  in rtl8365mb_switch_init()
1907 		for (i = 0; i < ci->jam_size; i++) {  in rtl8365mb_switch_init()
1908 			ret = regmap_write(priv->map, ci->jam_table[i].reg,  in rtl8365mb_switch_init()
1909 					   ci->jam_table[i].val);  in rtl8365mb_switch_init()
1917 		ret = regmap_write(priv->map, rtl8365mb_init_jam_common[i].reg,  in rtl8365mb_switch_init()
1930 	priv->write_reg_noack(priv, RTL8365MB_CHIP_RESET_REG,  in rtl8365mb_reset_chip()
1933 	/* Realtek documentation says the chip needs 1 second to reset. Sleep  in rtl8365mb_reset_chip()
1937 	return regmap_read_poll_timeout(priv->map, RTL8365MB_CHIP_RESET_REG, val,  in rtl8365mb_reset_chip()
1944 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_setup()
1951 	mb = priv->chip_data;  in rtl8365mb_setup()
1952 	cpu = &mb->cpu;  in rtl8365mb_setup()
1956 		dev_err(priv->dev, "failed to reset chip: %d\n", ret);  in rtl8365mb_setup()
1960 	/* Configure switch to vendor-defined initial state */  in rtl8365mb_setup()
1963 		dev_err(priv->dev, "failed to initialize switch: %d\n", ret);  in rtl8365mb_setup()
1969 	if (ret == -EPROBE_DEFER)  in rtl8365mb_setup()
1972 		dev_info(priv->dev, "no interrupt support\n");  in rtl8365mb_setup()
1975 	dsa_switch_for_each_cpu_port(cpu_dp, priv->ds) {  in rtl8365mb_setup()
1976 		cpu->mask |= BIT(cpu_dp->index);  in rtl8365mb_setup()
1978 		if (cpu->trap_port == RTL8365MB_MAX_NUM_PORTS)  in rtl8365mb_setup()
1979 			cpu->trap_port = cpu_dp->index;  in rtl8365mb_setup()
1981 	cpu->enable = cpu->mask > 0;  in rtl8365mb_setup()
1987 	for (i = 0; i < priv->num_ports; i++) {  in rtl8365mb_setup()
1988 		struct rtl8365mb_port *p = &mb->ports[i];  in rtl8365mb_setup()
1990 		if (dsa_is_unused_port(priv->ds, i))  in rtl8365mb_setup()
1994 		ret = rtl8365mb_port_set_isolation(priv, i, cpu->mask);  in rtl8365mb_setup()
2007 		rtl8365mb_port_stp_state_set(priv->ds, i, BR_STATE_DISABLED);  in rtl8365mb_setup()
2009 		/* Set up per-port private data */  in rtl8365mb_setup()
2010 		p->priv = priv;  in rtl8365mb_setup()
2011 		p->index = i;  in rtl8365mb_setup()
2014 	ret = rtl8365mb_port_change_mtu(ds, cpu->trap_port, ETH_DATA_LEN);  in rtl8365mb_setup()
2018 	if (priv->setup_interface) {  in rtl8365mb_setup()
2019 		ret = priv->setup_interface(ds);  in rtl8365mb_setup()
2021 			dev_err(priv->dev, "could not set up MDIO bus\n");  in rtl8365mb_setup()
2040 	struct realtek_priv *priv = ds->priv;  in rtl8365mb_teardown()
2075 	struct rtl8365mb *mb = priv->chip_data;  in rtl8365mb_detect()
2081 	ret = rtl8365mb_get_chip_id_and_ver(priv->map, &chip_id, &chip_ver);  in rtl8365mb_detect()
2083 		dev_err(priv->dev, "failed to read chip id and version: %d\n",  in rtl8365mb_detect()
2091 		if (ci->chip_id == chip_id && ci->chip_ver == chip_ver) {  in rtl8365mb_detect()
2092 			mb->chip_info = ci;  in rtl8365mb_detect()
2097 	if (!mb->chip_info) {  in rtl8365mb_detect()
2098 		dev_err(priv->dev,  in rtl8365mb_detect()
2101 		return -ENODEV;  in rtl8365mb_detect()
2104 	dev_info(priv->dev, "found an %s switch\n", mb->chip_info->name);  in rtl8365mb_detect()
2106 	priv->num_ports = RTL8365MB_MAX_NUM_PORTS;  in rtl8365mb_detect()
2107 	mb->priv = priv;  in rtl8365mb_detect()
2108 	mb->cpu.trap_port = RTL8365MB_MAX_NUM_PORTS;  in rtl8365mb_detect()
2109 	mb->cpu.insert = RTL8365MB_CPU_INSERT_TO_ALL;  in rtl8365mb_detect()
2110 	mb->cpu.position = RTL8365MB_CPU_POS_AFTER_SA;  in rtl8365mb_detect()
2111 	mb->cpu.rx_length = RTL8365MB_CPU_RXLEN_64BYTES;  in rtl8365mb_detect()
2112 	mb->cpu.format = RTL8365MB_CPU_FORMAT_8BYTES;  in rtl8365mb_detect()
2178 MODULE_AUTHOR("Alvin Šipraga <alsi@bang-olufsen.dk>");
2179 MODULE_DESCRIPTION("Driver for RTL8365MB-VC ethernet switch");