Lines Matching +full:data +full:- +full:mirror
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
68 return regmap_read(priv->regmap, reg, val); in qca8k_read()
73 return regmap_write(priv->regmap, reg, val); in qca8k_write()
78 return regmap_update_bits(priv->regmap, reg, mask, write_val); in qca8k_rmw()
90 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
91 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
92 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
93 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
94 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
95 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
96 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
108 return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0, in qca8k_busy_wait()
118 ret = regmap_bulk_read(priv->regmap, QCA8K_REG_ATU_DATA0, reg, in qca8k_fdb_read()
123 /* vid - 83:72 */ in qca8k_fdb_read()
124 fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]); in qca8k_fdb_read()
125 /* aging - 67:64 */ in qca8k_fdb_read()
126 fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]); in qca8k_fdb_read()
127 /* portmask - 54:48 */ in qca8k_fdb_read()
128 fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]); in qca8k_fdb_read()
129 /* mac - 47:0 */ in qca8k_fdb_read()
130 fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]); in qca8k_fdb_read()
131 fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]); in qca8k_fdb_read()
132 fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]); in qca8k_fdb_read()
133 fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]); in qca8k_fdb_read()
134 fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]); in qca8k_fdb_read()
135 fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]); in qca8k_fdb_read()
145 /* vid - 83:72 */ in qca8k_fdb_write()
147 /* aging - 67:64 */ in qca8k_fdb_write()
149 /* portmask - 54:48 */ in qca8k_fdb_write()
151 /* mac - 47:0 */ in qca8k_fdb_write()
160 regmap_bulk_write(priv->regmap, QCA8K_REG_ATU_DATA0, reg, in qca8k_fdb_write()
194 return -1; in qca8k_fdb_access()
205 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging); in qca8k_fdb_next()
218 mutex_lock(&priv->reg_mutex); in qca8k_fdb_add()
220 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); in qca8k_fdb_add()
221 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_add()
231 mutex_lock(&priv->reg_mutex); in qca8k_fdb_del()
233 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); in qca8k_fdb_del()
234 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_del()
241 mutex_lock(&priv->reg_mutex); in qca8k_fdb_flush()
242 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1); in qca8k_fdb_flush()
243 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_flush()
252 mutex_lock(&priv->reg_mutex); in qca8k_fdb_search_and_insert()
255 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); in qca8k_fdb_search_and_insert()
265 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); in qca8k_fdb_search_and_insert()
276 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); in qca8k_fdb_search_and_insert()
279 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_search_and_insert()
289 mutex_lock(&priv->reg_mutex); in qca8k_fdb_search_and_del()
292 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1); in qca8k_fdb_search_and_del()
302 ret = -EINVAL; in qca8k_fdb_search_and_del()
306 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1); in qca8k_fdb_search_and_del()
318 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1); in qca8k_fdb_search_and_del()
321 mutex_unlock(&priv->reg_mutex); in qca8k_fdb_search_and_del()
352 return -ENOMEM; in qca8k_vlan_access()
370 mutex_lock(&priv->reg_mutex); in qca8k_vlan_add()
391 mutex_unlock(&priv->reg_mutex); in qca8k_vlan_add()
402 mutex_lock(&priv->reg_mutex); in qca8k_vlan_del()
434 mutex_unlock(&priv->reg_mutex); in qca8k_vlan_del()
443 mutex_lock(&priv->reg_mutex); in qca8k_mib_init()
444 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, in qca8k_mib_init()
455 ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP); in qca8k_mib_init()
462 mutex_unlock(&priv->reg_mutex); in qca8k_mib_init()
475 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); in qca8k_port_set_status()
477 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask); in qca8k_port_set_status()
481 uint8_t *data) in qca8k_get_strings() argument
483 struct qca8k_priv *priv = ds->priv; in qca8k_get_strings()
489 for (i = 0; i < priv->info->mib_count; i++) in qca8k_get_strings()
490 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name, in qca8k_get_strings()
495 uint64_t *data) in qca8k_get_ethtool_stats() argument
497 struct qca8k_priv *priv = ds->priv; in qca8k_get_ethtool_stats()
503 if (priv->mgmt_master && priv->info->ops->autocast_mib && in qca8k_get_ethtool_stats()
504 priv->info->ops->autocast_mib(ds, port, data) > 0) in qca8k_get_ethtool_stats()
507 for (i = 0; i < priv->info->mib_count; i++) { in qca8k_get_ethtool_stats()
509 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset; in qca8k_get_ethtool_stats()
515 if (mib->size == 2) { in qca8k_get_ethtool_stats()
521 data[i] = val; in qca8k_get_ethtool_stats()
522 if (mib->size == 2) in qca8k_get_ethtool_stats()
523 data[i] |= (u64)hi << 32; in qca8k_get_ethtool_stats()
529 struct qca8k_priv *priv = ds->priv; in qca8k_get_sset_count()
534 return priv->info->mib_count; in qca8k_get_sset_count()
541 struct qca8k_priv *priv = ds->priv; in qca8k_set_mac_eee()
545 mutex_lock(&priv->reg_mutex); in qca8k_set_mac_eee()
550 if (eee->eee_enabled) in qca8k_set_mac_eee()
557 mutex_unlock(&priv->reg_mutex); in qca8k_set_mac_eee()
571 struct qca8k_priv *priv = ds->priv; in qca8k_port_configure_learning()
574 return regmap_set_bits(priv->regmap, in qca8k_port_configure_learning()
578 return regmap_clear_bits(priv->regmap, in qca8k_port_configure_learning()
586 struct qca8k_priv *priv = ds->priv; in qca8k_port_stp_state_set()
602 learning = dp->learning; in qca8k_port_stp_state_set()
605 learning = dp->learning; in qca8k_port_stp_state_set()
623 return -EINVAL; in qca8k_port_pre_bridge_flags()
649 struct qca8k_priv *priv = ds->priv; in qca8k_port_bridge_join()
653 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; in qca8k_port_bridge_join()
664 ret = regmap_set_bits(priv->regmap, in qca8k_port_bridge_join()
683 struct qca8k_priv *priv = ds->priv; in qca8k_port_bridge_leave()
686 cpu_port = dsa_to_port(ds, port)->cpu_dp->index; in qca8k_port_bridge_leave()
696 regmap_clear_bits(priv->regmap, in qca8k_port_bridge_leave()
710 struct qca8k_priv *priv = ds->priv; in qca8k_port_fast_age()
712 mutex_lock(&priv->reg_mutex); in qca8k_port_fast_age()
714 mutex_unlock(&priv->reg_mutex); in qca8k_port_fast_age()
719 struct qca8k_priv *priv = ds->priv; in qca8k_set_ageing_time()
732 return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL, in qca8k_set_ageing_time()
740 struct qca8k_priv *priv = ds->priv; in qca8k_port_enable()
743 priv->port_enabled_map |= BIT(port); in qca8k_port_enable()
753 struct qca8k_priv *priv = ds->priv; in qca8k_port_disable()
756 priv->port_enabled_map &= ~BIT(port); in qca8k_port_disable()
761 struct qca8k_priv *priv = ds->priv; in qca8k_port_change_mtu()
778 if (priv->port_enabled_map & BIT(0)) in qca8k_port_change_mtu()
781 if (priv->port_enabled_map & BIT(6)) in qca8k_port_change_mtu()
788 if (priv->port_enabled_map & BIT(0)) in qca8k_port_change_mtu()
791 if (priv->port_enabled_map & BIT(6)) in qca8k_port_change_mtu()
817 struct qca8k_priv *priv = ds->priv; in qca8k_port_fdb_add()
827 struct qca8k_priv *priv = ds->priv; in qca8k_port_fdb_del()
837 dsa_fdb_dump_cb_t *cb, void *data) in qca8k_port_fdb_dump() argument
839 struct qca8k_priv *priv = ds->priv; in qca8k_port_fdb_dump()
845 mutex_lock(&priv->reg_mutex); in qca8k_port_fdb_dump()
846 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) { in qca8k_port_fdb_dump()
850 ret = cb(_fdb.mac, _fdb.vid, is_static, data); in qca8k_port_fdb_dump()
854 mutex_unlock(&priv->reg_mutex); in qca8k_port_fdb_dump()
863 struct qca8k_priv *priv = ds->priv; in qca8k_port_mdb_add()
864 const u8 *addr = mdb->addr; in qca8k_port_mdb_add()
865 u16 vid = mdb->vid; in qca8k_port_mdb_add()
878 struct qca8k_priv *priv = ds->priv; in qca8k_port_mdb_del()
879 const u8 *addr = mdb->addr; in qca8k_port_mdb_del()
880 u16 vid = mdb->vid; in qca8k_port_mdb_del()
889 struct dsa_mall_mirror_tc_entry *mirror, in qca8k_port_mirror_add() argument
892 struct qca8k_priv *priv = ds->priv; in qca8k_port_mirror_add()
897 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in qca8k_port_mirror_add()
898 return -EEXIST; in qca8k_port_mirror_add()
900 ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val); in qca8k_port_mirror_add()
904 /* QCA83xx can have only one port set to mirror mode. in qca8k_port_mirror_add()
906 * When no mirror port is set, the values is set to 0xF in qca8k_port_mirror_add()
909 if (monitor_port != 0xF && monitor_port != mirror->to_local_port) in qca8k_port_mirror_add()
910 return -EEXIST; in qca8k_port_mirror_add()
914 mirror->to_local_port); in qca8k_port_mirror_add()
915 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, in qca8k_port_mirror_add()
928 ret = regmap_update_bits(priv->regmap, reg, val, val); in qca8k_port_mirror_add()
932 /* Track mirror port for tx and rx to decide when the in qca8k_port_mirror_add()
933 * mirror port has to be disabled. in qca8k_port_mirror_add()
936 priv->mirror_rx |= BIT(port); in qca8k_port_mirror_add()
938 priv->mirror_tx |= BIT(port); in qca8k_port_mirror_add()
944 struct dsa_mall_mirror_tc_entry *mirror) in qca8k_port_mirror_del() argument
946 struct qca8k_priv *priv = ds->priv; in qca8k_port_mirror_del()
950 if (mirror->ingress) { in qca8k_port_mirror_del()
958 ret = regmap_clear_bits(priv->regmap, reg, val); in qca8k_port_mirror_del()
962 if (mirror->ingress) in qca8k_port_mirror_del()
963 priv->mirror_rx &= ~BIT(port); in qca8k_port_mirror_del()
965 priv->mirror_tx &= ~BIT(port); in qca8k_port_mirror_del()
967 /* No port set to send packet to mirror port. Disable mirror port */ in qca8k_port_mirror_del()
968 if (!priv->mirror_rx && !priv->mirror_tx) { in qca8k_port_mirror_del()
970 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, in qca8k_port_mirror_del()
976 dev_err(priv->dev, "Failed to del mirror port from %d", port); in qca8k_port_mirror_del()
983 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_filtering()
1003 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in qca8k_port_vlan_add()
1004 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in qca8k_port_vlan_add()
1005 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_add()
1008 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged); in qca8k_port_vlan_add()
1010 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret); in qca8k_port_vlan_add()
1017 QCA8K_EGREES_VLAN_PORT(port, vlan->vid)); in qca8k_port_vlan_add()
1022 QCA8K_PORT_VLAN_CVID(vlan->vid) | in qca8k_port_vlan_add()
1023 QCA8K_PORT_VLAN_SVID(vlan->vid)); in qca8k_port_vlan_add()
1032 struct qca8k_priv *priv = ds->priv; in qca8k_port_vlan_del()
1035 ret = qca8k_vlan_del(priv, port, vlan->vid); in qca8k_port_vlan_del()
1037 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret); in qca8k_port_vlan_del()
1053 dsa_lag_foreach_port(dp, ds->dst, &lag) in qca8k_lag_can_offload()
1063 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { in qca8k_lag_can_offload()
1069 if (info->hash_type != NETDEV_LAG_HASH_L2 && in qca8k_lag_can_offload()
1070 info->hash_type != NETDEV_LAG_HASH_L23) { in qca8k_lag_can_offload()
1084 struct qca8k_priv *priv = ds->priv; in qca8k_lag_setup_hash()
1089 switch (info->hash_type) { in qca8k_lag_setup_hash()
1099 return -EOPNOTSUPP; in qca8k_lag_setup_hash()
1103 dsa_lags_foreach_id(i, ds->dst) in qca8k_lag_setup_hash()
1104 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) { in qca8k_lag_setup_hash()
1117 priv->lag_hash_mode = hash; in qca8k_lag_setup_hash()
1118 } else if (priv->lag_hash_mode != hash) { in qca8k_lag_setup_hash()
1120 return -EOPNOTSUPP; in qca8k_lag_setup_hash()
1123 return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL, in qca8k_lag_setup_hash()
1130 struct qca8k_priv *priv = ds->priv; in qca8k_lag_refresh_portmap()
1134 /* DSA LAG IDs are one-based, hardware is zero-based */ in qca8k_lag_refresh_portmap()
1135 id = lag.id - 1; in qca8k_lag_refresh_portmap()
1138 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val); in qca8k_lag_refresh_portmap()
1151 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, in qca8k_lag_refresh_portmap()
1159 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val); in qca8k_lag_refresh_portmap()
1189 return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), in qca8k_lag_refresh_portmap()
1203 return -EOPNOTSUPP; in qca8k_port_lag_join()
1224 if (!priv->info) in qca8k_read_switch_id()
1225 return -ENODEV; in qca8k_read_switch_id()
1229 return -ENODEV; in qca8k_read_switch_id()
1232 if (id != priv->info->id) { in qca8k_read_switch_id()
1233 dev_err(priv->dev, in qca8k_read_switch_id()
1235 id, priv->info->id); in qca8k_read_switch_id()
1236 return -ENODEV; in qca8k_read_switch_id()
1239 priv->switch_id = id; in qca8k_read_switch_id()
1242 priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val); in qca8k_read_switch_id()