Lines Matching full:smi
3 * Marvell 88E6xxx System Management Interface (SMI) support
11 #include "smi.h"
13 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
14 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
17 * is the only device connected to the SMI master. In this mode it responds to
18 * all 32 possible SMI addresses, and thus maps directly the internal devices.
21 * multiple devices to share the SMI interface. In this mode it responds to only
22 * 2 registers, used to indirectly access the internal SMI devices.
25 * configuration, and the device responds to 16 of the 32 SMI
26 * addresses, allowing two to coexist on the same SMI interface.
105 /* Offset 0x00: SMI Command Register
106 * Offset 0x01: SMI Data Register