227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)  in mt7530_write()  function
297 	mt7530_write(priv, MT7530_ATC, val);  in mt7530_fdb_cmd()
373 		mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);  in mt7530_fdb_write()
528 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
533 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
537 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
542 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
548 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
556 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
562 		mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
569 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
576 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
579 	mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);  in mt7531_pll_setup()
582 	mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);  in mt7531_pll_setup()
587 	mt7530_write(priv, MT7531_PLLGP_CR0, val);  in mt7531_pll_setup()
591 	mt7530_write(priv, MT7531_PLLGP_EN, val);  in mt7531_pll_setup()
600 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);  in mt7530_mib_reset()
601 	mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);  in mt7530_mib_reset()
908 	mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit));  in mt7530_set_ageing_time()
954 		mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);  in mt7530_setup_port5()
974 		mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);  in mt7530_setup_port5()
983 		mt7530_write(priv, MT7530_P5RGMIITXCR,  in mt7530_setup_port5()
987 		mt7530_write(priv, MT7530_IO_DRV_CR,  in mt7530_setup_port5()
991 	mt7530_write(priv, MT7530_MHWTRAP, val);  in mt7530_setup_port5()
1032 	mt7530_write(priv, MT7530_PVC_P(port),  in mt753x_cpu_port_enable()
1053 	mt7530_write(priv, MT7530_PCR_P(port),  in mt753x_cpu_port_enable()
1309 		mt7530_write(priv, MT7530_PCR_P(cpu_dp->index),  in mt7530_port_set_vlan_unaware()
1311 		mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG  in mt7530_port_set_vlan_unaware()
1535 	mt7530_write(priv, MT7530_VTCR, val);  in mt7530_vlan_cmd()
1591 	mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_add()
1630 		mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_hw_vlan_del()
1632 		mt7530_write(priv, MT7530_VAWD1, 0);  in mt7530_hw_vlan_del()
1633 		mt7530_write(priv, MT7530_VAWD2, 0);  in mt7530_hw_vlan_del()
1668 	mt7530_write(priv, MT7530_VAWD1, val);  in mt7530_setup_vlan0()
1787 	mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_add()
1797 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_add()
1816 	mt7530_write(priv, MT7530_PCR_P(port), val);  in mt753x_port_mirror_del()
1821 		mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);  in mt753x_port_mirror_del()
1917 	mt7530_write(priv, MT7530_LED_GPIO_OE, 0);  in mt7530_setup_gpio()
1918 	mt7530_write(priv, MT7530_LED_GPIO_DIR, 0);  in mt7530_setup_gpio()
1919 	mt7530_write(priv, MT7530_LED_IO_MODE, 0);  in mt7530_setup_gpio()
2272 	mt7530_write(priv, MT7530_SYS_CTRL,  in mt7530_setup()
2280 		mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),  in mt7530_setup()
2291 	mt7530_write(priv, MT7530_MHWTRAP, val);  in mt7530_setup()
2480 		mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK);  in mt7531_setup()
2483 	mt7530_write(priv, MT7530_SYS_CTRL,  in mt7531_setup()
2681 	mt7530_write(priv, MT7531_CLKGEN_CTRL, val);  in mt7531_rgmii_setup()
2815 		mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);  in mt753x_phylink_mac_config()
2922 	mt7530_write(priv, MT7530_PMCR_P(port),  in mt7531_cpu_port_config()
2937 	mt7530_write(priv, MT7530_PMCR_P(port),  in mt7988_cpu_port_config()
3106 	mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST);  in mt7988_setup()